600 Series Chipset Family On-Package Platform Controller Hub
Datasheet, Volume 1 of 2
FIVR
PCH integrates multiple voltage rails onto the PCH in order to reduce BOM costs for the platform and to enable additional voltage level features.
These internal FIVRs will generate VCC_VNNEXT_1P05 and VCC_V1P05EXT_1P05. External bypass VRs can be used during light load conditions for these rails and external bypass VRs are optional.
PCH Platform Voltage Rails
| Power Rail | Voltage | Description |
|---|---|---|
| VCCIN_AUX | 1.65 V or 1.8 V - Active 1.10 V - Retention OFF - Idle States | PCH FIVR Input rail |
| VCCPRIM_1P8 | 1.8 V | Primary well supply |
| VCCDSW_3P3 | 3.3 V | Deep sleep well supply, 3.3 V |
| VCCPRIM_3P3 | 3.3 V | Primary well supply, 3.3 V |
| VCCRTC | 3.3 V | RTC supply |
| VCC_V1P05EXT_1P05 (Optional) | 1.05 V | Used during light load conditions |
| VCC_VNNEXT_1P05 (Optional) | 0.78 V 1.05 V | Used during light load conditions |
VCCIN_AUX
VCCIN_AUX is the input rail to FIVR. During the deep S0ix states and Sx states, the input rail to the FIVRs can be disabled. This will be done by driving the CORE_VID values to '00.
VCCIN_AUX powergood during initial reset is tied into the RSMRST# signal, requiring that the FIVR input voltage rail is stable in the same window as the other SLP_SUS# rails.
To support dynamic switching during run time of the input VR, CORE_VID[1:0] pins are driven out from PCH.
VCCIN_AUX Control - CORE_VID Pins
The CORE_VID pins are used to control the VCCIN_AUX rail.
| SLP_SUS# | CORE_VID1 | CORE_VID0 | SLP_S0# | CPU Requirement | VCCIN_AUX Voltage | Comments |
|---|---|---|---|---|---|---|
| 0 | X | X | X | OFF | OFF | FIVR Input is OFF |
| 1 | 0 | 0 | 0 | VCCIN_AUX = 0 | 0 V | Typically used during S0ix and Sx states. |
| 1 | 0 | 1 | 1 | VCCIN_AUX = 0 | 1.10 V | Retention FIVR voltage, no VCCIN_AUX FIVRs active in CPU. |
| 1 | 1 | 0 | 1 | VCCIN_AUX = 1.65 V | 1.65 V | Low Current Mode Voltage 1.65 V |
| 1 | 1 | 1 | 1 | VCCIN_AUX = 1.8 V | 1.8 V | High Current Mode Voltage 1.8 V |
The default value for CORE_VID1/0 is 2'b11 (signaling 1.8 V). VCCIN_AUX configurations are specified through VCCIN_AUX_CFG1 & CFG2 registers. In a resume from 0 V, the field in VCCIN_AUX_CFG2 will specify the time to resume to 1.8 V.
External Bypass Rails
Both VCC_VNNEXT_1P05 and VCC_V1P05EXT_1P05 rails have the ability to operate with an external bypass voltage regulators. These rails are always on and must be come up after the 1.8 V rail has been brought up. These pins can be left unconnected when external bypass VRs not connected.
VCC_V1P05EXT_1P05 rail supports 1.05V only.
VCC_VNNEXT_1P05 rail can operate at two levels and SLP_S3# can be used as control signal to switch between two voltage levels.
| SLP_S3# | VCC_VNNEXT_1P05 |
|---|---|
| 1 | 0.78 V |
| 0 | 1.05 V |
Below FIVR registers should be configured properly as per system design.
- VCCIN_AUX_CFG1
- VCCIN_AUX_CFG2
- EXT_RAIL_CONFIG
- EXT_V1P05_VR_CONFIG
- EXT_VNN_VR_CONFIG