600 Series Chipset Family On-Package Platform Controller Hub
Datasheet, Volume 1 of 2
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Signals Description
Signal Name | Type | Description |
---|---|---|
PCIE9_TXP / UFS10_TXP | O | UFS port 1 lane 0 transmit signal |
PCIE9_TXN / UFS10_TXN | O | UFS port 1 lane 0 transmit signal |
PCIE9_RXP / UFS10_RXP | I | UFS port 1 lane 0 receive signal |
PCIE9_RXN / UFS10_RXN | I | UFS port 1 lane 0 receive signal |
PCIE10_TXP / UFS11_TXP | O | UFS port 1 lane 1 transmit signal |
PCIE10_TXN / UFS11_TXN | O | UFS port 1 lane 1 transmit signal |
PCIE10_RXP / UFS11_RXP | I | UFS port 1 lane 1 receive signal |
PCIE10_RXN / UFS11_RXN | I | UFS port 1 lane 1 receive signal |
CLKOUT_PCIE_N4 / UFS_REF_CLK | O | UFS reference clock signal (19.2 MHz). Note: Level shifter is required for this signal to meet UFS specification. |
UFS_RESET# | O | Unconnected pin (UFS device reset should be connected to a level shifted version of platform reset signal). |