PCH-P

The 12 Flexible HSIO Lanes [11:0] on PCH-P support the following configurations:

1. Up to twelve PCIe* Lanes
   • A maximum of six PCIe* Root Ports (or devices) can be enabled
     • When a GbE Port is enabled, the maximum number of PCIe* Root Ports (or devices) that can be enabled reduces based off the following:

       --> Max PCIe* Root Ports (or devices) = 6 - GbE (0 or 1)

   • PCIe* Lanes 1-4 (PCIe* Controller #1), 5-8 (PCIe* Controller #2), and 9-12 (PCIe* Controller #3) must be individually configured.
2. Up to four USB 3.2 Gen 1x1/2x1 Lanes
   • A maximum of four USB 3.2 Gen 1x1/2x1 Ports (or devices) can be enabled.
   • USB 3.2  Gen 1x1 = 5 GT/s
   • USB 3.2  Gen 2x1 = 10 GT/s
3. Up to two SATA Lanes
   • A maximum of two SATA Ports (or devices) can be enabled.
4. Up to three GbE Lanes
   • A maximum of one GbE Port (or device) can be enabled.
5. Supports two Lane 1x2 Universal Flash Storage (UFS)
6. For unused USB 3.2/PCIe* Combo Lanes, the unused lanes must be statically assigned to PCIe* or USB 3.2 via the USB 3.2/PCIe* Combo Port Soft Straps discussed in the SPI Programming Guide and through the Intel Flash Image Tool (FIT) tool.