600 Series Chipset Family On-Package Platform Controller Hub
Datasheet, Volume 1 of 2
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PCI Host Interface
The ISH provides access to PCI configuration space via a PCI Bridge. Type 0 Configuration Cycles from the host are directed to the PCI configuration space.
MMIO Space
A memory-mapped Base Address Register (BAR0) with a set of functional memory-mapped registers is accessible to the host via the Bridge. These registers are owned by the driver running on the Host OS.
The bridge also supports a second BAR (BAR1) that is an alias of the PCI Configuration space. It is used only in ACPI mode (that is, when the PCI configuration space is hidden).
DMA Controller
The DMA controller supports up to 64-bit addressing.
PCI Interrupts
The PCI bridge supports standard PCI interrupts, delivered using IRQx to the system IOAPIC and not using an MSI to the host CPU.
PCI Power Management
PME is not supported in ISH.