Intel® Core™ Ultra 200S and 200HX Series Processors
Datasheet, Volume 1 of 2
| ID | Date | Version | Classification |
|---|---|---|---|
| 832586 | 03/11/2025 | Public |
A newer version of this document is available. Customers should click here to go to the newest version.
Legal Disclaimer
Revision History
Introduction
Processor and Device IDs
Package Mechanical Specifications
Memory Mapping
Security Technologies
Intel® Virtualization Technology (Intel® VT)
Instructions Set Enhancements
Platform Environmental Control Interface (PECI)
Intel GMM and Neural Network Accelerator (Intel GNA 3.5)
Intel® Neural Processing Unit (Intel® NPU)
Power Management
Power Delivery
Electrical Specifications
Thermal Management
Clock Topology
Memory
USB Type-C* Sub System
Intel® Volume Management Device (Intel® VMD) Technology
PCI Express* (PCIe*)
Graphics
Display
General Purpose Input and Output
Interrupt Timer Subsystem (ITSS)
Direct Media Interface (DMI)
Direct Enhanced Serial Peripheral Interface (Direct eSPI)
Testability and Monitoring
Miscellaneous Signals
Security Technologies
Intel® Converged Boot Guard and Intel® TXT
Crypto Acceleration Instructions
Intel® Secure Key
Execute Disable Bit
Intel® Supervisor Mode Execution Prevention (Intel® SMEP)
Intel® Supervisor Mode Access Prevention (Intel® SMAP)
User Mode Instruction Prevention (UMIP)
Read Processor ID (RDPID)
Intel® Total Memory Encryption - Multi-Key
Control-flow Enforcement Technology (Intel® CET)
KeyLocker Technology
Intel® System Resources Defense and Intel® System Security Report
BIOS Guard
Intel® Platform Trust Technology
Linear Address Space Separation (LASS)
Security Firmware Engines
Power and Performance Technologies
Intel® Thread Director
Intel® Smart Cache Technology
P-core and E-core Level 0, Level 1 and Level 2 Caches
Ring Interconnect
Intel® Hybrid Technology
Intel® Turbo Boost Technology 2.0
Intel® Turbo Boost Max Technology 3.0
Intel® Adaptive Boost Technology
Intel® System Agent Enhanced SpeedStep ® Technology
Enhanced Intel SpeedStep® Technology
Intel® Thermal Velocity Boost (Intel® TVB)
Intel® Speed Shift Technology
Intel® Advanced Vector Extensions 2 (Intel® AVX2)
Intel® 64 Architecture x2APIC
Intel® Dynamic Tuning Technology (Intel® DTT)
Cache Line Write Back (CLWB)
User Mode Wait Instructions
Thermal Management Features
Adaptive Thermal Monitor
Digital Thermal Sensor
PROCHOT# Signal
PROCHOT Output Only
Bi-Directional PROCHOT#
PROCHOT Demotion Algorithm
Voltage Regulator Protection using PROCHOT#
Thermal Solution Design and PROCHOT# Behavior
Low-Power States and PROCHOT# Behavior
THERMTRIP# Signal
Critical Temperature Detection
Software Controlled Clock Modulation (On-Demand Mode)
System Memory Interface
Processor SKU Support Matrix
Supported Memory Modules and Devices
System Memory Timing Support
Memory Controller (MC)
System Memory Controller Organization Mode
System Memory Frequency
Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)
Data Scrambling
ECC H-Matrix Syndrome Codes
Data Swapping
DDR I/O Interleaving
DRAM Clock Generation
DRAM Reference Voltage Generation
Data Swizzling
Post Package Repair (PPR)
Data Swapping
By default, the processor supports on-board data swapping in two manners (for all segments and DRAM technologies):
- Bit swapping is allowed within each Byte for all DDR technologies.
- DDR5 x32 sub-channels can be swizzle within their x64 MC.
- DDR5: Byte swapping is allowed within each x32 Channel.
- ECC bits swap is allowed within ECC byte/nibble: DDR5 ECC[3..0].