Processor SKU Support Matrix

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Introduction
Processor and Device IDs
Package Mechanical Specifications
- Package Mechanical Attributes
- Package Storage Specifications
Memory Mapping
- Functional Description
- Memory Map
  - Boot Block Update Scheme
Security Technologies
Intel® Virtualization Technology (Intel® VT)
Instructions Set Enhancements
- CMPccXADD
- LAM
Platform Environmental Control Interface (PECI)
- PECI Bus Architecture
Intel GMM and Neural Network Accelerator (Intel GNA 3.5)
Intel® Neural Processing Unit (Intel® NPU)
- Functional Description
  - Processor Subsystem
  - NCE Subsystem
Power Management
Power Delivery
Electrical Specifications
- Processor Power Rails
  - Power and Ground Pins
  - VCC Voltage Identification (VID)
- DC Specifications
  - Processor Power Rails DC Specifications
  - Processor Interfaces DC Specifications
Thermal Management
Clock Topology
- Integrated Reference Clock PLL
- Processor Clocking Signals
Memory
USB Type-C* Sub System
Intel® Volume Management Device (Intel® VMD) Technology
PCI Express* (PCIe*)
Graphics
- Processor Graphics
  - Media Support (Intel® QuickSync and Clear Video Technology HD)
  - Graphics Core Cache
- Platform Graphics Hardware Feature
  - Hybrid Graphics
Display
General Purpose Input and Output
- Functional Description
- Signal Description
Interrupt Timer Subsystem (ITSS)
- Feature Overview
- Functional Description
Direct Media Interface (DMI)
Direct Enhanced Serial Peripheral Interface (Direct eSPI)
- Functional Description
- Signal Description
Testability and Monitoring
- Signal Description
- I/O Signal Planes and States
Miscellaneous Signals
- Signal Description
- Ground and Reserved Signals

DDR Support Matrix Table

Technology	DDR5
Processor	S, HX	S, HX
Configuration	1DPC ¹	2DPC ⁷
Maximum Frequency [MT/s]	S-Processor⁵: UDIMM/SODIMM 5600 CUDIMM/CSODIMM 6400^{9, 12} HX-Processor⁵ : SODIMM 5600 CSODIMM 6400^{9, 10}	S-Processor UDIMM/CUDIMM : 1DIMM 1R/2R 5600 2DIMM 1R 4800/2R 4400⁸ HX-Processor SODIMM/CSODIMM: 1DIMM 1R/2R 4800 2DIMM 1R 4800 / 2R 4400⁸
VDDQ [V]⁴	5, 1.1	5, 1.1
VDD2 [V] ⁴	1.1	1.1
Maximum RPC ²	2	4
Die Density [Gb]	16, 24, 32	16, 24, 32
Ballmap Mode	IL	IL
Notes: 1DPC refers to when only 1DIMM slot per channel is routed. RPC = Rank Per Channel VDD2 is Processor and DRAM voltage, and VDDQ is DRAM voltage. 5V is DIMM voltage, 1.1V is DRAM input voltage. Speed is QDF dependant. DDR5 ECC is supported only when all memory populated in system supports ECC Far memory slot to be populated, in case, single DIMM is placed on 2DPC channel. Maximum 2DPC frequency supported when same DIMM part number populated Within channel. Frequency is not guaranteed when mix DIMM's populated. DDR POR speed refers to Processor top SKU. Other SKUs may use lower memory speed, refer to ark.intel.com for top memory speed. DDR5 6400 requires to define a main clock out of 2 clock deferential pairs for each 32-bit channel.

DDR Technology Support Matrix

Technology	Form Factor	Ball Count	Processor
DDR5	SoDIMM/CSODIMM	262	S, HX
DDR5	UDIMM/CUDIMM	288	S

Supported Memory Modules and Devices

System Memory Interface Supported Memory Modules and Devices