Intel® Core™ Ultra 200S and 200HX Series Processors

Datasheet, Volume 1 of 2

ID Date Version Classification
832586 03/11/2025 Public

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Document Table of Contents
LAM

Fan Speed Control Scheme with DTS

With Digital Thermal Sensor (DTS) 1.1

To correctly use DTS 1.1, the designer must first select a worst case scenario TAMBIENT, and ensure that the Fan Speed Control (FSC) can provide a Ψ CA that is equivalent or greater than the Ψ CA specification.

The DTS 1.1 implementation consists of two points:

  • a Ψ CA at T CONTROL
  • a Ψ CA at DTS = -1

  • The Ψ CA point at DTS = -1 defines the minimum Ψ CA required at Processor Base Power considering the worst case system design T AMBIENT design point:

    Ψ CA = (T CASE-MAX - T AMBIENT-TARGET - 1 ) / Processor Base Power

    For example, for a 125 W Processor Base Power part, the T CASE maximum is 62.0 °C and at a worst case design point of 40 °C local ambient this will result in:

    Ψ CA = (62.0 - 40 - 1) / 125 = 0.168 °C/W

    Similarly for a system with a design target of 45 °C ambient, the Ψ CA at DTS = -1 needed will be 0.128 °C/W.

  • The second point defines the thermal solution performance (Ψ CA ) at T CONTROL . The following table lists the required Ψ CA for the various Processor Base Power processors.

These two points define the operational limits for the processor for DTS 1.1 implementation. At T CONTROL the fan speed must be programmed such that the resulting Ψ CA is better than or equivalent to the required Ψ CA listed in the following table. Similarly, the fan speed should be set at DTS = -1 such that the thermal solution performance is better than or equivalent to the ΨCA requirements at T AMBIENT-MAX .

The fan speed controller must linearly ramp the fan speed from processor DTS = T CONTROL to processor DTS = -1.

Digital Thermal Sensor (DTS) 1.1 Definition Points

Digital Thermal Sensor (DTS) 1.1 Thermal Solution Performance Above TCONTROL

PCG Die Configuration (Cores/GT) Processor Base Power [W] ΨCA at DTS = TCONTROL 1, 2 At System TAMBIENT_​MAX = 30 °C ΨCA at DTS = -1 At System TAMBIENT_​MAX = 40 °C ΨCA at DTS = -1 At System TAMBIENT_​MAX = 45 °C ΨCA at DTS = -1 At System TAMBIENT_​MAX = 50 °C
2020A 8P+16E 125 0.26 0.17 0.13 0.09
2022C 8P+16E 65 0.63 0.46 0.39 0.31
2022C 6P+8E 65 0.65 0.47 0.39 0.31
2022D 8P+16E 35 1.01 0.70 0.55 0.41
2022D 6P+8E 35 1.02 0.70 0.56 0.42
Notes:
  1. ΨCA at “DTS = TCONTROL” is applicable to systems that have an internal TRISE (TROOM temperature to Processor cooling fan inlet) of less than 10 °C. In case the expected TRISE is greater than 10 °C, a correction factor should be used as explained below. For each 1 °C TRISE above 10 °C, the correction factor (CF) is defined as CF = 1.7 / (Processor Base Power).
  2. The table data match for GT0.

With Digital Thermal Sensor (DTS) 2.0

To simplify processor thermal specification compliance, the processor calculates the DTS Thermal Profile from TCONTROL Offset, TCC Activation Temperature, Processor Base Power, and the Thermal Margin Slope provided in the following table.

Note:TCC Activation Offset is 0 for the processors.

Using the DTS Thermal Profile, the processor can calculate and report the Thermal Margin, where a value less than 0 indicates that the processor needs additional cooling, and a value greater than 0 indicates that the processor is sufficiently cooled.

Digital Thermal Sensor (DTS) 2.0 Definition Points

Thermal Margin Slope

PCG Die Configuration (Cores/GT) Processor Base Power [W] TCC Activation [°C] Temperature Control Offset Thermal Margin Slope [°C/W]
2020A 8P+16E 125 105 20 0.39
2022C 8P+16E 65 105 25 0.59
2022C 6P+8E 65 105 20 0.69
2022D 8P+16E 35 105 37 0.65
2022D 6P+8E 35 105 31 0.78
Notes:
  1. The default BIOS settings for this SKU is 10C TCC offset.