| Vcc GT | Active Voltage Range for Vcc GT | All | 0 | - | 1.52 | V | 2, 3, 5, 7 |
| Icc MAX_GT (S Processor) | Max. Current for Processor Graphics Rail | S-Processor Line 8P+16E Core 125W | - | - | 40 | A | 5 |
| Icc MAX_GT (S Processor) | Max. Current for Processor Graphics Rail | S-Processor Line 8P+12E Core 125W | - | - | 40 | A | 5 |
| Icc MAX_GT (S Processor) | Max. Current for Processor Graphics Rail | S-Processor Line 6P+8E Core 125W | - | - | 40 | A | 5 |
| Icc MAX_GT (S Processor) | Max. Current for Processor Graphics Rail | S-Processor Line 8P+16E Core 65W | - | - | 40 | A | 5 |
| Icc MAX_GT (S Processor) | Max. Current for Processor Graphics Rail | S-Processor Line 8P+12E Core 65W | - | - | 40 | A | 5 |
| Icc MAX_GT (S Processor) | Max. Current for Processor Graphics Rail | S-Processor Line 6P+8E Core 65W | - | - | 40 | A | 5 |
| Icc MAX_GT (S Processor) | Max. Current for Processor Graphics Rail | S-Processor Line 6P+4E Core 65W | - | - | 30 | A | 5 |
| Icc MAX_GT (S Processor) | Max. Current for Processor Graphics Rail | S-Processor Line 8P+16E Core 35W | - | - | 40 | A | 5 |
| Icc MAX_GT (S Processor) | Max. Current for Processor Graphics Rail | S-Processor Line 8P+12E Core 35W | - | - | 40 | A | 5 |
| Icc MAX_GT (S Processor) | Max. Current for Processor Graphics Rail | S-Processor Line 6P+8E Core 35W | - | - | 30 | A | 5 |
| Icc MAX_GT (S Processor) | Max. Current for Processor Graphics Rail | S-Processor Line 6P+4E Core 35W | - | - | 30 | A | 5 |
| TOB VCC GT | DC Voltage Tolerance | S -Processor Line: PS0, PS1 ,PS2, PS3 | - | - | ±20 | mV | 3,4 |
| TOBVCC GT+Ripple | DC + Ripple Voltage Tolerance | S Processor Lines: PS0, PS1, PS2, PS3 | - | - | -35 /+50 | mV | 3, 4 |
| DC_LL (S Processor) | DC Loadline | S -Processor Lines | - | - | 4.3 | mΩ | 6,8 |
| AC_LL (S Processor) | AC Loadline | S -Processor Lines | - | - | | mΩ | 6,8,9 |
| V_OVS_MAX | Max Overshoot Allowance from IccMAX | All | - | - | 70 | mV | |
| T_OVS_MAX | Max Overshoot Time from IccMAX | All | - | - | 10 | µs | |
- All specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date.
- Maximum operating voltage given for motherboard design purposes. Each processor is programmed with a maximum valid voltage identification value (VID) that is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Adaptive Thermal Monitor, Enhanced Intel Speed-step Technology, or low-power states). Failure of product operation, including potential irreversible damage to the part, can occur from operating the part at voltages above the individual VID that is programmed.
- The voltage specification requirements are measured across VccGT_SENSE and VssGT_SENSE as near as possible to the processor. The measurement needs to be performed with a 20MHz bandwidth limit on the oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.
- PSx refers to the voltage regulator power state as set by the SVID protocol. Refer to the IMVP9.2 Specification for more information.
- Operating voltage range in steady state.
- LL spec values should not be exceeded. If exceeded, power, performance and a reliability penalty are expected.
- Load Line measured at the sense point.
- Ripple can be higher if DC TOB is below 20mV, as long as Total TOB is within TOBVCCGT+Ripple spec.
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