Processor Clocking Signals

Intel® Core™ Ultra 200S and 200HX Series Processors

Datasheet, Volume 1 of 2

ID	Date	Version	Classification
832586	03/11/2025		Public

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Signal Description

Signal Name	Type	Description
CLKOUT_I_GEN4_N1	O	PCI Express* Clock Output: Serial Reference 100 MHz PCIe* specification compliant differential output clocks to PCIe* devices interfacing IOE. CLKOUT_I_GEN5_P/N [1] can be used for IOE PCIe* Gen4 support.
CLKOUT_I_GEN4_P1
CLKOUT_I_GEN5_N0
CLKOUT_I_GEN5_P0
CLKOUT_S_GEN5_N1	O	PCI Express* Clock Output: Serial Reference 100 MHz PCIe* specification compliant differential output clocks to PCIe* devices interfacing SOC-S. CLKOUT_S_GEN5_P/N [3:0] can be used for SOC-S PCIe* Gen5 support
CLKOUT_S_GEN5_P1
CLKOUT_S_GEN5_N2
CLKOUT_S_GEN5_P2
CLKOUT_S_GEN5_N3
CLKOUT_S_GEN5_P3
CLKOUT_S_GEN5_N0	O	DMI Clock Output: Serial Reference differential output clocks to PCH DMI interfacing SOC-S. CLKOUT_S_GEN5_P/N [0] is dedicated to be used as Intel^® 800 Series Chipset DMI REFCLK only
CLKOUT_S_GEN5_P0	O
GPP_SB08/I_SRCCLKREQ0#	IOD	Clock Request: Serial Reference Clock request signals for PCIe* 100 MHz differential clocks. The I_SRCCLKREQ # signals can be configured to map to any of the IOE PCI Express* Root Ports while using any of the IOE CLKOUT differential pairs
GPP_SB09/I_SRCCLKREQ1#	IOD
GPP_SD06/SRCCLKREQ2#	IOD	Clock Request: Serial Reference Clock request signals for PCIe* 100 MHz differential clocks. The SRCCLKREQ # signals can be configured to map to any of the SOC-S PCI Express* Root Ports while using any of the SOC-S CLKOUT differential pairs. SRCCLKREQ2# pins (muxed on GPP_SD06 and GPP_SB00) and SRCCLKREQ3# pins (muxed on GPP_SD07 and GPP_SB01) are alternate signals; only one pin can be used at a time.
GPP_SB14/SRCCLKREQ1#
GPP_SB00/SRCCLKREQ2#
GPP_SD07/SRCCLKREQ3#
GPP_SB01/SRCCLKREQ3#
GPP_SB07/SRCCLKREQ0#	IOD	DMI Clock Request : Serial Reference Clock request signals for PCH DMI interfacing SOC-S. The SRCCLKREQ0# signals is dedicated to be used as Intel^® 800 Series Chipset DMI CLKREQ only
EXT_INJ_BCLK_N	I	100 MHz Differential bus clock input to the processor
EXT_INJ_BCLK_P	I	100 MHz Differential bus clock input to the processor
EXT_INJ_PHYREF_N	I	100 MHz Differential bus clock input for PCIe and DMI OC
EXT_INJ_PHYREF_P	I	100 MHz Differential bus clock input for PCIe and DMI OC
XTAL_INJ_N	I	38.4 MHz crystal input
XTAL_INJ_P	I	38.4 MHz crystal input
RTC_CLK_IN	I	32.768Khz RTC CLK from PCH to CPU
CLK_I_RCOMP CLK_S_RCOMP	Analog	(HX only) Differential Clock Bias Reference: Used to set BIAS reference for differential clocks.