Intel® Core™ Ultra 200S and 200HX Series Processors

Datasheet, Volume 1 of 2

ID Date Version Classification
832586 03/11/2025 Public

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Document Table of Contents
Document Table of Contents
Legal Disclaimer Revision History Introduction Processor and Device IDs Package Mechanical Specifications Memory Mapping Security Technologies Intel® Virtualization Technology (Intel® VT) Instructions Set Enhancements Platform Environmental Control Interface (PECI) Intel GMM and Neural Network Accelerator (Intel GNA 3.5) Intel® Neural Processing Unit (Intel® NPU) Power Management Power Delivery Electrical Specifications Thermal Management Clock Topology Memory USB Type-C* Sub System Intel® Volume Management Device (Intel® VMD) Technology PCI Express* (PCIe*) Graphics Display General Purpose Input and Output Interrupt Timer Subsystem (ITSS) Direct Media Interface (DMI) Direct Enhanced Serial Peripheral Interface (Direct eSPI) Testability and Monitoring Miscellaneous Signals
Legal Disclaimer
Revision History
Introduction
Introduction Processor Volatility Statement Package Support Supported Technologies Power Management Support Thermal Management Support Ballout Information Processor Testability Operating Systems Support Terminology and Special Marks Related Documents
Processor Volatility Statement
Package Support
S Processor Package Support HX Processor Package Support
S Processor Package Support
HX Processor Package Support
Supported Technologies
Supported Technologies API Support (Windows*) Firmware Resiliency
API Support (Windows*)
Firmware Resiliency
Power Management Support
Power Management Support Processor Core Power Management System Power Management Memory Controller Power Management Processor Graphics Power Management
Processor Core Power Management
System Power Management
Memory Controller Power Management
Processor Graphics Power Management
Thermal Management Support
Ballout Information
Processor Testability
Operating Systems Support
Terminology and Special Marks
Related Documents
Processor and Device IDs
Processor and Device IDs CPUID PCI Configuration Header Device IDs Revision IDs
CPUID
PCI Configuration Header
Device IDs
Revision IDs
Package Mechanical Specifications
Package Mechanical Specifications Package Mechanical Attributes Package Storage Specifications
Package Mechanical Attributes
Package Storage Specifications
Memory Mapping
Memory Mapping Functional Description Memory Map
Functional Description
PCI Devices and Functions Fixed I/O Address Ranges Variable I/O Decode Ranges
PCI Devices and Functions
Fixed I/O Address Ranges
Variable I/O Decode Ranges
Memory Map
Memory Map Boot Block Update Scheme
Boot Block Update Scheme
Security Technologies
Security Technologies Intel® Converged Boot Guard and Intel® TXT Crypto Acceleration Instructions Intel® Secure Key Execute Disable Bit Intel® Supervisor Mode Execution Prevention (Intel® SMEP) Intel® Supervisor Mode Access Prevention (Intel® SMAP) User Mode Instruction Prevention (UMIP) Read Processor ID (RDPID) Intel® Total Memory Encryption - Multi-Key Control-flow Enforcement Technology (Intel® CET) KeyLocker Technology Intel® System Resources Defense and Intel® System Security Report BIOS Guard Intel® Platform Trust Technology Linear Address Space Separation (LASS) Security Firmware Engines
Intel® Converged Boot Guard and Intel® TXT
Crypto Acceleration Instructions
Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) Perform Carry-Less Multiplication Quad Word Instruction (PCLMULQDQ) Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions) New Cryptographic Acceleration Instructions
Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)
Perform Carry-Less Multiplication Quad Word Instruction (PCLMULQDQ)
Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions)
New Cryptographic Acceleration Instructions
Intel® Secure Key
Execute Disable Bit
Intel® Supervisor Mode Execution Prevention (Intel® SMEP)
Intel® Supervisor Mode Access Prevention (Intel® SMAP)
User Mode Instruction Prevention (UMIP)
Read Processor ID (RDPID)
Intel® Total Memory Encryption - Multi-Key
Control-flow Enforcement Technology (Intel® CET)
Control-flow Enforcement Technology (Intel® CET) Shadow Stack Indirect Branch Tracking
Shadow Stack
Indirect Branch Tracking
KeyLocker Technology
Intel® System Resources Defense and Intel® System Security Report
BIOS Guard
Intel® Platform Trust Technology
Linear Address Space Separation (LASS)
Security Firmware Engines
Intel® Converged Security and Management Engine (Intel® CSME) Intel® Silicon Security Engine Intel® Graphics System Controller (Intel® GSC)
Intel® Converged Security and Management Engine (Intel® CSME)
Intel® Silicon Security Engine
Intel® Graphics System Controller (Intel® GSC)
Intel® Virtualization Technology (Intel® VT)
Intel® Virtualization Technology (Intel® VT) Intel® Virtualization Technology (Intel® VT) for Intel® 64 and Intel® Architecture (Intel® VT-x) Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Intel® APIC Virtualization Technology (Intel® APICv)
Intel® Virtualization Technology (Intel® VT) for Intel® 64 and Intel® Architecture (Intel® VT-x)
Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d)
Intel® APIC Virtualization Technology (Intel® APICv)
Instructions Set Enhancements
CMPccXADD LAM
CMPccXADD
LAM
Platform Environmental Control Interface (PECI)
Platform Environmental Control Interface (PECI) PECI Bus Architecture
PECI Bus Architecture
Intel GMM and Neural Network Accelerator (Intel GNA 3.5)
Intel® Neural Processing Unit (Intel® NPU)
Intel® Neural Processing Unit (Intel® NPU) Functional Description
Functional Description
Functional Description Processor Subsystem NCE Subsystem
Processor Subsystem
NCE Subsystem
NCE Subsystem Some NCE Subsystem Features NCE Tile ACT-SHAVE
Some NCE Subsystem Features
NCE Tile
ACT-SHAVE
Power Management
Power Management System Power States, Advanced Configuration and Power Interface (ACPI) Processor IA Core Power Management Processor Graphics Power Management TCSS Power State Power and Performance Technologies Deprecated Technology Power and Internal Signals
System Power States, Advanced Configuration and Power Interface (ACPI)
Processor IA Core Power Management
Processor IA Core Power Management OS/HW Controlled P-states Low-Power Idle States Requesting the Low-Power Idle States Processor IA Core C-State Rules Package C-States Package C-States and Display Resolutions
OS/HW Controlled P-states
Enhanced Intel SpeedStep® Technology Intel® Speed Shift Technology
Enhanced Intel SpeedStep® Technology
Intel® Speed Shift Technology
Low-Power Idle States
Requesting the Low-Power Idle States
Processor IA Core C-State Rules
Package C-States
Package C-States and Display Resolutions
Processor Graphics Power Management
Processor Graphics Power Management Memory Power Savings Technologies Display Power Savings Technologies Processor Graphics Core Power Savings Technologies
Memory Power Savings Technologies
Display Power Savings Technologies
Processor Graphics Core Power Savings Technologies
TCSS Power State
Power and Performance Technologies
Power and Performance Technologies Intel® Thread Director Intel® Smart Cache Technology P-core and E-core Level 0, Level 1 and Level 2 Caches Ring Interconnect Intel® Hybrid Technology Intel® Turbo Boost Technology 2.0 Intel® Turbo Boost Max Technology 3.0 Intel® Adaptive Boost Technology Intel® System Agent Enhanced SpeedStep ® Technology Enhanced Intel SpeedStep® Technology Intel® Thermal Velocity Boost (Intel® TVB) Intel® Speed Shift Technology Intel® Advanced Vector Extensions 2 (Intel® AVX2) Intel® 64 Architecture x2APIC Intel® Dynamic Tuning Technology (Intel® DTT) Cache Line Write Back (CLWB) User Mode Wait Instructions
Intel® Thread Director
Intel® Smart Cache Technology
P-core and E-core Level 0, Level 1 and Level 2 Caches
Ring Interconnect
Intel® Hybrid Technology
Intel® Turbo Boost Technology 2.0
Intel® Turbo Boost Technology 2.0 Intel® Turbo Boost Technology 2.0 Power Monitoring Intel® Turbo Boost Technology 2.0 Power Control Intel® Turbo Boost Technology 2.0 Frequency
Intel® Turbo Boost Technology 2.0 Power Monitoring
Intel® Turbo Boost Technology 2.0 Power Control
Intel® Turbo Boost Technology 2.0 Frequency
Intel® Turbo Boost Max Technology 3.0
Intel® Adaptive Boost Technology
Intel® System Agent Enhanced SpeedStep ® Technology
Enhanced Intel SpeedStep® Technology
Intel® Thermal Velocity Boost (Intel® TVB)
Intel® Speed Shift Technology
Intel® Advanced Vector Extensions 2 (Intel® AVX2)
Intel® Advanced Vector Extensions 2 (Intel® AVX2) Intel® AVX2 Vector Neural Network Instructions (AVX2 VNNI)
Intel® AVX2 Vector Neural Network Instructions (AVX2 VNNI)
Intel® 64 Architecture x2APIC
Intel® Dynamic Tuning Technology (Intel® DTT)
Cache Line Write Back (CLWB)
User Mode Wait Instructions
Deprecated Technology
Power and Internal Signals
Signal Description Power Sequencing Signals I/O Signal Planes and States
Signal Description
Power Sequencing Signals
I/O Signal Planes and States
Power Delivery
Power and Ground Signals Digital Linear Voltage Regulator (DLVR) Fast V-Mode (FVM) Current Excursion Protection (CEP)
Power and Ground Signals
Digital Linear Voltage Regulator (DLVR)
Fast V-Mode (FVM)
Current Excursion Protection (CEP)
Electrical Specifications
Electrical Specifications Processor Power Rails DC Specifications
Processor Power Rails
Processor Power Rails Power and Ground Pins VCC Voltage Identification (VID)
Power and Ground Pins
VCC Voltage Identification (VID)
DC Specifications
DC Specifications Processor Power Rails DC Specifications Processor Interfaces DC Specifications
Processor Power Rails DC Specifications
Processor Power Rails DC Specifications VCCCORE DC Specifications VccGT DC Specifications VccSA DC Specification VDD2 DC Specifications VCCPRIM_VNNAON DC Specifications VCCPRIM_IO DC Specifications VCCPRIM_1P8 DC Specifications
VCCCORE DC Specifications
VccGT DC Specifications
VccSA DC Specification
VDD2 DC Specifications
VCCPRIM_VNNAON DC Specifications
VCCPRIM_IO DC Specifications
VCCPRIM_1P8 DC Specifications
Processor Interfaces DC Specifications
Processor Interfaces DC Specifications DDR5 DC Specifications PCIe* DC and Timing Specifications Digital Display Interface (DDI) DC Specifications Single Ended DC Specification
DDR5 DC Specifications
PCIe* DC and Timing Specifications
Digital Display Interface (DDI) DC Specifications
Single Ended DC Specification
Single Ended DC Specification CMOS DC Specifications GTL and OD DC Specification SVID DC Specifications
CMOS DC Specifications
GTL and OD DC Specification
SVID DC Specifications
Thermal Management
Thermal Management Processor Thermal Management Processor Base Power Thermal and Power Specifications Processor Line Thermal and Power Specifications Error and Thermal Protection Signals Thermal Metrology Fan Speed Control Scheme with DTS Thermal Sensor
Processor Thermal Management
Processor Thermal Management Thermal Considerations Assured Power (cTDP) Thermal Management Features Intel® Memory Thermal Management
Thermal Considerations
Thermal Considerations Package Power Control Platform Power Control Turbo Time Parameter (Tau)
Package Power Control
Platform Power Control
Turbo Time Parameter (Tau)
Assured Power (cTDP)
Assured Power (cTDP) Assured Power (cTDP) Modes
Assured Power (cTDP) Modes
Thermal Management Features
Thermal Management Features Adaptive Thermal Monitor Digital Thermal Sensor PROCHOT# Signal PROCHOT Output Only Bi-Directional PROCHOT# PROCHOT Demotion Algorithm Voltage Regulator Protection using PROCHOT# Thermal Solution Design and PROCHOT# Behavior Low-Power States and PROCHOT# Behavior THERMTRIP# Signal Critical Temperature Detection Software Controlled Clock Modulation (On-Demand Mode)
Adaptive Thermal Monitor
Digital Thermal Sensor
PROCHOT# Signal
PROCHOT Output Only
Bi-Directional PROCHOT#
PROCHOT Demotion Algorithm
Voltage Regulator Protection using PROCHOT#
Thermal Solution Design and PROCHOT# Behavior
Low-Power States and PROCHOT# Behavior
THERMTRIP# Signal
Critical Temperature Detection
Software Controlled Clock Modulation (On-Demand Mode)
Intel® Memory Thermal Management
Processor Base Power Thermal and Power Specifications
Processor Line Thermal and Power Specifications
Error and Thermal Protection Signals
Thermal Metrology
Fan Speed Control Scheme with DTS
Thermal Sensor
Thermal Sensor Modes of Operation Temperature Trip Point Thermal Sensor Accuracy (Taccuracy) Thermal Reporting to EC
Modes of Operation
Temperature Trip Point
Thermal Sensor Accuracy (Taccuracy)
Thermal Reporting to EC
Clock Topology
Clock Topology Integrated Reference Clock PLL Processor Clocking Signals
Integrated Reference Clock PLL
Processor Clocking Signals
Memory
Memory System Memory Interface Integrated Memory Controller (IMC) Power Management Signal Description
System Memory Interface
System Memory Interface Processor SKU Support Matrix Supported Memory Modules and Devices System Memory Timing Support Memory Controller (MC) System Memory Controller Organization Mode System Memory Frequency Technology Enhancements of Intel® Fast Memory Access (Intel® FMA) Data Scrambling ECC H-Matrix Syndrome Codes Data Swapping DDR I/O Interleaving DRAM Clock Generation DRAM Reference Voltage Generation Data Swizzling Post Package Repair (PPR)
Processor SKU Support Matrix
Supported Memory Modules and Devices
System Memory Timing Support
System Memory Timing Support SAGV Points
SAGV Points
Memory Controller (MC)
System Memory Controller Organization Mode
System Memory Frequency
Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)
Data Scrambling
ECC H-Matrix Syndrome Codes
Data Swapping
DDR I/O Interleaving
DRAM Clock Generation
DRAM Reference Voltage Generation
Data Swizzling
Post Package Repair (PPR)
Integrated Memory Controller (IMC) Power Management
Integrated Memory Controller (IMC) Power Management Disabling Unused System Memory Outputs DRAM Power Management and Initialization DDR Electrical Power Gating Power Training
Disabling Unused System Memory Outputs
DRAM Power Management and Initialization
DRAM Power Management and Initialization Conditional Self-Refresh Dynamic Power-Down DRAM I/O Power Management
Conditional Self-Refresh
Dynamic Power-Down
DRAM I/O Power Management
DDR Electrical Power Gating
Power Training
Signal Description
USB Type-C* Sub System
USB Type-C* Sub System General Capabilities USB4* Router xHCI/xDCI Controllers Display Interface USB Type-C Signals LSx AUX BIAS Control
General Capabilities
USB4* Router
USB4* Router USB4 Host Router Implementation Capabilities
USB4 Host Router Implementation Capabilities
xHCI/xDCI Controllers
xHCI/xDCI Controllers USB 3 Controllers
USB 3 Controllers
USB 3 Controllers Extensible Host Controller Interface (xHCI) Extensible Device Controller Interface (xDCI)
Extensible Host Controller Interface (xHCI)
Extensible Device Controller Interface (xDCI)
Display Interface
USB Type-C Signals
LSx
LSx LSx Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
LSx Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
AUX BIAS Control
Intel® Volume Management Device (Intel® VMD) Technology
PCI Express* (PCIe*)
PCI Express* (PCIe*) Functional Description Signal Description I/O Signal Planes and States PCI Express* Root Port Support Feature Details
Functional Description
Functional Description PCI Express* Power Management Port 80h Decode Separate Reference Clock with Independent SSC (SRIS) Advanced Error Reporting Single - Root I/O Virtualization (SR - IOV) PCI Express* Receiver Lane Polarity Inversion Precision Time Measurement (PTM)
PCI Express* Power Management
Port 80h Decode
Separate Reference Clock with Independent SSC (SRIS)
Advanced Error Reporting
Single - Root I/O Virtualization (SR - IOV)
PCI Express* Receiver Lane Polarity Inversion
Precision Time Measurement (PTM)
Signal Description
I/O Signal Planes and States
PCI Express* Root Port Support Feature Details
Graphics
Graphics Processor Graphics Platform Graphics Hardware Feature
Processor Graphics
Processor Graphics Media Support (Intel® QuickSync and Clear Video Technology HD) Graphics Core Cache
Media Support (Intel® QuickSync and Clear Video Technology HD)
Media Support (Intel® QuickSync and Clear Video Technology HD) Hardware Accelerated Video Decode Hardware Accelerated Video Encode Hardware Accelerated Video Processing Hardware Accelerated Transcoding
Hardware Accelerated Video Decode
Hardware Accelerated Video Encode
Hardware Accelerated Video Processing
Hardware Accelerated Transcoding
Graphics Core Cache
Platform Graphics Hardware Feature
Platform Graphics Hardware Feature Hybrid Graphics
Hybrid Graphics
Display
Display Display Technologies Support Display Interfaces Display Features
Display Technologies Support
Display Interfaces
Display Interfaces Digital Display Interface DDI Signals Digital Display Interface TCP Signals
Digital Display Interface DDI Signals
Digital Display Interface TCP Signals
Display Features
Display Features General Capabilities Multiple Display Configurations High-bandwidth Digital Content Protection (HDCP) DisplayPort* High-Definition Multimedia Interface (HDMI*) embedded DisplayPort* (eDP*) Integrated Audio
General Capabilities
Multiple Display Configurations
High-bandwidth Digital Content Protection (HDCP)
DisplayPort*
DisplayPort* Multi-Stream Transport (MST)
Multi-Stream Transport (MST)
High-Definition Multimedia Interface (HDMI*)
embedded DisplayPort* (eDP*)
Integrated Audio
General Purpose Input and Output
General Purpose Input and Output Functional Description Signal Description
Functional Description
Interrupt / IRQ via GPIO Requirement Integrated Pull-ups and Pull-downs SCI / SMI and NMI Timed GPIO
Interrupt / IRQ via GPIO Requirement
Integrated Pull-ups and Pull-downs
SCI / SMI and NMI
Timed GPIO
Signal Description
Interrupt Timer Subsystem (ITSS)
Interrupt Timer Subsystem (ITSS) Feature Overview Functional Description
Feature Overview
Functional Description
Functional Description 8254 Timers APIC Advanced Programmable Interrupt Controller High Precision Event Timer (HPET)
8254 Timers
8254 Timers Timer Programming Reading from Interval Timer
Timer Programming
Reading from Interval Timer
APIC Advanced Programmable Interrupt Controller
High Precision Event Timer (HPET)
High Precision Event Timer (HPET) Timer Accuracy Timer Off-load Periodic Versus Non-Periodic Modes Enabling the Timers Interrupt Levels
Timer Accuracy
Timer Off-load
Periodic Versus Non-Periodic Modes
Enabling the Timers
Interrupt Levels
Direct Media Interface (DMI)
Direct Media Interface (DMI) DMI Lane Reversal and Polarity Inversion DMI Error Flow DMI Link Down Signal Description
DMI Lane Reversal and Polarity Inversion
DMI Error Flow
DMI Link Down
Signal Description
Direct Enhanced Serial Peripheral Interface (Direct eSPI)
Functional Description Signal Description
Functional Description
Functional Description Processor-PCH eSPI Return Clock Support PCH Multiple External eSPI Device Support Processor Direct eSPI Channel Support
Processor-PCH eSPI Return Clock Support
PCH Multiple External eSPI Device Support
Processor Direct eSPI Channel Support
Signal Description
Testability and Monitoring
Testability and Monitoring Signal Description I/O Signal Planes and States
Signal Description
I/O Signal Planes and States
Miscellaneous Signals
Signal Description Ground and Reserved Signals
Signal Description
Ground and Reserved Signals

P-core and E-core Level 0, Level 1 and Level 2 Caches

The 1st level cache is not shared between physical cores and each physical core has a separate set of caches.

The P-Core 1st level cache hierarchy is divided into:

  • A Data Cache (DL0, DL1)
  • An Instruction Cache (IL1)

On the data side, it is built as two-level cache, with L0 of 48KB and L1 of 192KB, both of which are 12-way set-associative.

On the instruction side, there is a single L1 cache of 64KB, which is 16-way set associative.

The E-Core 1st level cache hierarchy is divided into:

  • A Data Cache (DL1)
  • An Instruction Cache (IL1)

On the data side, it is built as one-level cache, with L1 of 32KB, 8-way set-associative.

On the instruction side, there is a single L1 cache of 64KB, which is 16-way set associative.

The 2nd level cache holds both data and instructions. It is also referred to as mid-level cache or MLC.

  • The P-core 2nd level caches are not shared between physical cores and each physical core has a separate set of caches. Its size is 3MB and it is a 12-way associative non-inclusive cache.
  • The E-core 2nd level cache is shared between E-Cores within a module of 4 E-Cores in the Compute tile. Its size is 4MB and it is a 16-way associative non-inclusive cache.

P-core and E-core Cache Hierarchy

Note: The above figure does not represent the exact number of cores.
Cache P-core E-core
L0 DL0 48KB 12-way set-associative per core None
L1 DL1 192KB 12-way set-associative per core 32KB 8-way set-associative per core
L1 IL1 64KB 16-way set-associative per core 64KB 16-way set-associative per core
L2 3MB 12-way set-associative per core 4MB 16-way set-associative within a module of 4 Compute tile E-cores
L3 Maximum of 3 MB per P-core / module of 4 E-cores shared across Compute tile

Ring Interconnect