System Power States, Advanced Configuration and Power Interface (ACPI)

Intel® Core™ Ultra 200S and 200HX Series Processors

Datasheet, Volume 1 of 2

ID	Date	Version	Classification
832586	03/11/2025		Public

A newer version of this document is available. Customers should click here to go to the newest version.

This section describes System Power States and ACPI states supported by the processor.

For more information, refer to Intel® 800 Series Chipset Family Platform Controller Hub (PCH) Datasheet, Volume 1 of 2 (#833778 ).

General System Power States

State		Description
G0/S0/C0		Full On: CPU operating. Individual devices may be shut to save power. The different CPU operating levels are defined by Cx states.
GO/S0/Cx		Cx state: CPU manages C-states by itself and can be in low power state
G0/S0ix/Cx		S0ix:The south supports an S0ix state which also requires the CPU be in a Cx state. Additional south power actions such as voltage reduction, chip-wide voltage rail removal may occur in this state.
G1/S4		Suspend-To-Disk (STD): The context of the system is maintained on the disk. All power is then shut to the system except to the logic required to resume. Externally appears same as S5 but may have different wake events.
G2/S5		Soft Off: System context not maintained. All power is shut except for the logic required to restart. A full boot is required when waking.
G3		Mechanical OFF: System context not maintained. All power shut except for the RTC. No “Wake” events are possible because the system does not have any power. This state occurs if the user removes the batteries, turns off a mechanical switch, or if the system power supply is at a level that is insufficient to power the “waking” logic. When system power returns the transition will depend on the state just prior to the entry to G3.

The table below shows the transitions rules among the various states.

Note:Transitions among the various states may appear to temporarily transition through intermediate states. For example, in going from S0 to S5, it may appear to pass through the G1/S4 state. These intermediate transitions and states are not listed in the table below.

State Transition Rules for the Processor

Present State	Transition Trigger	Next State
G0/S0/C0	SLP_EN bit set Power Button Override³ Mechanical Off/Power Failure	G0/S0/Cx G1/S4, or G2/S5 state G2/S5 G3
G0/S0/Cx	Power Button Override³ Mechanical Off/Power Failure	G0/S0/C0 S5 G3
G0/S0ix/Cx	Any south action which is blocked from occurring while in S0ix CPU or south IP request for CPU C-state exit	G0/S0ix/Cx G0/S0/Cx G0/S0/C2(or C0)
G1/S3, G1/S4	Any Enabled Wake Event Power Button Override³ Mechanical Off/Power Failure	G0/S0/C0² G2/S5 G3
G2/S5	Any Enabled Wake Event Mechanical Off/Power Failure	G0/S0/C0² G3
G3	Power Returns	S0/C0 (reboot) or G2/S5⁴ (stay off until power button pressed or other wake event)^1,2
Notes: Some wake events can be preserved through power failure. Transitions from the S4-S5 states to the S0 state are deferred until BATLOW# is inactive. Includes all other applicable types of events that force the host into and stay in G2/S5. If the system was in G1/S4 before G3 entry, then the system will go to S0/C0 or G1/S4. On G3 exit, prior to the first transition to S0, S5 power may be higher than S5 power after the first S0 to S5 transition. Some processor settings required to achieve minimum S5 power are loaded during first boot to S0 after a G3 exit. Consequently, entry into S5 from S0 will result in a more power-optimized S5 state than entry into S5 from G3 without an S5-S0-S5 transition. The difference is expected to be in the few mW range

Intel® Core™ Ultra 200S and 200HX Series Processors

Datasheet, Volume 1 of 2