Processor Line Thermal and Power Specifications

Intel® Core™ Ultra 200S and 200HX Series Processors

Datasheet, Volume 1 of 2

ID	Date	Version	Classification
832586	03/11/2025		Public

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Package Turbo Specifications (S Processor Lines)

No Specifications for Min/Max PL1/PL2 values.

Hardware default of PL1 Tau=1s, By including the benefits available from power and thermal management features the recommended is to use PL1 Tau=28s.

PL2- Processor opportunistic higher Average Power – Reactive, Limited Duration controlled by Tau_PL1 setting.

PL1 Tau - PL1 average power is controlled via PID algorithm with this Tau, The larger the Tau, the longer the PL2 duration.

System cooling solution and designs found to not being able to support the Performance TauPL1, adjust the TauPL1 to cooling capability.

Segment and Package	Processor IA Cores, Graphics, Configuration and Processor Base Power	Parameter	Minimum	Tau MSR Max Value	Recommended Value	Units	Table: General Notes
S-Processor Line LGA	8P+16E Core 125W⁶	Power Limit 1 Time (PL1 Tau)	0.1	448	56	S	3,4,5,6,7,8,14,16,17
		Power Limit 1 (PL1)	N/A	N/A	125	W
		Power Limit 2 (PL2)	N/A	N/A	250	W
S-Processor Line LGA	8P+12E Core 125W	Power Limit 1 Time (PL1 Tau)	0.1	448	56	S	3,4,5,6,7,8,14,16,17
		Power Limit 1 (PL1)	N/A	N/A	125	W
		Power Limit 2 (PL2)	N/A	N/A	250	W
S-Processor Line LGA	6P+8E Core 125W	Power Limit 1 Time (PL1 Tau)	0.1	448	56	S	3,4,5,6,7,8,14,16,17
		Power Limit 1 (PL1)	N/A	N/A	125	W
		Power Limit 2 (PL2)	N/A	N/A	159	W
S-Processor Line LGA	8P+16E Core 65W¹	Power Limit 1 Time (PL1 Tau)	0.1	448	28	S	3,4,5,6,7,8,14,16,17
		Power Limit 1 (PL1)	N/A	N/A	65	W
		Power Limit 2 (PL2)	N/A	N/A	182	W
S-Processor Line LGA	8P+12E Core 65W	Power Limit 1 Time (PL1 Tau)	0.1	448	28	S	3,4,5,6,7,8,14,16,17
		Power Limit 1 (PL1)	N/A	N/A	65	W
		Power Limit 2 (PL2)	N/A	N/A	182	W
S-Processor Line LGA	6P+8E Core 65W	Power Limit 1 Time (PL1 Tau)	0.1	448	28	S	3,4,5,6,7,8,14,16,17
		Power Limit 1 (PL1)	N/A	N/A	65	W
		Power Limit 2 (PL2)	N/A	N/A	121	W
S-Processor Line LGA	6P+4E Core 65W	Power Limit 1 Time (PL1 Tau)	0.1	448	28	S	3,4,5,6,7,8,14,16,17
		Power Limit 1 (PL1)	N/A	N/A	65	W
		Power Limit 2 (PL2)	N/A	N/A	121	W
S-Processor Line LGA	8P+16E Core 35W¹	Power Limit 1 Time (PL1 Tau)	0.1	448	28	S	3,4,5,6,7,8,14,16,17
		Power Limit 1 (PL1)	N/A	N/A	35	W
		Power Limit 2 (PL2)	N/A	N/A	112	W
S-Processor Line LGA	8P+12E Core 35W	Power Limit 1 Time (PL1 Tau)	0.1	448	28	S	3,4,5,6,7,8,14,16,17
		Power Limit 1 (PL1)	N/A	N/A	35	W
		Power Limit 2 (PL2)	N/A	N/A	112	W
S-Processor Line LGA	6P+8E Core 35W	Power Limit 1 Time (PL1 Tau)	0.1	448	28	S	3,4,5,6,7,8,14,16,17
		Power Limit 1 (PL1)	N/A	N/A	35	W
		Power Limit 2 (PL2)	N/A	N/A	114	W
S-Processor Line LGA	6P+4E Core 35W	Power Limit 1 Time (PL1 Tau)	0.1	448	28	S	3,4,5,6,7,8,14,16,17
		Power Limit 1 (PL1)	N/A	N/A	35	W
		Power Limit 2 (PL2)	N/A	N/A	114	W
Note:Refer to Table: General Notes

Package Turbo Specifications (HX Processor Lines)

No Specifications for Min/Max PL1/PL2 values.

Hardware default of PL1 Tau=1s, By including the benefits available from power and thermal management features the recommended is to use PL1 Tau=28s.

PL2- Processor opportunistic higher Average Power – Reactive, Limited Duration controlled by Tau_PL1 setting.

PL1 Tau - PL1 average power is controlled via PID algorithm with this Tau, The larger the Tau, the longer the PL2 duration.

System cooling solution and designs found to not being able to support the Performance TauPL1, adjust the TauPL1 to cooling capability.

The HX 8+16 55W is targeted for ES1/ES2 samples only.

Segment and Package	Processor IA Cores, Graphics, Configuration and Processor Base Power	Parameter	Minimum	Tau MSR Max Value	Recommended Value	Units	Table: General Notes
HX-Processor Line LGA	8P+16E Core 55W	Power Limit 1 Time (PL1 Tau)	0.1	448	56	S	3,4,5,6,7,8,14,16,17
		Power Limit 1 (PL1)	N/A	N/A	55	W
		Power Limit 2 (PL2)	N/A	N/A	160	W
	8P+12E Core 55W	Power Limit 1 Time (PL1 Tau)	0.1	448	56	S	3,4,5,6,7,8,14,16,17
		Power Limit 1 (PL1)	N/A	N/A	55	W
		Power Limit 2 (PL2)	N/A	N/A	144	W
	6P+8E Core 55W¹	Power Limit 1 Time (PL1 Tau)	0.1	448	56	S	3,4,5,6,7,8,14,16,17
		Power Limit 1 (PL1)	N/A	N/A	55	W
		Power Limit 2 (PL2)	N/A	N/A	108	W
Note:Refer to Table: General Notes

Operating Temperature Specifications (S/HX Processor Line )

Segment	Package Turbo Parameter	Temperature Range		Processor Base Power Specification Temperature Range		Units	Notes
Segment	Package Turbo Parameter	Minimum	Maximum	Minimum	Maximum
HX-Processor Line SBGA	Operating temperature	0	105	0	105	ºC	1, 2
S-Processor Line LGA	Operating temperature	0	105	0	105	ºC	1, 2
Notes: The thermal solution needs to ensure that the processor temperature does not exceed the Processor Base Power Specification Temperature. The processor operating temperature is monitored by Digital Temperature Sensors (DTS). For DTS accuracy, refer to Digital Thermal Sensor.

Low Power and TMTV Specifications (S Processor Line LGA)

Processor IA Cores, Graphics Configuration and Processor Base Power	PCG7	Maximum Power Package C8 (W)^1,4,5	TMTV Processor Base Power (W)^6,7	Min TCASE (°C)	Maximum TMTV TCASE (°C)
8P+16E Core 125W	2020A	N/A	125	0	61.8
8P+16E Core 65W	2022C	N/A	65	0	71.1
Notes: The package C-state power is the worst case power in the system configured as follows: DMI and PCIe links are at L1 Specification at DTS = 50 °C and minimum voltage loadline. Specification at DTS = 35 °C and minimum voltage loadline. These DTS values in Notes 2 - 3 are based on the TCC Activation MSR having a value of 100. These values are specified at VCC_MAX and VNOM for all other voltage rails for all processor frequencies. Systems should be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCCP exceeds VCCP_MAX at specified ICCP. Refer to the loadline specifications. Processor Base Power should be used for processor thermal solution design targets. Processor Base Power is not the maximum power that the processor can dissipate. Processor Base Power is measured at DTS = -1. Processor Base Power is achieved with the Memory configured for DDR. Platform Compatibility Guide (PCG) (previously known as FMB) provides a design target for meeting all planned processor frequency requirements.

Processor IA Cores, Graphics Configuration and Processor Base Power

PCG7

Maximum Power Package C8 (W)^1,4,5

TMTV Processor Base Power (W)^6,7

Min TCASE

(°C)

Maximum TMTV TCASE

(°C)

8P+16E Core 125W

2020A

N/A

125

61.8

8P+16E Core 65W

2022C

N/A

71.1

Notes:

The package C-state power is the worst case power in the system configured as follows:
1. DMI and PCIe links are at L1
Specification at DTS = 50 °C and minimum voltage loadline.
Specification at DTS = 35 °C and minimum voltage loadline.
These DTS values in Notes 2 - 3 are based on the TCC Activation MSR having a value of 100.
These values are specified at VCC_MAX and VNOM for all other voltage rails for all processor frequencies. Systems should be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCCP exceeds VCCP_MAX at specified ICCP. Refer to the loadline specifications.
Processor Base Power should be used for processor thermal solution design targets. Processor Base Power is not the maximum power that the processor can dissipate. Processor Base Power is measured at DTS = -1. Processor Base Power is achieved with the Memory configured for DDR.
Platform Compatibility Guide (PCG) (previously known as FMB) provides a design target for meeting all planned processor frequency requirements.

TCONTROL Offset Configuration (S Processor Line LGA - Client)

Segment	TEMP_TARGET (TCONTROL) [ºC]
8P+16E Core 125W	20
Notes: Digital Thermal Sensor (DTS) based fan speed control is recommended to achieve optimal thermal performance. Intel recommends full cooling capability at approximately the DTS value of -1, to minimize TCC activation risk. For example, if TCONTROL = 20 ºC, Fan acceleration operation will start at 80 ºC (100 ºC - 20 ºC).