| VCCPRIM_1P8_PROC_FLTRA | VCCPRIM_1P8_PROC_FLTRA Power Rail Voltage | All | - | 1.8 | - | V | 2,3,4 |
| TOBVCCPRIM_1P8_PROC_FLTRA | Voltage Tolerance | All | - | - | ±5 | % | 2,3 |
| IccMAX_VCCPRIM_1P8_PROC_FLTRA | Maximum Current | S-Processor Line | - | - | 168 | mA | 3 |
| IccMAX_VCCPRIM_1P8_PROC_FLTRA | Maximum Current | HX-Processor Line | - | - | 168 | mA | 3 |
- All specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date.
- Includes AC and DC error, where the AC noise is bandwidth limited to under 1 MHz, measured on package pins.
- No requirement on the breakdown of AC versus DC noise.
- The voltage specification requirements are measured on package pins as near as possible to the processor with an oscilloscope set to 100 MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe
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