DDR4 DC Specifications

12th Generation Intel® Core™ Processors Datasheet, Volume 1 of 2

Datasheet

ID	Date	Version	Classification
655258	28/10/2021 00:00:00		Public Content

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DDR4 Signal Group DC Specifications

Symbol	Parameter	S 8+8 Processor Line			Units	Notes¹
Symbol	Parameter	Minimum	Typical	Maximum	Units	Notes¹
V_IL	Input Low Voltage	—	0.75*Vdd2	0.68*Vdd2	V	2, 3, 4
V_IH	Input High Voltage	0.82*Vdd2	0.75*Vdd2	—	V	2, 3, 4
R_{ON_UP(DQ)}	Data Buffer pull-up Resistance	30	—	50	Ω	5,12
R_{ON_DN(DQ)}	Data Buffer pull-down Resistance	30	—	50
R_ODT(DQ)	On-die termination equivalent resistance for data signals	40	—	200	Ω	6, 12
V_ODT(DC)	On-die termination DC working point (driver set to receive mode)	0.45*Vdd2	—	0.85*Vdd2	V	12
R_{ON_UP(CK)}	Clock Buffer pull-up Resistance	25	—	45	Ω	5, 12
R_{ON_DN(CK)}	Clock Buffer pull-down Resistance	25	—	45	Ω	5, 12
R_{ON_UP(CMD)}	Command Buffer pull-up Resistance	25	—	45	Ω	5, 12
R_{ON_DN(CMD)}	Command Buffer pull-down Resistance	25	—	45	Ω	5, 12
R_{ON_UP(CTL)}	Control Buffer pull-up Resistance	25	—	45	Ω	5, 12
R_{ON_DN(CTL)}	Control Buffer pull-down Resistance	25	—	45	Ω	5, 12
R_{ON_UP} _{(SM_PG_CNTL1)}	System Memory Power Gate Control Buffer Pull-up Resistance	45	—	125	Ω	—
R_{ON_DN} _{(SM_PG_CNTL1)}	System Memory Power Gate Control Buffer Pull- down Resistance	40	—	130	Ω	—
I_LI	Input Leakage Current (DQ, CK) 0 V 0.2* V_DD2 0.8* V_DD2	—	—	1.1	mA	—
DDR0_VREF_DQ DDR1_VREF_DQ	VREF output voltage	Trainable	V_DD2/2	Trainable	V	—
SM_RCOMP[0]	Command COMP Resistance	99	100	101	Ω	8
SM_RCOMP[1]	Data COMP Resistance	99	100	101	Ω	8
SM_RCOMP[2]	ODT COMP Resistance	99	100	101	Ω	8
Notes: All specifications in this table apply to all processor frequencies. Timing specifications only depend on the operating frequency of the memory channel and not the maximum rated frequency V_IL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value. V_IH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value. V_IH and V_OH may experience excursions above V_DD2. However, input signal drivers should comply with the signal quality specifications. Pull up/down resistance after compensation (assuming ±5% COMP inaccuracy). Note that BIOS power training may change these values significantly based on margin/power trade-off. Refer to processor I/O Buffer Models for I/V characteristics. ODT values after COMP (assuming ±5% inaccuracy). BIOS MRC can reduce ODT strength towards The minimum and maximum values for these signals are programmable by BIOS to one of the two sets. SM_RCOMP[x] resistance should be provided on the system board with 1% resistors. SM_RCOMP[x] resistors are to VSS. Values are pre-silicon estimations and are subject to change. SM_DRAMPWROK must have a maximum of 15 ns rise or fall time over VDD2 * 0.30 ±100 mV and the edge must be monotonic. SM_VREF is defined as V_DD2/2 for DDR4 R_ON tolerance is preliminary and might be subject to change. Maximum-minimum range is correct but center point is subject to change during MRC boot training. Processor may be damaged if V_IH exceeds the maximum voltage for extended periods.