Processor Line Thermal and Power - 001 - ID:655258 | 12th Generation Intel® Core™ Processors Datasheet, Volume 1 of 2

12th Generation Intel® Core™ Processors Datasheet, Volume 1 of 2

Datasheet

ID	Date	Version	Classification
655258	28/10/2021 00:00:00		Public Content

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Processor Line Thermal and Power

Package Turbo Specifications (S - Processor Lines)

Segment and Package	Processor IA Cores, Graphics, Configuration and Processor Base Power (a.k.a TDP)	Parameter	Minimum	Recommended Value	Tau MSR Max Value	Units	Notes
S-Processor Line LGA	8+8 Core 125W	Power Limit 1 Time (PL1 Tau)	0.1	56	448	S	3,4,5,6,7,8,14,16,17
		Power Limit 1 (PL1)	N/A	125	N/A	W
		Power Limit 2 (PL2)	N/A	241	N/A	W
	8+4 Core 125W	Power Limit 1 Time (PL1 Tau)	0.1	56	448	S	3,4,5,6,7,8,14,16,17
		Power Limit 1 (PL1)	N/A	125	N/A	W
		Power Limit 2 (PL2)	N/A	190	N/A	W
	6+4 Core 125W	Power Limit 1 Time (PL1 Tau)	0.1	56	448	S	3,4,5,6,7,8,14,16,17
		Power Limit 1 (PL1)	N/A	125	N/A	W
		Power Limit 2 (PL2)	N/A	150	N/A	W
Notes: No Specifications for Min/Max PL1/PL2 values. Hardware default of PL1 Tau=1s, By including the benefits available from power and thermal management features the recommended is to use PL1 Tau=28s. PL2- SoC opportunistic higher Average Power – Reactive, Limited Duration controlled by Tau_PL1 setting. PL1 Tau - PL1 average power is controlled via PID algorithm with this Tau. The larger the Tau, the longer the PL2 duration. System cooling solution and designs found to not being able to support the Performance TauPL1, adjust the TauPL1 to cooling capability.

Low Power and TTV

Low Power and TTV Specifications (S-Processor Line LGA )

Processor IA Cores, Graphics Configuration and Processor Base Power (a.k.a TDP)	PCG7	Maximum Power Package C7 (W)^1,4,5	Maximum Power Package C8 (W)^1,4,5	TTV Processor Base Power (a.k.a TDP) (W)^6,7	Min TCASE (°C)	Maximum TTV TCASE (°C)
8+8 Core 125W	2020A	N/A	N/A	125	0	61.9
8+4 Core 125W		N/A	N/A	125	0	61.9
6+4 Core 125W		N/A	N/A	125	0	61.9
Notes: The package C-state power is the worst case power in the system configured as follows: Memory configured for DDR4 and populated with two DIMMs per channel. DMI and PCIe links are at L1 Specification at DTS = 50 °C and minimum voltage loadline. Specification at DTS = 35 °C and minimum voltage loadline. These DTS values in Notes 2 - 3 are based on the TCC Activation MSR having a value of 100, Refer Thermal Management Features. These values are specified at VCC_MAX and VNOM for all other voltage rails for all processor frequencies. Systems should be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCCP exceeds VCCP_MAX at specified ICCP. Refer the loadline specifications. Thermal Processor Base Power (a.k.a TDP) should be used for processor thermal solution design targets. Processor Base Power is not the maximum power that the processor can dissipate. Processor Base Power (a.k.a TDP) is measured at DTS = -1. Processor Base Power(a.k.a TDP) is achieved with the Memory configured for DDR Platform Compatibility Guide (PCG) (previously known as FMB) provides a design target for meeting all planned processor frequency requirements. Not 100% tested. Specified by design characterization.

TCONTROL Offset Configuration (S-Processor Line - Client)

Segment	8+8 Core	8+4 Core	6+4 Core
Processor Base Power (a.k.a TDP) [W]	125	125	125
TEMP_TARGET (TCONTROL) [ºC]	20	20	20
Notes: Digital Thermal Sensor (DTS) based fan speed control is recommended to achieve optimal thermal performance. Intel recommends full cooling capability at approximately the DTS value of -1, to minimize TCC activation risk. For example, if TCONTROL = 20 ºC, Fan acceleration operation will start at 80 ºC (100 ºC - 20 ºC).