12th Generation Intel® Core™ Processors Datasheet, Volume 1 of 2
PCI Express* Architecture
Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers operate unchanged.
The PCI Express* configuration uses standard mechanisms as defined in the PCI Plug-and-Play specification.
The processor PCI Express* port supports Gen 4 at 16GT/s uses a 128b/130b encoding and Gen 5 at 32 GT/s uses a 128b/130b encoding
S-Processor Line: The 4 lanes port can operate at 2.5 GT/s, 5 GT/s, 8 GT/s or 16 GT/s.
S-Processor Line: The 16 lanes port can operate at 2.5 GT/s, 5 GT/s, 8 GT/s, 16 GT/s or 32 GT/s**
The PCI Express* architecture is specified in three layers – Transaction Layer, Data Link Layer, and Physical Layer. Refer to the PCI Express Base Specification 5.0 for details of PCI Express* architecture.