12th Generation Intel® Core™ Processors Datasheet, Volume 1 of 2
Datasheet
Terminology and Special Marks
| Term | Description | ||
|---|---|---|---|
| 4K | Ultra High Definition (UHD) | ||
| AES | Advanced Encryption Standard | ||
| AGC | Adaptive Gain Control | ||
| API | Application Programming Interface | ||
| AVC | Advanced Video Coding | ||
| BLT | Block Level Transfer | ||
| BPP | Bits per Pixel | ||
| CDR | Clock and Data Recovery | ||
| CTLE | Continuous Time Linear Equalizer | ||
| DDC | Digital Display Channel | ||
| DDI | Digital Display Interface for DP or HDMI/DVI | ||
| DSI | Display Serial Interface | ||
| DDR4 | Fourth-Generation Double Data Rate SDRAM Memory Technology | ||
| DDR5 | Firth-Generation Double Data Rate SDRAM Memory Technology | ||
| DFE | Decision Feedback Equalizer | ||
| DMA | Direct Memory Access | ||
| DPPM | Dynamic Power Performance Management | ||
| DMI | Direct Media Interface | ||
| DP* | DisplayPort* | ||
| DSC | Display Stream Compression | ||
| DSI | Display Serial Interface | ||
| DTS | Digital Thermal Sensor | ||
| ECC | Error Correction Code - used to fix DDR transactions errors | ||
| eDP* | Embedded DisplayPort* | ||
| EU | Execution Unit in the Graphics Processor | ||
| FIVR | Fully Integrated Voltage Regulator | ||
| GSA | Graphics in System Agent | ||
| GNA | Gauss Newton Algorithm | ||
| HDCP | High-Bandwidth Digital Content Protection | ||
| HDMI* | High Definition Multimedia Interface | ||
| IMC | Integrated Memory Controller | ||
| Intel® 64 Technology | 64-bit memory extensions to the IA-32 architecture | ||
| Intel® DPST | Intel® Display Power Saving Technology | ||
| Intel® PTT | Intel® Platform Trust Technology | ||
| Intel® TXT | Intel® Trusted Execution Technology | ||
| Intel® VT | Intel® Virtualization Technology. Processor Virtualization, when used in conjunction with Virtual Machine Monitor software, enables multiple, robust independent software environments inside a single platform. | ||
| Intel® VT-d | Intel® Virtualization Technology (Intel® VT) for Directed I/O. Intel® VT-d is a hardware assist, under system software (Virtual Machine Manager or OS) control, for enabling I/O device Virtualization. Intel® VT-d also brings robust security by providing protection from errant DMAs by using DMA remapping, a key feature of Intel® VT-d. | ||
| ITH | Intel® Trace Hub | ||
| IOV | I/O Virtualization | ||
| IPU | Image Processing Unit | ||
| LFM | Low Frequency Mode. corresponding to the Enhanced Intel SpeedStep® Technology’s lowest voltage/frequency pair. It can be read at MSR CEh [47:40]. | ||
| LLC | Last Level Cache | ||
| LPSP | Low-Power Single Pipe | ||
| LSF | Lowest Supported Frequency.This frequency is the lowest frequency where manufacturing confirms logical functionality under the set of operating conditions. | ||
| LTR | The Latency Tolerance Reporting (LTR) mechanism enables Endpoints to report their service latency requirements for Memory Reads and Writes to the Root Complex, so that power management policies for central platform resources (such as main memory, RC internal interconnects, and snoop resources) can be implemented to consider Endpoint service requirements. | ||
| MCP | Multi-Chip Package - includes the processor and the PCH. In some SKUs, it might have additional On-Package Cache. | ||
| MFM | Minimum Frequency Mode. MFM is the minimum ratio supported by the processor and can be read from MSR CEh [55:48]. | ||
| MLC | Mid-Level Cache | ||
| MPEG | Motion Picture Expert Group, international standard body JTC1/SC29/WG11 under ISO/IEC that has defined audio and video compression standards such as MPEG-1, MPEG-2, and MPEG-4, etc. | ||
| NCTF | Non-Critical to Function. NCTF locations are typically redundant ground or non-critical reserved balls/lands, so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality. | ||
| PCH | Platform Controller Hub. The chipset with centralized platform capabilities including the main I/O interfaces along with display connectivity, audio features, power management, manageability, security, and storage features. The PCH may also be referred to as “chipset”. | ||
| PECI | Platform Environment Control Interface | ||
| PEG | PCI Express* Graphics | ||
| PL1, PL2, PL3 | Power Limit 1, Power Limit 2, Power Limit 3 | ||
| PMIC | Power Management Integrated Circuit | ||
| Processor | The 64-bit multi-core component (package) | ||
| Processor Core | The term “processor core” refers to the Si die itself, which can contain multiple execution cores. Each execution core has an instruction cache, data cache, and 256-KB L2 cache. All execution cores share the LLC. | ||
| Processor Graphics | Intel® Processor Graphics | ||
| PSR | Panel Self-Refresh | ||
| PSx | Power Save States (PS0, PS1, PS2, PS3, PS4) | ||
| Rank | A unit of DRAM corresponding to four to eight devices in parallel, ignoring ECC. These devices are usually, but not always, mounted on a single side of a SoDIMM. | ||
| SCI | System Control Interrupt. SCI is used in the ACPI protocol. | ||
| SDP | Scenario Design Power | ||
| SHA | Secure Hash Algorithm | ||
| SSC | Spread Spectrum Clock | ||
| Storage Conditions | |||
| STR | Suspend to RAM | ||
| TAC | Thermal Averaging Constant | ||
| TBT | Thunderbolt™ Interface | ||
| TCC | Thermal Control Circuit | ||
| Processor Base Power (a.k.a TDP) | Thermal Design Power | ||
| TTV Processor Base Power (a.k.a TDP) | Thermal Test Vehicle TDP | ||
| VCC | Processor Core Power Supply | ||
| VCCGT | Processor Graphics Power Supply | ||
| VCCSA | System Agent Power Supply | ||
| VLD | Variable Length Decoding | ||
| VPID | Virtual Processor ID | ||
| VSS | Processor Ground | ||
| D0ix-states | USB controller power states ranging from D0i0 to D0i3, where D0i0 is fully powered on and D0i3 is primarily powered off. Controlled by SW. | ||
| S0ix-states | Processor residency idle standby power states. |
| Mark | Definition |
|---|---|
| [] | Brackets ([]) sometimes follow a ball, pin, registers or a bit name. These brackets enclose a range of numbers, for example, TCP[2:0]_TXRX_P[1:0] may refer to four USB-C* pins or EAX[7:0] may indicate a range that is 8 bits length. |
| _N / # / B | A suffix of _N or # or B indicates an active low signal. For example, CATERR# _N does not refer to a differential pair of signals such as CLK_P, CLK_N |
| 0x000 | Hexadecimal numbers are identified with an x in the number. All numbers are decimal (base 10) unless otherwise specified. Non-obvious binary numbers have the ‘b’ enclosed at the end of the number. For example, 0101b |