12th Generation Intel® Core™ Processors Datasheet, Volume 1 of 2
PCI Express* Hot Plug
All PCIe* Root Ports support Express Card 1.0 based hot - plug that performs the following:
- Presence Detect and Link Active Changed Support
- Interrupt Generation Support
- For hot plug support, please refer to the below table
|Port||GEN||S - Processor|
When a module is plugged in and power is supplied, the physical layer will detect the presence of the device, and the root port sets SLSTS.PDS and SLSTS.PDC. If SLCTL.PDE and SLCTL.HPE are both set, the root port will also generate an interrupt.
When a module is removed (using the physical layer detection), the root port clears SLSTS.PDS and sets SLSTS.PDC. If SLCTL.PDE and SLCTL.HPE are both set, the root port will also generate an interrupt.
Interrupts for power - management events are not supported on legacy operating systems. To support power - management on non - PCI Express* aware operating systems, power management events can be routed to generate SCI. To generate SCI, MPC.HPCE must be set. When set, enabled hot - plug events will cause SMSCS.HPCS to be set.
Additionally, BIOS workaround for hot - plug can be supported by setting MPC.HPME. When this bit is set, hot - plug events can cause SMI status bits in SMSCS to be set. Supported hot - plug events and their corresponding SMSCS bit are:
When any of these bits are set, SMI# will be generated. These bits are set regardless of whether interrupts or SCI is enabled for hot - plug events. The SMI# may occur concurrently with an interrupt or SCI.
- SMI is referred to Serial management Interfaces
- SLSTS - Slot Status
- SLCTL - Slot Control
- For full register detail, refer to
12 th Generation Intel ® Core™ Processors Datasheet Volume 2 (655259).