12th Generation Intel® Core™ Processors Datasheet, Volume 1 of 2
Date 28/10/2021 00:00:00
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Security Technologies Intel® Trusted Execution Technology Intel® Advanced Encryption Standard New Instructions Perform Carry-Less Multiplication Quad Word Instruction Intel® Secure Key Execute Disable Bit Boot Guard Technology Intel® Supervisor Mode Execution Protection Intel® Supervisor Mode Access Protection Intel® Secure Hash Algorithm Extensions User Mode Instruction Prevention Read Processor ID Intel® Multi-Key Total Memory Encryption Intel® Control-flow Enforcement Technology KeyLocker Technology Devil’s Gate Rock
Power and Performance Technologies Intel® Smart Cache Technology IA Cores Level 1 and Level 2 Caches Ring Interconnect Intel® Hybrid Technology Intel® Turbo Boost Max Technology 3.0 Intel® Hyper-Threading Technology Intel® Turbo Boost Technology 2.0 Enhanced Intel SpeedStep® Technology Intel® Thermal Velocity Boost (Intel® TVB) Intel® Speed Shift Technology Intel® Advanced Vector Extensions 2 (Intel® AVX2) Intel® 64 Architecture x2APIC Intel® Dynamic Tuning Technology Intel® GMM and Neural Network Accelerator Cache Line Write Back Remote Action Request User Mode Wait Instructions
Power Management Advanced Configuration and Power Interface (ACPI) States Supported Processor IA Core Power Management Processor AUX Power Management Processor Graphics Power Management System Agent Enhanced Intel SpeedStep® Technology Rest Of Platform (ROP) PMIC PCI Express* Power Management TCSS Power State
Thermal Management Features Adaptive Thermal Monitor Digital Thermal Sensor PROCHOT# Signal PROCHOT Output Only Bi-Directional PROCHOT# PROCHOT Demotion Algorithm Voltage Regulator Protection using PROCHOT# Thermal Solution Design and PROCHOT# Behavior Low-Power States and PROCHOT# Behavior THRMTRIP# Signal Critical Temperature Detection On-Demand Mode MSR Based On-Demand Mode I/O Emulation-Based On-Demand Mode
System Memory Interface Processor SKU Support Matrix Supported Memory Modules and Devices System Memory Timing Support Memory Controller (MC) Memory Controller Power Gate System Memory Controller Organization Mode (DDR4/5 Only) System Memory Frequency Technology Enhancements of Intel® Fast Memory Access (Intel® FMA) Data Scrambling Data Swapping DDR I/O Interleaving DRAM Clock Generation DRAM Reference Voltage Generation Data Swizzling Error Correction With Standard RAM Post Package Repair (PPR)
Signal Description System Memory Interface PCI Express* Graphics (PEG) Signals Direct Media Interface (DMI) Signals Reset and Miscellaneous Signals Display Interfaces Processor Clocking Signals Testability Signals Error and Thermal Protection Signals Power Sequencing Signals Processor Power Rails Ground and Reserved Signals Processor Internal Pull-Up / Pull-Down Terminations
Intel® 64 Architecture x2APIC
The x2APIC architecture extends the xAPIC architecture that provides key mechanisms for interrupt delivery. This extension is primarily intended to increase processor addressability.
- Retains all key elements of compatibility to the xAPIC architecture:
- Delivery modes
- Interrupt and processor priorities
- Interrupt sources
- Interrupt destination types
- Provides extensions to scale processor addressability for both the logical and physical destination modes
- Adds new features to enhance the performance of interrupt delivery
- Reduces the complexity of logical destination mode interrupt delivery on link based architectures
The key enhancements provided by the x2APIC architecture over xAPIC are the following:
- Support for two modes of operation to provide backward compatibility and extensibility for future platform innovations:
- In xAPIC compatibility mode, APIC registers are accessed through memory mapped interface to a 4K-Byte page, identical to the xAPIC architecture.
- In the x2APIC mode, APIC registers are accessed through the Model Specific Register (MSR) interfaces. In this mode, the x2APIC architecture provides significantly increased processor addressability and some enhancements on interrupt delivery.
- Increased range of processor addressability in x2APIC mode:
- Physical xAPIC ID field increases from 8 bits to 32 bits, allowing for interrupt processor addressability up to 4G-1 processors in physical destination mode. A processor implementation of x2APIC architecture can support fewer than 32-bits in a software transparent fashion.
- Logical xAPIC ID field increases from 8 bits to 32 bits. The 32-bit logical x2APIC ID is partitioned into two sub-fields – a 16-bit cluster ID and a 16-bit logical ID within the cluster. Consequently, ((2^20) - 16) processors can be addressed in logical destination mode. Processor implementations can support fewer than 16 bits in the cluster ID sub-field and logical ID sub-field in a software agnostic fashion.
- More efficient MSR interface to access APIC registers:
- To enhance inter-processor and self-directed interrupt delivery as well as the ability to virtualize the local APIC, the APIC register set can be accessed only through MSR-based interfaces in x2APIC mode. The Memory Mapped IO (MMIO) interface used by xAPIC is not supported in x2APIC mode.
- The semantics for accessing APIC registers have been revised to simplify the programming of frequently-used APIC registers by system software. Specifically, the software semantics for using the Interrupt Command Register (ICR) and End Of Interrupt (EOI) registers have been modified to allow for more efficient delivery and dispatching of interrupts.
- The x2APIC extensions are made available to system software by enabling the local x2APIC unit in the “x2APIC” mode. To benefit from x2APIC capabilities, a new operating system and a new BIOS are both needed, with special support for the x2APIC mode.
- The x2APIC architecture provides backward compatibility to the xAPIC architecture and forwards extensible for future Intel platform innovations.
For more information, refer to the Intel® 64 Architecture x2APIC Specification at http://www.intel.com/products/processor/manuals/