Intel® Core™ Ultra Series 3 Processors I/O Registers

ID Date Version Classification
872352 04/14/2026 001 Public
Document Table of Contents
Document Table of Contents
Introduction 8254 Timer I/O Advanced Programmable Interrupt (APIC) Index Advanced Programmable Interrupt (APIC) Mem Audio Memory Mapped I/O Audio PCI Configuration CNVi Bluetooth* PCI Configuration CNVi WiFi* PCI Configuration eSPI PCI Configuration (D31:F0) eSPI PCR GPIO Community 0 GPIO Community 1 GPIO Community 3 GPIO Community 4 GPIO Community 5 GSPI Additional MMIO GSPI DMA Controller GSPI PCI Configuration (D30:F2/3, D18:F6) GSPI0 MMIO High Precision Event Timer (HPET) MMIO I/O Trap I2C Additional MMIO I2C DMA Controller I2C MMIO I2C PCI Configuration (D21:F0/1/2/3; D25:F0/1) I3C Additional MMIO I3C Additional MMIO I3C DMA Controller I3C MMIO I3C PCI Configuration (D17:F0/1) IDE Redirection (IDE-R) PCI Configuration (D22:F2) Integrated GbE Configuration (D31:F6) Intel® CSME HECI 1 Memory Mapped I/O Intel® CSME HECI 2 Memory Mapped I/O Intel® CSME HECI 3 Memory Mapped I/O Intel® CSME HECI 4 Memory Mapped I/O Intel® CSME HECI PCI Configuration (D22:F0/1/4/5) Intel® Trace Hub PCI Configuration (D31:F7) Intel® Trusted Execution Technology Configuration Intergrated Sensor Hub (ISH) PCI Configuration (D18:F0) Interrupt I/O Interrupt PCR iSCLK Camera Registers Keyboard and Text (KT) Redirection PCI Configuration (D22:F3) P2SB Bridge PCI Configuration (D31:F1, D18:F1) PCI Express* (PCIe*) Configuration (D28:F0/1/2/3/4/5/6/7) PCI Express* (PCIe*) Configuration (D6:F0/1) (Gen 5) PMC I/O Based PMC MMIO PMC PCI Configuration (D31:F2) Processor I/O RTC I/O RTC Index RTC PCR Shared SRAM PCI Configuration (D20:F2) SMBus I/O SMBus MMIO SMBus PCI Configuration (D31:F4) SMBus PCR SMBus TCO I/O SPI MMIO SPI PCI Configuration (D31:F5) Touch Host Controller (THC) MMIO Common Touch Host Controller (THC) MMIO Port Touch Host Controller (THC) PCI Configuration (D16:F0/1) TPM Configuration Type-C Subsystem xHCI PCI Configuration (D13:F0) UART Additional MMIO UART MMIO UART PCI Configuration (D30:F0/1, D25:F2) USB Type-C Subsystem PCIe Root Port PCI Configuration (D7:F0/1/2/3) xDCI (USB Device Control) MMIO Device xDCI (USB Device Control) MMIO Global xDCI (USB Device Control) PCI Configuration (D20:F1) xHCI MMIO xHCI PCI Configuration (D20:F0)
Introduction
8254 Timer I/O
8254 Timer I/O Counter 0_Counter Access Ports Register (C0_CAPR) Counter 0_Interval Timer Status Byte Format Register (C0_ITSBFR) Counter 2_Counter Access Ports Register (C2_CAPR) Counter 2_Interval Timer Status Byte Format Register (C2_ITSBFR) Counter Latch Command (CLC) Read Back Command (RBC) Timer Control Word Register (TCW)
Counter 0_Counter Access Ports Register (C0_CAPR)
Counter 0_Interval Timer Status Byte Format Register (C0_ITSBFR)
Counter 2_Counter Access Ports Register (C2_CAPR)
Counter 2_Interval Timer Status Byte Format Register (C2_ITSBFR)
Counter Latch Command (CLC)
Read Back Command (RBC)
Timer Control Word Register (TCW)
Advanced Programmable Interrupt (APIC) Index
Advanced Programmable Interrupt (APIC) Index Identification Register (IDR) Version Register (VS) Redirection Table Entry 0 (RTE0) Redirection Table Entry 1 (RTE1) Redirection Table Entry 2 (RTE2) Redirection Table Entry 3 (RTE3) Redirection Table Entry 4 (RTE4) Redirection Table Entry 5 (RTE5) Redirection Table Entry 6 (RTE6) Redirection Table Entry 7 (RTE7) Redirection Table Entry 8 (RTE8) Redirection Table Entry 9 (RTE9) Redirection Table Entry 10 (RTE10) Redirection Table Entry 11 (RTE11) Redirection Table Entry 12 (RTE12) Redirection Table Entry 13 (RTE13) Redirection Table Entry 14 (RTE14) Redirection Table Entry 15 (RTE15) Redirection Table Entry 16 (RTE16) Redirection Table Entry 17 (RTE17) Redirection Table Entry 18 (RTE18) Redirection Table Entry 19 (RTE19) Redirection Table Entry 20 (RTE20) Redirection Table Entry 21 (RTE21) Redirection Table Entry 22 (RTE22) Redirection Table Entry 23 (RTE23) Redirection Table Entry 24 (RTE24) Redirection Table Entry 25 (RTE25) Redirection Table Entry 26 (RTE26) Redirection Table Entry 27 (RTE27) Redirection Table Entry 28 (RTE28) Redirection Table Entry 29 (RTE29) Redirection Table Entry 30 (RTE30) Redirection Table Entry 31 (RTE31) Redirection Table Entry 32 (RTE32) Redirection Table Entry 33 (RTE33) Redirection Table Entry 34 (RTE34) Redirection Table Entry 35 (RTE35) Redirection Table Entry 36 (RTE36) Redirection Table Entry 37 (RTE37) Redirection Table Entry 38 (RTE38) Redirection Table Entry 39 (RTE39) Redirection Table Entry 40 (RTE40) Redirection Table Entry 41 (RTE41) Redirection Table Entry 42 (RTE42) Redirection Table Entry 43 (RTE43) Redirection Table Entry 44 (RTE44) Redirection Table Entry 45 (RTE45) Redirection Table Entry 46 (RTE46) Redirection Table Entry 47 (RTE47) Redirection Table Entry 48 (RTE48) Redirection Table Entry 49 (RTE49) Redirection Table Entry 50 (RTE50) Redirection Table Entry 51 (RTE51) Redirection Table Entry 52 (RTE52) Redirection Table Entry 53 (RTE53) Redirection Table Entry 54 (RTE54) Redirection Table Entry 55 (RTE55) Redirection Table Entry 56 (RTE56) Redirection Table Entry 57 (RTE57) Redirection Table Entry 58 (RTE58) Redirection Table Entry 59 (RTE59) Redirection Table Entry 60 (RTE60) Redirection Table Entry 61 (RTE61) Redirection Table Entry 62 (RTE62) Redirection Table Entry 63 (RTE63) Redirection Table Entry 64 (RTE64) Redirection Table Entry 65 (RTE65) Redirection Table Entry 66 (RTE66) Redirection Table Entry 67 (RTE67) Redirection Table Entry 68 (RTE68) Redirection Table Entry 69 (RTE69) Redirection Table Entry 70 (RTE70) Redirection Table Entry 71 (RTE71) Redirection Table Entry 72 (RTE72) Redirection Table Entry 73 (RTE73) Redirection Table Entry 74 (RTE74) Redirection Table Entry 75 (RTE75) Redirection Table Entry 76 (RTE76) Redirection Table Entry 77 (RTE77) Redirection Table Entry 78 (RTE78) Redirection Table Entry 79 (RTE79) Redirection Table Entry 80 (RTE80) Redirection Table Entry 81 (RTE81) Redirection Table Entry 82 (RTE82) Redirection Table Entry 83 (RTE83) Redirection Table Entry 84 (RTE84) Redirection Table Entry 85 (RTE85) Redirection Table Entry 86 (RTE86) Redirection Table Entry 87 (RTE87) Redirection Table Entry 88 (RTE88) Redirection Table Entry 89 (RTE89) Redirection Table Entry 90 (RTE90) Redirection Table Entry 91 (RTE91) Redirection Table Entry 92 (RTE92) Redirection Table Entry 93 (RTE93) Redirection Table Entry 94 (RTE94) Redirection Table Entry 95 (RTE95) Redirection Table Entry 96 (RTE96) Redirection Table Entry 97 (RTE97) Redirection Table Entry 98 (RTE98) Redirection Table Entry 99 (RTE99) Redirection Table Entry 100 (RTE100) Redirection Table Entry 101 (RTE101) Redirection Table Entry 102 (RTE102) Redirection Table Entry 103 (RTE103) Redirection Table Entry 104 (RTE104) Redirection Table Entry 105 (RTE105) Redirection Table Entry 106 (RTE106) Redirection Table Entry 107 (RTE107) Redirection Table Entry 108 (RTE108) Redirection Table Entry 109 (RTE109) Redirection Table Entry 110 (RTE110) Redirection Table Entry 111 (RTE111) Redirection Table Entry 112 (RTE112) Redirection Table Entry 113 (RTE113) Redirection Table Entry 114 (RTE114) Redirection Table Entry 115 (RTE115) Redirection Table Entry 116 (RTE116) Redirection Table Entry 117 (RTE117) Redirection Table Entry 118 (RTE118) Redirection Table Entry 119 (RTE119)
Identification Register (IDR)
Version Register (VS)
Redirection Table Entry 0 (RTE0)
Redirection Table Entry 1 (RTE1)
Redirection Table Entry 2 (RTE2)
Redirection Table Entry 3 (RTE3)
Redirection Table Entry 4 (RTE4)
Redirection Table Entry 5 (RTE5)
Redirection Table Entry 6 (RTE6)
Redirection Table Entry 7 (RTE7)
Redirection Table Entry 8 (RTE8)
Redirection Table Entry 9 (RTE9)
Redirection Table Entry 10 (RTE10)
Redirection Table Entry 11 (RTE11)
Redirection Table Entry 12 (RTE12)
Redirection Table Entry 13 (RTE13)
Redirection Table Entry 14 (RTE14)
Redirection Table Entry 15 (RTE15)
Redirection Table Entry 16 (RTE16)
Redirection Table Entry 17 (RTE17)
Redirection Table Entry 18 (RTE18)
Redirection Table Entry 19 (RTE19)
Redirection Table Entry 20 (RTE20)
Redirection Table Entry 21 (RTE21)
Redirection Table Entry 22 (RTE22)
Redirection Table Entry 23 (RTE23)
Redirection Table Entry 24 (RTE24)
Redirection Table Entry 25 (RTE25)
Redirection Table Entry 26 (RTE26)
Redirection Table Entry 27 (RTE27)
Redirection Table Entry 28 (RTE28)
Redirection Table Entry 29 (RTE29)
Redirection Table Entry 30 (RTE30)
Redirection Table Entry 31 (RTE31)
Redirection Table Entry 32 (RTE32)
Redirection Table Entry 33 (RTE33)
Redirection Table Entry 34 (RTE34)
Redirection Table Entry 35 (RTE35)
Redirection Table Entry 36 (RTE36)
Redirection Table Entry 37 (RTE37)
Redirection Table Entry 38 (RTE38)
Redirection Table Entry 39 (RTE39)
Redirection Table Entry 40 (RTE40)
Redirection Table Entry 41 (RTE41)
Redirection Table Entry 42 (RTE42)
Redirection Table Entry 43 (RTE43)
Redirection Table Entry 44 (RTE44)
Redirection Table Entry 45 (RTE45)
Redirection Table Entry 46 (RTE46)
Redirection Table Entry 47 (RTE47)
Redirection Table Entry 48 (RTE48)
Redirection Table Entry 49 (RTE49)
Redirection Table Entry 50 (RTE50)
Redirection Table Entry 51 (RTE51)
Redirection Table Entry 52 (RTE52)
Redirection Table Entry 53 (RTE53)
Redirection Table Entry 54 (RTE54)
Redirection Table Entry 55 (RTE55)
Redirection Table Entry 56 (RTE56)
Redirection Table Entry 57 (RTE57)
Redirection Table Entry 58 (RTE58)
Redirection Table Entry 59 (RTE59)
Redirection Table Entry 60 (RTE60)
Redirection Table Entry 61 (RTE61)
Redirection Table Entry 62 (RTE62)
Redirection Table Entry 63 (RTE63)
Redirection Table Entry 64 (RTE64)
Redirection Table Entry 65 (RTE65)
Redirection Table Entry 66 (RTE66)
Redirection Table Entry 67 (RTE67)
Redirection Table Entry 68 (RTE68)
Redirection Table Entry 69 (RTE69)
Redirection Table Entry 70 (RTE70)
Redirection Table Entry 71 (RTE71)
Redirection Table Entry 72 (RTE72)
Redirection Table Entry 73 (RTE73)
Redirection Table Entry 74 (RTE74)
Redirection Table Entry 75 (RTE75)
Redirection Table Entry 76 (RTE76)
Redirection Table Entry 77 (RTE77)
Redirection Table Entry 78 (RTE78)
Redirection Table Entry 79 (RTE79)
Redirection Table Entry 80 (RTE80)
Redirection Table Entry 81 (RTE81)
Redirection Table Entry 82 (RTE82)
Redirection Table Entry 83 (RTE83)
Redirection Table Entry 84 (RTE84)
Redirection Table Entry 85 (RTE85)
Redirection Table Entry 86 (RTE86)
Redirection Table Entry 87 (RTE87)
Redirection Table Entry 88 (RTE88)
Redirection Table Entry 89 (RTE89)
Redirection Table Entry 90 (RTE90)
Redirection Table Entry 91 (RTE91)
Redirection Table Entry 92 (RTE92)
Redirection Table Entry 93 (RTE93)
Redirection Table Entry 94 (RTE94)
Redirection Table Entry 95 (RTE95)
Redirection Table Entry 96 (RTE96)
Redirection Table Entry 97 (RTE97)
Redirection Table Entry 98 (RTE98)
Redirection Table Entry 99 (RTE99)
Redirection Table Entry 100 (RTE100)
Redirection Table Entry 101 (RTE101)
Redirection Table Entry 102 (RTE102)
Redirection Table Entry 103 (RTE103)
Redirection Table Entry 104 (RTE104)
Redirection Table Entry 105 (RTE105)
Redirection Table Entry 106 (RTE106)
Redirection Table Entry 107 (RTE107)
Redirection Table Entry 108 (RTE108)
Redirection Table Entry 109 (RTE109)
Redirection Table Entry 110 (RTE110)
Redirection Table Entry 111 (RTE111)
Redirection Table Entry 112 (RTE112)
Redirection Table Entry 113 (RTE113)
Redirection Table Entry 114 (RTE114)
Redirection Table Entry 115 (RTE115)
Redirection Table Entry 116 (RTE116)
Redirection Table Entry 117 (RTE117)
Redirection Table Entry 118 (RTE118)
Redirection Table Entry 119 (RTE119)
Advanced Programmable Interrupt (APIC) Mem
Advanced Programmable Interrupt (APIC) Mem Index Register (IDX) Window Register (WDW) EOI Register (EOI)
Index Register (IDX)
Window Register (WDW)
EOI Register (EOI)
Audio Memory Mapped I/O
Audio Memory Mapped I/O Global Capabilities (GCAP) Minor Version (VMIN) Major Version (VMAJ) Output Payload Capability (OUTPAY) Input Payload Capability (INPAY) Global Control (GCTL) Wake Enable (WAKEEN) Wake Status (WAKESTS) Global Status (GSTS) Global Capabilities 2 (GCAP2) Linked List Capabilities Header (LLCH) Output Stream Payload Capability (OUTSTRMPAY) Input Stream Payload Capability (INSTRMPAY) Interrupt Control (INTCTL) Interrupt Status (INTSTS) Wall Clock Counter (WALCLK) Stream Synchronization (SSYNC) CORB Lower Base Address (CORBLBASE) CORB Upper Base Address (CORBUBASE) CORB Write Pointer (CORBWP) CORB Read Pointer (CORBRP) CORB Control (CORBCTL) CORB Status (CORBSTS) CORB Size (CORBSIZE) RIRB Lower Base Address (RIRBLBASE) RIRB Upper Base Address (RIRBUBASE) RIRB Write Pointer (RIRBWP) Response Interrupt Count (RINTCNT) RIRB Control (RIRBCTL) RIRB Status (RIRBSTS) RIRB Size (RIRBSIZE) Immediate Command (IC) Immediate Response (IR) Immediate Command Status (ICS) DMA Position Lower Base Address (DPLBASE) DMA Position Upper Base Address (DPUBASE) Input Stream Descriptor x Control (ISD0CTL_B0) Input Stream Descriptor x Control (ISD0CTL_B2) Input Stream Descriptor x Status (ISD0STS) Input Stream Descriptor x Link Position in Buffer (ISD0LPIB) Input Stream Descriptor x Cyclic Buffer Length (ISD0CBL) Input Stream Descriptor x Last Valid Index (ISD0LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD0FIFOW) Input Stream Descriptor x FIFO Size (ISD0FIFOS) Input Stream Descriptor x Format (ISD0FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD0BDLPLBA) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD0BDLPUBA) Input Stream Descriptor x Control (ISD1CTL_B0) Input Stream Descriptor x Control (ISD1CTL_B2) Input Stream Descriptor x Status (ISD1STS) Input Stream Descriptor x Link Position in Buffer (ISD1LPIB) Input Stream Descriptor x Cyclic Buffer Length (ISD1CBL) Input Stream Descriptor x Last Valid Index (ISD1LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD1FIFOW) Input Stream Descriptor x FIFO Size (ISD1FIFOS) Input Stream Descriptor x Format (ISD1FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD1BDLPLBA) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD1BDLPUBA) Input Stream Descriptor x Control (ISD2CTL_B0) Input Stream Descriptor x Control (ISD2CTL_B2) Input Stream Descriptor x Status (ISD2STS) Input Stream Descriptor x Link Position in Buffer (ISD2LPIB) Input Stream Descriptor x Cyclic Buffer Length (ISD2CBL) Input Stream Descriptor x Last Valid Index (ISD2LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD2FIFOW) Input Stream Descriptor x FIFO Size (ISD2FIFOS) Input Stream Descriptor x Format (ISD2FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD2BDLPLBA) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD2BDLPUBA) Input Stream Descriptor x Control (ISD3CTL_B0) Input Stream Descriptor x Control (ISD3CTL_B2) Input Stream Descriptor x Status (ISD3STS) Input Stream Descriptor x Link Position in Buffer (ISD3LPIB) Input Stream Descriptor x Cyclic Buffer Length (ISD3CBL) Input Stream Descriptor x Last Valid Index (ISD3LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD3FIFOW) Input Stream Descriptor x FIFO Size (ISD3FIFOS) Input Stream Descriptor x Format (ISD3FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD3BDLPLBA) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD3BDLPUBA) Input Stream Descriptor x Control (ISD4CTL_B0) Input Stream Descriptor x Control (ISD4CTL_B2) Input Stream Descriptor x Status (ISD4STS) Input Stream Descriptor x Link Position in Buffer (ISD4LPIB) Input Stream Descriptor x Cyclic Buffer Length (ISD4CBL) Input Stream Descriptor x Last Valid Index (ISD4LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD4FIFOW) Input Stream Descriptor x FIFO Size (ISD4FIFOS) Input Stream Descriptor x Format (ISD4FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD4BDLPLBA) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD4BDLPUBA) Input Stream Descriptor x Control (ISD5CTL_B0) Input Stream Descriptor x Control (ISD5CTL_B2) Input Stream Descriptor x Status (ISD5STS) Input Stream Descriptor x Link Position in Buffer (ISD5LPIB) Input Stream Descriptor x Cyclic Buffer Length (ISD5CBL) Input Stream Descriptor x Last Valid Index (ISD5LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD5FIFOW) Input Stream Descriptor x FIFO Size (ISD5FIFOS) Input Stream Descriptor x Format (ISD5FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD5BDLPLBA) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD5BDLPUBA) Input Stream Descriptor x Control (ISD6CTL_B0) Input Stream Descriptor x Control (ISD6CTL_B2) Input Stream Descriptor x Status (ISD6STS) Input Stream Descriptor x Link Position in Buffer (ISD6LPIB) Input Stream Descriptor x Cyclic Buffer Length (ISD6CBL) Input Stream Descriptor x Last Valid Index (ISD6LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD6FIFOW) Input Stream Descriptor x FIFO Size (ISD6FIFOS) Input Stream Descriptor x Format (ISD6FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD6BDLPLBA) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD6BDLPUBA) Input Stream Descriptor x Control (ISD7CTL_B0) Input Stream Descriptor x Control (ISD7CTL_B2) Input Stream Descriptor x Status (ISD7STS) Input Stream Descriptor x Link Position in Buffer (ISD7LPIB) Input Stream Descriptor x Cyclic Buffer Length (ISD7CBL) Input Stream Descriptor x Last Valid Index (ISD7LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD7FIFOW) Input Stream Descriptor x FIFO Size (ISD7FIFOS) Input Stream Descriptor x Format (ISD7FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD7BDLPLBA) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD7BDLPUBA) Input Stream Descriptor x Control (ISD8CTL_B0) Input Stream Descriptor x Control (ISD8CTL_B2) Input Stream Descriptor x Status (ISD8STS) Input Stream Descriptor x Link Position in Buffer (ISD8LPIB) Input Stream Descriptor x Cyclic Buffer Length (ISD8CBL) Input Stream Descriptor x Last Valid Index (ISD8LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD8FIFOW) Input Stream Descriptor x FIFO Size (ISD8FIFOS) Input Stream Descriptor x Format (ISD8FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD8BDLPLBA) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD8BDLPUBA) Input Stream Descriptor x Control (ISD9CTL_B0) Input Stream Descriptor x Control (ISD9CTL_B2) Input Stream Descriptor x Status (ISD9STS) Input Stream Descriptor x Link Position in Buffer (ISD9LPIB) Input Stream Descriptor x Cyclic Buffer Length (ISD9CBL) Input Stream Descriptor x Last Valid Index (ISD9LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD9FIFOW) Input Stream Descriptor x FIFO Size (ISD9FIFOS) Input Stream Descriptor x Format (ISD9FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD9BDLPLBA) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD9BDLPUBA) Input Stream Descriptor x Control (ISD10CTL_B0) Input Stream Descriptor x Control (ISD10CTL_B2) Input Stream Descriptor x Status (ISD10STS) Input Stream Descriptor x Link Position in Buffer (ISD10LPIB) Input Stream Descriptor x Cyclic Buffer Length (ISD10CBL) Input Stream Descriptor x Last Valid Index (ISD10LVI) Input Stream Descriptor x FIFO Eviction Watermark (ISD10FIFOW) Input Stream Descriptor x FIFO Size (ISD10FIFOS) Input Stream Descriptor x Format (ISD10FMT) Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD10BDLPLBA) Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD10BDLPUBA) Output Stream Descriptor x Control (OSD0CTL_B0) Output Stream Descriptor x Control (OSD0CTL_B2) Output Stream Descriptor x Status (OSD0STS) Output Stream Descriptor x Link Position in Buffer (OSD0LPIB) Output Stream Descriptor x Cyclic Buffer Length (OSD0CBL) Output Stream Descriptor x Last Valid Index (OSD0LVI) Output Stream Descriptor x FIFO Eviction Watermark (OSD0FIFOW) Output Stream Descriptor x FIFO Size (OSD0FIFOS) Output Stream Descriptor x Format (OSD0FMT) Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD0BDLPLBA) Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD0BDLPUBA) Output Stream Descriptor x Control (OSD1CTL_B0) Output Stream Descriptor x Control (OSD1CTL_B2) Output Stream Descriptor x Status (OSD1STS) Output Stream Descriptor x Link Position in Buffer (OSD1LPIB) Output Stream Descriptor x Cyclic Buffer Length (OSD1CBL) Output Stream Descriptor x Last Valid Index (OSD1LVI) Output Stream Descriptor x FIFO Eviction Watermark (OSD1FIFOW) Output Stream Descriptor x FIFO Size (OSD1FIFOS) Output Stream Descriptor x Format (OSD1FMT) Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD1BDLPLBA) Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD1BDLPUBA) Output Stream Descriptor x Control (OSD2CTL_B0) Output Stream Descriptor x Control (OSD2CTL_B2) Output Stream Descriptor x Status (OSD2STS) Output Stream Descriptor x Link Position in Buffer (OSD2LPIB) Output Stream Descriptor x Cyclic Buffer Length (OSD2CBL) Output Stream Descriptor x Last Valid Index (OSD2LVI) Output Stream Descriptor x FIFO Eviction Watermark (OSD2FIFOW) Output Stream Descriptor x FIFO Size (OSD2FIFOS) Output Stream Descriptor x Format (OSD2FMT) Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD2BDLPLBA) Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD2BDLPUBA) Output Stream Descriptor x Control (OSD3CTL_B0) Output Stream Descriptor x Control (OSD3CTL_B2) Output Stream Descriptor x Status (OSD3STS) Output Stream Descriptor x Link Position in Buffer (OSD3LPIB) Output Stream Descriptor x Cyclic Buffer Length (OSD3CBL) Output Stream Descriptor x Last Valid Index (OSD3LVI) Output Stream Descriptor x FIFO Eviction Watermark (OSD3FIFOW) Output Stream Descriptor x FIFO Size (OSD3FIFOS) Output Stream Descriptor x Format (OSD3FMT) Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD3BDLPLBA) Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD3BDLPUBA) Output Stream Descriptor x Control (OSD4CTL_B0) Output Stream Descriptor x Control (OSD4CTL_B2) Output Stream Descriptor x Status (OSD4STS) Output Stream Descriptor x Link Position in Buffer (OSD4LPIB) Output Stream Descriptor x Cyclic Buffer Length (OSD4CBL) Output Stream Descriptor x Last Valid Index (OSD4LVI) Output Stream Descriptor x FIFO Eviction Watermark (OSD4FIFOW) Output Stream Descriptor x FIFO Size (OSD4FIFOS) Output Stream Descriptor x Format (OSD4FMT) Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD4BDLPLBA) Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD4BDLPUBA) Output Stream Descriptor x Control (OSD5CTL_B0) Output Stream Descriptor x Control (OSD5CTL_B2) Output Stream Descriptor x Status (OSD5STS) Output Stream Descriptor x Link Position in Buffer (OSD5LPIB) Output Stream Descriptor x Cyclic Buffer Length (OSD5CBL) Output Stream Descriptor x Last Valid Index (OSD5LVI) Output Stream Descriptor x FIFO Eviction Watermark (OSD5FIFOW) Output Stream Descriptor x FIFO Size (OSD5FIFOS) Output Stream Descriptor x Format (OSD5FMT) Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD5BDLPLBA) Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD5BDLPUBA) Output Stream Descriptor x Control (OSD6CTL_B0) Output Stream Descriptor x Control (OSD6CTL_B2) Output Stream Descriptor x Status (OSD6STS) Output Stream Descriptor x Link Position in Buffer (OSD6LPIB) Output Stream Descriptor x Cyclic Buffer Length (OSD6CBL) Output Stream Descriptor x Last Valid Index (OSD6LVI) Output Stream Descriptor x FIFO Eviction Watermark (OSD6FIFOW) Output Stream Descriptor x FIFO Size (OSD6FIFOS) Output Stream Descriptor x Format (OSD6FMT) Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD6BDLPLBA) Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD6BDLPUBA) Output Stream Descriptor x Control (OSD7CTL_B0) Output Stream Descriptor x Control (OSD7CTL_B2) Output Stream Descriptor x Status (OSD7STS) Output Stream Descriptor x Link Position in Buffer (OSD7LPIB) Output Stream Descriptor x Cyclic Buffer Length (OSD7CBL) Output Stream Descriptor x Last Valid Index (OSD7LVI) Output Stream Descriptor x FIFO Eviction Watermark (OSD7FIFOW) Output Stream Descriptor x FIFO Size (OSD7FIFOS) Output Stream Descriptor x Format (OSD7FMT) Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD7BDLPLBA) Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD7BDLPUBA) Output Stream Descriptor x Control (OSD8CTL_B0) Output Stream Descriptor x Control (OSD8CTL_B2) Output Stream Descriptor x Status (OSD8STS) Output Stream Descriptor x Link Position in Buffer (OSD8LPIB) Output Stream Descriptor x Cyclic Buffer Length (OSD8CBL) Output Stream Descriptor x Last Valid Index (OSD8LVI) Output Stream Descriptor x FIFO Eviction Watermark (OSD8FIFOW) Output Stream Descriptor x FIFO Size (OSD8FIFOS) Output Stream Descriptor x Format (OSD8FMT) Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD8BDLPLBA) Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD8BDLPUBA) DMA Resume Capability Header (DRSMCH) DMA Resume Control (DRSMCTL) Input Stream Descriptor x DMA Position in Buffer Resume (ISD0DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (ISD1DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (ISD2DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (ISD3DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (ISD4DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (ISD5DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (ISD6DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (ISD7DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (ISD8DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (ISD9DPIBR) Input Stream Descriptor x DMA Position in Buffer Resume (ISD10DPIBR) Output Stream Descriptor x DMA Position in Buffer Resume (OSD0DPIBR) Output Stream Descriptor x DMA Position in Buffer Resume (OSD1DPIBR) Output Stream Descriptor x DMA Position in Buffer Resume (OSD2DPIBR) Output Stream Descriptor x DMA Position in Buffer Resume (OSD3DPIBR) Output Stream Descriptor x DMA Position in Buffer Resume (OSD4DPIBR) Output Stream Descriptor x DMA Position in Buffer Resume (OSD5DPIBR) Output Stream Descriptor x DMA Position in Buffer Resume (OSD6DPIBR) Output Stream Descriptor x DMA Position in Buffer Resume (OSD7DPIBR) Output Stream Descriptor x DMA Position in Buffer Resume (OSD8DPIBR) Software Position Based FIFO Capability Header (SPBFCH) Software Position Based FIFO Control (SPBFCTL) Input Stream Descriptor x Software Position in Buffer (ISD0SPIB) Input Stream Descriptor x Max FIFO Size (ISD0MAXFIFOS) Input Stream Descriptor x Software Position in Buffer (ISD1SPIB) Input Stream Descriptor x Max FIFO Size (ISD1MAXFIFOS) Input Stream Descriptor x Software Position in Buffer (ISD2SPIB) Input Stream Descriptor x Max FIFO Size (ISD2MAXFIFOS) Input Stream Descriptor x Software Position in Buffer (ISD3SPIB) Input Stream Descriptor x Max FIFO Size (ISD3MAXFIFOS) Input Stream Descriptor x Software Position in Buffer (ISD4SPIB) Input Stream Descriptor x Max FIFO Size (ISD4MAXFIFOS) Input Stream Descriptor x Software Position in Buffer (ISD5SPIB) Input Stream Descriptor x Max FIFO Size (ISD5MAXFIFOS) Input Stream Descriptor x Software Position in Buffer (ISD6SPIB) Input Stream Descriptor x Max FIFO Size (ISD6MAXFIFOS) Input Stream Descriptor x Software Position in Buffer (ISD7SPIB) Input Stream Descriptor x Max FIFO Size (ISD7MAXFIFOS) Input Stream Descriptor x Software Position in Buffer (ISD8SPIB) Input Stream Descriptor x Max FIFO Size (ISD8MAXFIFOS) Input Stream Descriptor x Software Position in Buffer (ISD9SPIB) Input Stream Descriptor x Max FIFO Size (ISD9MAXFIFOS) Input Stream Descriptor x Software Position in Buffer (ISD10SPIB) Input Stream Descriptor x Max FIFO Size (ISD10MAXFIFOS) Output Stream Descriptor x Software Position in Buffer (OSD0SPIB) Output Stream Descriptor x Max FIFO Size (OSD0MAXFIFOS) Output Stream Descriptor x Software Position in Buffer (OSD1SPIB) Output Stream Descriptor x Max FIFO Size (OSD1MAXFIFOS) Output Stream Descriptor x Software Position in Buffer (OSD2SPIB) Output Stream Descriptor x Max FIFO Size (OSD2MAXFIFOS) Output Stream Descriptor x Software Position in Buffer (OSD3SPIB) Output Stream Descriptor x Max FIFO Size (OSD3MAXFIFOS) Output Stream Descriptor x Software Position in Buffer (OSD4SPIB) Output Stream Descriptor x Max FIFO Size (OSD4MAXFIFOS) Output Stream Descriptor x Software Position in Buffer (OSD5SPIB) Output Stream Descriptor x Max FIFO Size (OSD5MAXFIFOS) Output Stream Descriptor x Software Position in Buffer (OSD6SPIB) Output Stream Descriptor x Max FIFO Size (OSD6MAXFIFOS) Output Stream Descriptor x Software Position in Buffer (OSD7SPIB) Output Stream Descriptor x Max FIFO Size (OSD7MAXFIFOS) Output Stream Descriptor x Software Position in Buffer (OSD8SPIB) Output Stream Descriptor x Max FIFO Size (OSD8MAXFIFOS) Processing Pipe Capability Header (PPCH) Processing Pipe Control (PPCTL) Processing Pipe Status (PPSTS) Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC0LLPL) Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC0LLPU) Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC0LDPL) Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC0LDPU) Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC1LLPL) Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC1LLPU) Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC1LDPL) Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC1LDPU) Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC2LLPL) Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC2LLPU) Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC2LDPL) Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC2LDPU) Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC3LLPL) Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC3LLPU) Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC3LDPL) Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC3LDPU) Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC4LLPL) Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC4LLPU) Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC4LDPL) Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC4LDPU) Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC5LLPL) Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC5LLPU) Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC5LDPL) Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC5LDPU) Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC6LLPL) Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC6LLPU) Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC6LDPL) Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC6LDPU) Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC7LLPL) Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC7LLPU) Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC7LDPL) Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC7LDPU) Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC8LLPL) Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC8LLPU) Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC8LDPL) Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC8LDPU) Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC9LLPL) Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC9LLPU) Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC9LDPL) Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC9LDPU) Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC10LLPL) Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC10LLPU) Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC10LDPL) Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC10LDPU) Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC0LLPL) Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC0LLPU) Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC0LDPL) Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC0LDPU) Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC1LLPL) Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC1LLPU) Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC1LDPL) Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC1LDPU) Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC2LLPL) Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC2LLPU) Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC2LDPL) Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC2LDPU) Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC3LLPL) Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC3LLPU) Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC3LDPL) Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC3LDPU) Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC4LLPL) Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC4LLPU) Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC4LDPL) Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC4LDPU) Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC5LLPL) Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC5LLPU) Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC5LDPL) Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC5LDPU) Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC6LLPL) Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC6LLPU) Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC6LDPL) Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC6LDPU) Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC7LLPL) Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC7LLPU) Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC7LDPL) Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC7LDPU) Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC8LLPL) Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC8LLPU) Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC8LDPL) Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC8LDPU) Input Processing Pipe Link Connection x Control (IPPLC0CTL) Input Processing Pipe Link Connection x Format (IPPLC0FMT) Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC0LLPL) Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC0LLPU) Input Processing Pipe Link Connection x Control (IPPLC1CTL) Input Processing Pipe Link Connection x Format (IPPLC1FMT) Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC1LLPL) Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC1LLPU) Input Processing Pipe Link Connection x Control (IPPLC2CTL) Input Processing Pipe Link Connection x Format (IPPLC2FMT) Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC2LLPL) Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC2LLPU) Input Processing Pipe Link Connection x Control (IPPLC3CTL) Input Processing Pipe Link Connection x Format (IPPLC3FMT) Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC3LLPL) Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC3LLPU) Input Processing Pipe Link Connection x Control (IPPLC4CTL) Input Processing Pipe Link Connection x Format (IPPLC4FMT) Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC4LLPL) Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC4LLPU) Input Processing Pipe Link Connection x Control (IPPLC5CTL) Input Processing Pipe Link Connection x Format (IPPLC5FMT) Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC5LLPL) Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC5LLPU) Input Processing Pipe Link Connection x Control (IPPLC6CTL) Input Processing Pipe Link Connection x Format (IPPLC6FMT) Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC6LLPL) Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC6LLPU) Input Processing Pipe Link Connection x Control (IPPLC7CTL) Input Processing Pipe Link Connection x Format (IPPLC7FMT) Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC7LLPL) Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC7LLPU) Input Processing Pipe Link Connection x Control (IPPLC8CTL) Input Processing Pipe Link Connection x Format (IPPLC8FMT) Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC8LLPL) Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC8LLPU) Input Processing Pipe Link Connection x Control (IPPLC9CTL) Input Processing Pipe Link Connection x Format (IPPLC9FMT) Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC9LLPL) Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC9LLPU) Input Processing Pipe Link Connection x Control (IPPLC10CTL) Input Processing Pipe Link Connection x Format (IPPLC10FMT) Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC10LLPL) Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC10LLPU) Output Processing Pipe Link Connection x Control (OPPLC0CTL) Output Processing Pipe Link Connection x Format (OPPLC0FMT) Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC0LLPL) Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC0LLPU) Output Processing Pipe Link Connection x Control (OPPLC1CTL) Output Processing Pipe Link Connection x Format (OPPLC1FMT) Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC1LLPL) Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC1LLPU) Output Processing Pipe Link Connection x Control (OPPLC2CTL) Output Processing Pipe Link Connection x Format (OPPLC2FMT) Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC2LLPL) Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC2LLPU) Output Processing Pipe Link Connection x Control (OPPLC3CTL) Output Processing Pipe Link Connection x Format (OPPLC3FMT) Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC3LLPL) Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC3LLPU) Output Processing Pipe Link Connection x Control (OPPLC4CTL) Output Processing Pipe Link Connection x Format (OPPLC4FMT) Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC4LLPL) Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC4LLPU) Output Processing Pipe Link Connection x Control (OPPLC5CTL) Output Processing Pipe Link Connection x Format (OPPLC5FMT) Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC5LLPL) Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC5LLPU) Output Processing Pipe Link Connection x Control (OPPLC6CTL) Output Processing Pipe Link Connection x Format (OPPLC6FMT) Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC6LLPL) Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC6LLPU) Output Processing Pipe Link Connection x Control (OPPLC7CTL) Output Processing Pipe Link Connection x Format (OPPLC7FMT) Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC7LLPL) Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC7LLPU) Output Processing Pipe Link Connection x Control (OPPLC8CTL) Output Processing Pipe Link Connection x Format (OPPLC8FMT) Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC8LLPL) Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC8LLPU) Multiple Links Capability Header (MLCH) Multiple Links Capability Declaration (MLCD) HD-A Link Capabilities (HDALCAP) HD-A Link Control (HDALCTL) HD-A Link Output Stream ID Valid (HDALOSIDV) HD-A Link SDI IDentifiers (HDALSDIID) iDisp-A Link Capabilities (IDALCAP) iDisp-A Link Control (IDALCTL) iDisp-A Link Output Stream ID Valid (IDALOSIDV) iDisp-A Link SDI IDentifiers (IDALSDIID) iDisp-A Link Per Stream Output Overhead (IDALPSOO) iDisp-A Link Per Stream Input Overhead (IDALPSIO) iDisp-A Link Wall Frame Counter (IDALWALFC) iDisp-A Link 6 MHz Output Payload Capability (IDALOUTPAY6) iDisp-A Link 12 MHz Output Payload Capability (IDALOUTPAY12) iDisp-A Link 24 MHz Output Payload Capability (IDALOUTPAY24) iDisp-A Link 48 MHz Output Payload Capability (IDALOUTPAY48) iDisp-A Link 96 MHz Output Payload Capability (IDALOUTPAY96) iDisp-A Link 6 MHz Input Payload Capability (IDALINPAY6) iDisp-A Link 12 MHz Input Payload Capability (IDALINPAY12) iDisp-A Link 24 MHz Input Payload Capability (IDALINPAY24) iDisp-A Link 48 MHz Input Payload Capability (IDALINPAY48) iDisp-A Link 96 MHz Input Payload Capability (IDALINPAY96) DMIC Link Capabilities (DMICLCAP) DMIC Link Control (DMICLCTL) DMIC Link Output Stream ID Valid (DMICLOSIDV) DMIC Link SDI IDentifiers (DMICLSDIID) DMIC Link Synchronization (DMICLSYNC) DMIC Link Extension Pointer (DMICLEPTR) I2S / PCM Link Capabilities (I2SLCAP) I2S / PCM Link Control (I2SLCTL) I2S / PCM Link Output Stream ID Valid (I2SLOSIDV) I2S / PCM Link SDI IDentifiers (I2SLSDIID0) I2S / PCM Link Synchronization (I2SLSYNC) I2S / PCM Link Extension Pointer (I2SLEPTR) USB Audio Offload Link Capabilities (UAOLCAP) USB Audio Offload Link Control (UAOLCTL) USB Audio Offload Link Output Stream ID Valid (UAOLOSIDV) USB Audio Offload Link SDI IDentifiers (UAOLSDIID) USB Audio Offload Link Extension Pointer (UAOLEPTR) SoundWire Link Capabilities (SNDWLCAP) SoundWire Link Control (SNDWLCTL) SoundWire Link Output Stream ID Valid (SNDWLOSIDV) SoundWire Link SDI IDentifiers (SNDWLSDIID0) SoundWire Link SDI IDentifiers (SNDWLSDIID1) SoundWire Link SDI IDentifiers (SNDWLSDIID2) SoundWire Link SDI IDentifiers (SNDWLSDIID3) SoundWire Link SDI IDentifiers (SNDWLSDIID4) SoundWire Link Synchronization (SNDWLSYNC) SoundWire Link Extension Pointer (SNDWLEPTR) IOSF Status (IOSFSTS) Traffic Class Assignments (TCA) Transfer Traffic Class Configuration (TTCCFG) Codec Configuration (CDCCFG) Host PCI Configuration Control (HfPCICFGCTL) Fuse Value (FUSVAL) Set ID Value (DW0) (SETIDVAL0) Set ID Value (DW1) (SETIDVAL1) Hard Strap Value (HSTRVAL) Soft Strap Value (SSTRVAL) HD-A Hardware Initialization (DW0) (HDAHWI0) HD-A Hardware Initialization (DW1) (HDAHWI1) Host PCI Configuration Hardware Initialization (DW 0) (HfPCICFGHWI0) Host PCI Configuration Hardware Initialization (DW 1) (HfPCICFGHWI1) Host PCI Configuration Soft Strap Value (DW 0) (HfPCICFGSSV0) Host PCI Configuration Soft Strap Value (DW 1) (HfPCICFGSSV1) Host PCI Configuration Hardware Initialization Select (HfPCICFGHWIS) Power Management / Clock Capability (HfPMCCAP) Power Management / Clock Control (HST) Pointer (HfPMCCHPTR) Clock Control (HfCLKCTL) Clock Status (HfCLKSTS) Power Control (HfPWRCTL) Power Status (HfPWRSTS) Power Control 2 (HfPWRCTL2) Power Status 2 (HfPWRSTS2) D0i3 Control (D0I3C) Function Configuration (FNCFG) Wall Clock Counter Alias (WALCLKA) Input Stream Descriptor x Link Position in Buffer Alias (ISD0LPIBA) Input Stream Descriptor x Link Position in Buffer Alias (ISD1LPIBA) Input Stream Descriptor x Link Position in Buffer Alias (ISD2LPIBA) Input Stream Descriptor x Link Position in Buffer Alias (ISD3LPIBA) Input Stream Descriptor x Link Position in Buffer Alias (ISD4LPIBA) Input Stream Descriptor x Link Position in Buffer Alias (ISD5LPIBA) Input Stream Descriptor x Link Position in Buffer Alias (ISD6LPIBA) Input Stream Descriptor x Link Position in Buffer Alias (ISD7LPIBA) Input Stream Descriptor x Link Position in Buffer Alias (ISD8LPIBA) Input Stream Descriptor x Link Position in Buffer Alias (ISD9LPIBA) Input Stream Descriptor x Link Position in Buffer Alias (ISD10LPIBA) Output Stream Descriptor x Link Position in Buffer Alias (OSD0LPIBA) Output Stream Descriptor x Link Position in Buffer Alias (OSD1LPIBA) Output Stream Descriptor x Link Position in Buffer Alias (OSD2LPIBA) Output Stream Descriptor x Link Position in Buffer Alias (OSD3LPIBA) Output Stream Descriptor x Link Position in Buffer Alias (OSD4LPIBA) Output Stream Descriptor x Link Position in Buffer Alias (OSD5LPIBA) Output Stream Descriptor x Link Position in Buffer Alias (OSD6LPIBA) Output Stream Descriptor x Link Position in Buffer Alias (OSD7LPIBA) Output Stream Descriptor x Link Position in Buffer Alias (OSD8LPIBA) USB Audio Offload Link x PCM Stream Capabilities (UAOL0PCMSCAP) USB Audio Offload Link x PCM Stream y Channel Count (UAOL0PCMS0CHC) USB Audio Offload Link x PCM Stream y Channel Map (UAOL0PCMS0CM) USB Audio Offload Link x PCM Stream y Channel Count (UAOL0PCMS1CHC) USB Audio Offload Link x PCM Stream y Channel Map (UAOL0PCMS1CM) USB Audio Offload Link x PCM Stream y Channel Count (UAOL0PCMS2CHC) USB Audio Offload Link x PCM Stream y Channel Map (UAOL0PCMS2CM) USB Audio Offload Link x PCM Stream y Channel Count (UAOL0PCMS3CHC) USB Audio Offload Link x PCM Stream y Channel Map (UAOL0PCMS3CM) USB Audio Offload Link x PCM Stream y Channel Count (UAOL0PCMS4CHC) USB Audio Offload Link x PCM Stream y Channel Map (UAOL0PCMS4CM) USB Audio Offload Link x PCM Stream y Channel Count (UAOL0PCMS5CHC) USB Audio Offload Link x PCM Stream y Channel Map (UAOL0PCMS5CM) USB Audio Offload Link x Target Bus / Device / Function (UAOL0TBDF) USB Audio Offload Link x Output Payload Capability (UAOL0OPC) USB Audio Offload Link x Input Payload Capability (UAOL0IPC) USB Audio Offload Link x Frame Counter (UAOL0FC) USB Audio Offload Link x Frame Adjustment (UAOL0FA) USB Audio Offload Link x Immediate Command (UAOL0IC) USB Audio Offload Link x Immediate Response (UAOL0IR) USB Audio Offload Link x Immediate Command Payload y (UAOL0ICP0) USB Audio Offload Link x Immediate Command Payload y (UAOL0ICP1) USB Audio Offload Link x Immediate Command Payload y (UAOL0ICP2) USB Audio Offload Link x Immediate Command Payload y (UAOL0ICP3) USB Audio Offload Link x Immediate Response Payload y (UAOL0IRP0) USB Audio Offload Link x Immediate Response Payload y (UAOL0IRP1) USB Audio Offload Link x Immediate Response Payload y (UAOL0IRP2) USB Audio Offload Link x Immediate Response Payload y (UAOL0IRP3) USB Audio Offload Link x PCM Stream y Format (UAOL0PCMS0CTL) USB Audio Offload Link x PCM Stream y Status (UAOL0PCMS0STS) USB Audio Offload Link x PCM Stream y Fractional Rate Adjustment (UAOL0PCMS0RA) USB Audio Offload Link x PCM Stream y FIFO Address (UAOL0PCMS0FSA) USB Audio Offload Link x PCM Stream y Format (UAOL0PCMS1CTL) USB Audio Offload Link x PCM Stream y Status (UAOL0PCMS1STS) USB Audio Offload Link x PCM Stream y Fractional Rate Adjustment (UAOL0PCMS1RA) USB Audio Offload Link x PCM Stream y FIFO Address (UAOL0PCMS1FSA) USB Audio Offload Link x PCM Stream y Format (UAOL0PCMS2CTL) USB Audio Offload Link x PCM Stream y Status (UAOL0PCMS2STS) USB Audio Offload Link x PCM Stream y Fractional Rate Adjustment (UAOL0PCMS2RA) USB Audio Offload Link x PCM Stream y FIFO Address (UAOL0PCMS2FSA) USB Audio Offload Link x PCM Stream y Format (UAOL0PCMS3CTL) USB Audio Offload Link x PCM Stream y Status (UAOL0PCMS3STS) USB Audio Offload Link x PCM Stream y Fractional Rate Adjustment (UAOL0PCMS3RA) USB Audio Offload Link x PCM Stream y FIFO Address (UAOL0PCMS3FSA) USB Audio Offload Link x PCM Stream y Format (UAOL0PCMS4CTL) USB Audio Offload Link x PCM Stream y Status (UAOL0PCMS4STS) USB Audio Offload Link x PCM Stream y Fractional Rate Adjustment (UAOL0PCMS4RA) USB Audio Offload Link x PCM Stream y FIFO Address (UAOL0PCMS4FSA) USB Audio Offload Link x PCM Stream y Format (UAOL0PCMS5CTL) USB Audio Offload Link x PCM Stream y Status (UAOL0PCMS5STS) USB Audio Offload Link x PCM Stream y Fractional Rate Adjustment (UAOL0PCMS5RA) USB Audio Offload Link x PCM Stream y FIFO Address (UAOL0PCMS5FSA) USB Audio Offload Link x Vendor Specific Control (UAOL0VSCTL) Digital Microphone x PCM Stream Capabilities (DMIC0PCMSCAP) Digital Microphone PCM Stream y Channel Count (DMIC0PCMS0CHC) Digital Microphone x PCM Stream y Channel Map (DMIC0PCMS0CM) Digital Microphone PCM Stream y Channel Count (DMIC0PCMS1CHC) Digital Microphone x PCM Stream y Channel Map (DMIC0PCMS1CM) Microphone HiQ Output Control and Status Register (OUTCONTROL0) Microphone HiQ Channel Status Register (OUTSTATUS0) Microphone Data Readout and Test Registers (OUTDATA0) Microphone HiQ Output Control and Status Register (OUTCONTROL1) Microphone HiQ Channel Status Register (OUTSTATUS1) Microphone Data Readout and Test Registers (OUTDATA1) CIC Filter Control Register (PDMCTRL0_CIC_CONTROL) CIC Filter Configuration Register (PDMCTRL0_CIC_CONFIG) Microphone Control Register (PDMCTRL0_MIC_CONTROL) FIR Filter Control Register (PDMCTRL0_FIR_CONTROL_A) FIR Filter Configuration Register (PDMCTRL0_FIR_CONFIG_A) DC Offset Control Register, left channel (PDMCTRL0_DC_OFFSET_LEFT_A) DC Offset Control Register, right channel (PDMCTRL0_DC_OFFSET_RIGHT_A) Output Gain Control Register, left channel (PDMCTRL0_OUT_GAIN_LEFT_A) Output Gain Control Register, right channel (PDMCTRL0_OUT_GAIN_RIGHT_A) FIR Filter Control Register (PDMCTRL0_FIR_CONTROL_B) FIR Filter Configuration Register (PDMCTRL0_FIR_CONFIG_B) DC Offset Control Register, left channel (PDMCTRL0_DC_OFFSET_LEFT_B) DC Offset Control Register, right channel (PDMCTRL0_DC_OFFSET_RIGHT_B) Output Gain Control Register, left channel (PDMCTRL0_OUT_GAIN_LEFT_B) Output Gain Control Register, right channel (PDMCTRL0_OUT_GAIN_RIGHT_B) CIC Filter Control Register (PDMCTRL1_CIC_CONTROL) CIC Filter Configuration Register (PDMCTRL1_CIC_CONFIG) Microphone Control Register (PDMCTRL1_MIC_CONTROL) FIR Filter Control Register (PDMCTRL1_FIR_CONTROL_A) FIR Filter Configuration Register (PDMCTRL1_FIR_CONFIG_A) DC Offset Control Register, left channel (PDMCTRL1_DC_OFFSET_LEFT_A) DC Offset Control Register, right channel (PDMCTRL1_DC_OFFSET_RIGHT_A) Output Gain Control Register, left channel (PDMCTRL1_OUT_GAIN_LEFT_A) Output Gain Control Register, right channel (PDMCTRL1_OUT_GAIN_RIGHT_A) FIR Filter Control Register (PDMCTRL1_FIR_CONTROL_B) FIR Filter Configuration Register (PDMCTRL1_FIR_CONFIG_B) DC Offset Control Register, left channel (PDMCTRL1_DC_OFFSET_LEFT_B) DC Offset Control Register, right channel (PDMCTRL1_DC_OFFSET_RIGHT_B) Output Gain Control Register, left channel (PDMCTRL1_OUT_GAIN_LEFT_B) Output Gain Control Register, right channel (PDMCTRL1_OUT_GAIN_RIGHT_B) Digital Microphone x Link Vendor Specific Control (DMIC0LVSCTL) Digital Microphone x Privacy Control & Status (DMIC0PVCCS) I2S x PCM Stream Capabilities (I2S0PCMSCAP) I2S x PCM Stream y Channel Count (I2S0PCMS0CHC) I2S x PCM Stream y Channel Map (I2S0PCMS0CM) I2S x PCM Stream y Channel Count (I2S0PCMS1CHC) I2S x PCM Stream y Channel Map (I2S0PCMS1CM) I2S x PCM Stream y Channel Count (I2S0PCMS2CHC) I2S x PCM Stream y Channel Map (I2S0PCMS2CM) I2S x PCM Stream y Channel Count (I2S0PCMS3CHC) I2S x PCM Stream y Channel Map (I2S0PCMS3CM) I2S x PCM Stream y Channel Count (I2S0PCMS4CHC) I2S x PCM Stream y Channel Map (I2S0PCMS4CM) I2S x PCM Stream y Channel Count (I2S0PCMS5CHC) I2S x PCM Stream y Channel Map (I2S0PCMS5CM) I2S x PCM Stream y Channel Count (I2S0PCMS6CHC) I2S x PCM Stream y Channel Map (I2S0PCMS6CM) I2S x PCM Stream y Channel Count (I2S0PCMS7CHC) I2S x PCM Stream y Channel Map (I2S0PCMS7CM) I2S x PCM Stream y Channel Count (I2S0PCMS8CHC) I2S x PCM Stream y Channel Map (I2S0PCMS8CM) I2S x PCM Stream y Channel Count (I2S0PCMS9CHC) I2S x PCM Stream y Channel Map (I2S0PCMS9CM) I2S x PCM Stream y Channel Count (I2S0PCMS10CHC) I2S x PCM Stream y Channel Map (I2S0PCMS10CM) I2S x PCM Stream y Channel Count (I2S0PCMS11CHC) I2S x PCM Stream y Channel Map (I2S0PCMS11CM) I2S x PCM Stream y Channel Count (I2S0PCMS12CHC) I2S x PCM Stream y Channel Map (I2S0PCMS12CM) I2S x PCM Stream y Channel Count (I2S0PCMS13CHC) I2S x PCM Stream y Channel Map (I2S0PCMS13CM) I2S x PCM Stream y Channel Count (I2S0PCMS14CHC) I2S x PCM Stream y Channel Map (I2S0PCMS14CM) I2S x PCM Stream y Channel Count (I2S0PCMS15CHC) I2S x PCM Stream y Channel Map (I2S0PCMS15CM) SSP x Control 0 (I2S0_SSC0) SSP x Control 1 (I2S0_SSC1) SSP x Status (I2S0_SSS) SSP x Time Out (I2S0_SSTO) SSP x Programmable Serial Protocol (I2S0_SSPSP) SSP x Time Slot Status (I2S0_SSTSS) SSP x Command / Status 2 (I2S0_SSC2) SSP x Programmable Serial Protocol 2 (I2S0_SSPSP2) SSP x Reserved 2 (I2S0_SSRSVD2) SSP x IO Control (I2S0_SSIOC) SSP x Global Frame Synchronization (I2S0_SSGFS) SSP x Multi Input DMA y Control / Status (I2S0_SSMID0CS) SSP x Multi Input DMA y Data (I2S0_SSMID0D) SSP x Multi Input DMA y Time Slot Active (I2S0_SSMID0TSA) SSP x Multi Input DMA y Control / Status (I2S0_SSMID1CS) SSP x Multi Input DMA y Data (I2S0_SSMID1D) SSP x Multi Input DMA y Time Slot Active (I2S0_SSMID1TSA) SSP x Multi Input DMA y Control / Status (I2S0_SSMID2CS) SSP x Multi Input DMA y Data (I2S0_SSMID2D) SSP x Multi Input DMA y Time Slot Active (I2S0_SSMID2TSA) SSP x Multi Input DMA y Control / Status (I2S0_SSMID3CS) SSP x Multi Input DMA y Data (I2S0_SSMID3D) SSP x Multi Input DMA y Time Slot Active (I2S0_SSMID3TSA) SSP x Multi Input DMA y Control / Status (I2S0_SSMID4CS) SSP x Multi Input DMA y Data (I2S0_SSMID4D) SSP x Multi Input DMA y Time Slot Active (I2S0_SSMID4TSA) SSP x Multi Input DMA y Control / Status (I2S0_SSMID5CS) SSP x Multi Input DMA y Data (I2S0_SSMID5D) SSP x Multi Input DMA y Time Slot Active (I2S0_SSMID5TSA) SSP x Multi Input DMA y Control / Status (I2S0_SSMID6CS) SSP x Multi Input DMA y Data (I2S0_SSMID6D) SSP x Multi Input DMA y Time Slot Active (I2S0_SSMID6TSA) SSP x Multi Input DMA y Control / Status (I2S0_SSMID7CS) SSP x Multi Input DMA y Data (I2S0_SSMID7D) SSP x Multi Input DMA y Time Slot Active (I2S0_SSMID7TSA) SSP x Multi Output DMA y Control / Status (I2S0_SSMOD0CS) SSP x Multi Output DMA y Data (I2S0_SSMOD0D) SSP x Multi Output DMA y Time Slot Active (I2S0_SSMOD0TSA) SSP x Multi Output DMA y Control / Status (I2S0_SSMOD1CS) SSP x Multi Output DMA y Data (I2S0_SSMOD1D) SSP x Multi Output DMA y Time Slot Active (I2S0_SSMOD1TSA) SSP x Multi Output DMA y Control / Status (I2S0_SSMOD2CS) SSP x Multi Output DMA y Data (I2S0_SSMOD2D) SSP x Multi Output DMA y Time Slot Active (I2S0_SSMOD2TSA) SSP x Multi Output DMA y Control / Status (I2S0_SSMOD3CS) SSP x Multi Output DMA y Data (I2S0_SSMOD3D) SSP x Multi Output DMA y Time Slot Active (I2S0_SSMOD3TSA) SSP x Multi Output DMA y Control / Status (I2S0_SSMOD4CS) SSP x Multi Output DMA y Data (I2S0_SSMOD4D) SSP x Multi Output DMA y Time Slot Active (I2S0_SSMOD4TSA) SSP x Multi Output DMA y Control / Status (I2S0_SSMOD5CS) SSP x Multi Output DMA y Data (I2S0_SSMOD5D) SSP x Multi Output DMA y Time Slot Active (I2S0_SSMOD5TSA) SSP x Multi Output DMA y Control / Status (I2S0_SSMOD6CS) SSP x Multi Output DMA y Data (I2S0_SSMOD6D) SSP x Multi Output DMA y Time Slot Active (I2S0_SSMOD6TSA) SSP x Multi Output DMA y Control / Status (I2S0_SSMOD7CS) SSP x Multi Output DMA y Data (I2S0_SSMOD7D) SSP x Multi Output DMA y Time Slot Active (I2S0_SSMOD7TSA) I2S x Link Vendor Specific Control (I2S0LVSCTL) I2S x PCM Stream Capabilities (I2S1PCMSCAP) I2S x PCM Stream y Channel Count (I2S1PCMS0CHC) I2S x PCM Stream y Channel Map (I2S1PCMS0CM) I2S x PCM Stream y Channel Count (I2S1PCMS1CHC) I2S x PCM Stream y Channel Map (I2S1PCMS1CM) I2S x PCM Stream y Channel Count (I2S1PCMS2CHC) I2S x PCM Stream y Channel Map (I2S1PCMS2CM) I2S x PCM Stream y Channel Count (I2S1PCMS3CHC) I2S x PCM Stream y Channel Map (I2S1PCMS3CM) I2S x PCM Stream y Channel Count (I2S1PCMS4CHC) I2S x PCM Stream y Channel Map (I2S1PCMS4CM) I2S x PCM Stream y Channel Count (I2S1PCMS5CHC) I2S x PCM Stream y Channel Map (I2S1PCMS5CM) I2S x PCM Stream y Channel Count (I2S1PCMS6CHC) I2S x PCM Stream y Channel Map (I2S1PCMS6CM) I2S x PCM Stream y Channel Count (I2S1PCMS7CHC) I2S x PCM Stream y Channel Map (I2S1PCMS7CM) I2S x PCM Stream y Channel Count (I2S1PCMS8CHC) I2S x PCM Stream y Channel Map (I2S1PCMS8CM) I2S x PCM Stream y Channel Count (I2S1PCMS9CHC) I2S x PCM Stream y Channel Map (I2S1PCMS9CM) I2S x PCM Stream y Channel Count (I2S1PCMS10CHC) I2S x PCM Stream y Channel Map (I2S1PCMS10CM) I2S x PCM Stream y Channel Count (I2S1PCMS11CHC) I2S x PCM Stream y Channel Map (I2S1PCMS11CM) I2S x PCM Stream y Channel Count (I2S1PCMS12CHC) I2S x PCM Stream y Channel Map (I2S1PCMS12CM) I2S x PCM Stream y Channel Count (I2S1PCMS13CHC) I2S x PCM Stream y Channel Map (I2S1PCMS13CM) I2S x PCM Stream y Channel Count (I2S1PCMS14CHC) I2S x PCM Stream y Channel Map (I2S1PCMS14CM) I2S x PCM Stream y Channel Count (I2S1PCMS15CHC) I2S x PCM Stream y Channel Map (I2S1PCMS15CM) SSP x Control 0 (I2S1_SSC0) SSP x Control 1 (I2S1_SSC1) SSP x Status (I2S1_SSS) SSP x Time Out (I2S1_SSTO) SSP x Programmable Serial Protocol (I2S1_SSPSP) SSP x Time Slot Status (I2S1_SSTSS) SSP x Command / Status 2 (I2S1_SSC2) SSP x Programmable Serial Protocol 2 (I2S1_SSPSP2) SSP x IO Control (I2S1_SSIOC) SSP x Global Frame Synchronization (I2S1_SSGFS) SSP x Multi Input DMA y Control / Status (I2S1_SSMID0CS) SSP x Multi Input DMA y Data (I2S1_SSMID0D) SSP x Multi Input DMA y Time Slot Active (I2S1_SSMID0TSA) SSP x Multi Input DMA y Control / Status (I2S1_SSMID1CS) SSP x Multi Input DMA y Data (I2S1_SSMID1D) SSP x Multi Input DMA y Time Slot Active (I2S1_SSMID1TSA) SSP x Multi Input DMA y Control / Status (I2S1_SSMID2CS) SSP x Multi Input DMA y Data (I2S1_SSMID2D) SSP x Multi Input DMA y Time Slot Active (I2S1_SSMID2TSA) SSP x Multi Input DMA y Control / Status (I2S1_SSMID3CS) SSP x Multi Input DMA y Data (I2S1_SSMID3D) SSP x Multi Input DMA y Time Slot Active (I2S1_SSMID3TSA) SSP x Multi Input DMA y Control / Status (I2S1_SSMID4CS) SSP x Multi Input DMA y Data (I2S1_SSMID4D) SSP x Multi Input DMA y Time Slot Active (I2S1_SSMID4TSA) SSP x Multi Input DMA y Control / Status (I2S1_SSMID5CS) SSP x Multi Input DMA y Data (I2S1_SSMID5D) SSP x Multi Input DMA y Time Slot Active (I2S1_SSMID5TSA) SSP x Multi Input DMA y Control / Status (I2S1_SSMID6CS) SSP x Multi Input DMA y Data (I2S1_SSMID6D) SSP x Multi Input DMA y Time Slot Active (I2S1_SSMID6TSA) SSP x Multi Input DMA y Control / Status (I2S1_SSMID7CS) SSP x Multi Input DMA y Data (I2S1_SSMID7D) SSP x Multi Input DMA y Time Slot Active (I2S1_SSMID7TSA) SSP x Multi Output DMA y Control / Status (I2S1_SSMOD0CS) SSP x Multi Output DMA y Data (I2S1_SSMOD0D) SSP x Multi Output DMA y Time Slot Active (I2S1_SSMOD0TSA) SSP x Multi Output DMA y Control / Status (I2S1_SSMOD1CS) SSP x Multi Output DMA y Data (I2S1_SSMOD1D) SSP x Multi Output DMA y Time Slot Active (I2S1_SSMOD1TSA) SSP x Multi Output DMA y Control / Status (I2S1_SSMOD2CS) SSP x Multi Output DMA y Data (I2S1_SSMOD2D) SSP x Multi Output DMA y Time Slot Active (I2S1_SSMOD2TSA) SSP x Multi Output DMA y Control / Status (I2S1_SSMOD3CS) SSP x Multi Output DMA y Data (I2S1_SSMOD3D) SSP x Multi Output DMA y Time Slot Active (I2S1_SSMOD3TSA) SSP x Multi Output DMA y Control / Status (I2S1_SSMOD4CS) SSP x Multi Output DMA y Data (I2S1_SSMOD4D) SSP x Multi Output DMA y Time Slot Active (I2S1_SSMOD4TSA) SSP x Multi Output DMA y Control / Status (I2S1_SSMOD5CS) SSP x Multi Output DMA y Data (I2S1_SSMOD5D) SSP x Multi Output DMA y Time Slot Active (I2S1_SSMOD5TSA) SSP x Multi Output DMA y Control / Status (I2S1_SSMOD6CS) SSP x Multi Output DMA y Data (I2S1_SSMOD6D) SSP x Multi Output DMA y Time Slot Active (I2S1_SSMOD6TSA) SSP x Multi Output DMA y Control / Status (I2S1_SSMOD7CS) SSP x Multi Output DMA y Data (I2S1_SSMOD7D) SSP x Multi Output DMA y Time Slot Active (I2S1_SSMOD7TSA) I2S x Link Vendor Specific Control (I2S1LVSCTL) I2S x PCM Stream Capabilities (I2S2PCMSCAP) I2S x PCM Stream y Channel Count (I2S2PCMS0CHC) I2S x PCM Stream y Channel Map (I2S2PCMS0CM) I2S x PCM Stream y Channel Count (I2S2PCMS1CHC) I2S x PCM Stream y Channel Map (I2S2PCMS1CM) I2S x PCM Stream y Channel Count (I2S2PCMS2CHC) I2S x PCM Stream y Channel Map (I2S2PCMS2CM) I2S x PCM Stream y Channel Count (I2S2PCMS3CHC) I2S x PCM Stream y Channel Map (I2S2PCMS3CM) I2S x PCM Stream y Channel Count (I2S2PCMS4CHC) I2S x PCM Stream y Channel Map (I2S2PCMS4CM) I2S x PCM Stream y Channel Count (I2S2PCMS5CHC) I2S x PCM Stream y Channel Map (I2S2PCMS5CM) I2S x PCM Stream y Channel Count (I2S2PCMS6CHC) I2S x PCM Stream y Channel Map (I2S2PCMS6CM) I2S x PCM Stream y Channel Count (I2S2PCMS7CHC) I2S x PCM Stream y Channel Map (I2S2PCMS7CM) I2S x PCM Stream y Channel Count (I2S2PCMS8CHC) I2S x PCM Stream y Channel Map (I2S2PCMS8CM) I2S x PCM Stream y Channel Count (I2S2PCMS9CHC) I2S x PCM Stream y Channel Map (I2S2PCMS9CM) I2S x PCM Stream y Channel Count (I2S2PCMS10CHC) I2S x PCM Stream y Channel Map (I2S2PCMS10CM) I2S x PCM Stream y Channel Count (I2S2PCMS11CHC) I2S x PCM Stream y Channel Map (I2S2PCMS11CM) I2S x PCM Stream y Channel Count (I2S2PCMS12CHC) I2S x PCM Stream y Channel Map (I2S2PCMS12CM) I2S x PCM Stream y Channel Count (I2S2PCMS13CHC) I2S x PCM Stream y Channel Map (I2S2PCMS13CM) I2S x PCM Stream y Channel Count (I2S2PCMS14CHC) I2S x PCM Stream y Channel Map (I2S2PCMS14CM) I2S x PCM Stream y Channel Count (I2S2PCMS15CHC) I2S x PCM Stream y Channel Map (I2S2PCMS15CM) SSP x Control 0 (I2S2_SSC0) SSP x Control 1 (I2S2_SSC1) SSP x Status (I2S2_SSS) SSP x Time Out (I2S2_SSTO) SSP x Programmable Serial Protocol (I2S2_SSPSP) SSP x Time Slot Status (I2S2_SSTSS) SSP x Command / Status 2 (I2S2_SSC2) SSP x Programmable Serial Protocol 2 (I2S2_SSPSP2) SSP x IO Control (I2S2_SSIOC) SSP x Global Frame Synchronization (I2S2_SSGFS) SSP x Multi Input DMA y Control / Status (I2S2_SSMID0CS) SSP x Multi Input DMA y Data (I2S2_SSMID0D) SSP x Multi Input DMA y Time Slot Active (I2S2_SSMID0TSA) SSP x Multi Input DMA y Control / Status (I2S2_SSMID1CS) SSP x Multi Input DMA y Data (I2S2_SSMID1D) SSP x Multi Input DMA y Time Slot Active (I2S2_SSMID1TSA) SSP x Multi Input DMA y Control / Status (I2S2_SSMID2CS) SSP x Multi Input DMA y Data (I2S2_SSMID2D) SSP x Multi Input DMA y Time Slot Active (I2S2_SSMID2TSA) SSP x Multi Input DMA y Control / Status (I2S2_SSMID3CS) SSP x Multi Input DMA y Data (I2S2_SSMID3D) SSP x Multi Input DMA y Time Slot Active (I2S2_SSMID3TSA) SSP x Multi Input DMA y Control / Status (I2S2_SSMID4CS) SSP x Multi Input DMA y Data (I2S2_SSMID4D) SSP x Multi Input DMA y Time Slot Active (I2S2_SSMID4TSA) SSP x Multi Input DMA y Control / Status (I2S2_SSMID5CS) SSP x Multi Input DMA y Data (I2S2_SSMID5D) SSP x Multi Input DMA y Time Slot Active (I2S2_SSMID5TSA) SSP x Multi Input DMA y Control / Status (I2S2_SSMID6CS) SSP x Multi Input DMA y Data (I2S2_SSMID6D) SSP x Multi Input DMA y Time Slot Active (I2S2_SSMID6TSA) SSP x Multi Input DMA y Control / Status (I2S2_SSMID7CS) SSP x Multi Input DMA y Data (I2S2_SSMID7D) SSP x Multi Input DMA y Time Slot Active (I2S2_SSMID7TSA) SSP x Multi Output DMA y Control / Status (I2S2_SSMOD0CS) SSP x Multi Output DMA y Data (I2S2_SSMOD0D) SSP x Multi Output DMA y Time Slot Active (I2S2_SSMOD0TSA) SSP x Multi Output DMA y Control / Status (I2S2_SSMOD1CS) SSP x Multi Output DMA y Data (I2S2_SSMOD1D) SSP x Multi Output DMA y Time Slot Active (I2S2_SSMOD1TSA) SSP x Multi Output DMA y Control / Status (I2S2_SSMOD2CS) SSP x Multi Output DMA y Data (I2S2_SSMOD2D) SSP x Multi Output DMA y Time Slot Active (I2S2_SSMOD2TSA) SSP x Multi Output DMA y Control / Status (I2S2_SSMOD3CS) SSP x Multi Output DMA y Data (I2S2_SSMOD3D) SSP x Multi Output DMA y Time Slot Active (I2S2_SSMOD3TSA) SSP x Multi Output DMA y Control / Status (I2S2_SSMOD4CS) SSP x Multi Output DMA y Data (I2S2_SSMOD4D) SSP x Multi Output DMA y Time Slot Active (I2S2_SSMOD4TSA) SSP x Multi Output DMA y Control / Status (I2S2_SSMOD5CS) SSP x Multi Output DMA y Data (I2S2_SSMOD5D) SSP x Multi Output DMA y Time Slot Active (I2S2_SSMOD5TSA) SSP x Multi Output DMA y Control / Status (I2S2_SSMOD6CS) SSP x Multi Output DMA y Data (I2S2_SSMOD6D) SSP x Multi Output DMA y Time Slot Active (I2S2_SSMOD6TSA) SSP x Multi Output DMA y Control / Status (I2S2_SSMOD7CS) SSP x Multi Output DMA y Data (I2S2_SSMOD7D) SSP x Multi Output DMA y Time Slot Active (I2S2_SSMOD7TSA) I2S x Link Vendor Specific Control (I2S2LVSCTL) SoundWire x Link Extended Capability (SNDW0LECAP) SoundWire x PCM Stream Capabilities (SNDW0PCMSCAP) SoundWire PCM Stream y Channel Count (SNDW0PCMS0CHC) SoundWire x PCM Stream y Channel Map (SNDW0PCMS0CM) SoundWire PCM Stream y Channel Count (SNDW0PCMS1CHC) SoundWire x PCM Stream y Channel Map (SNDW0PCMS1CM) SoundWire PCM Stream y Channel Count (SNDW0PCMS2CHC) SoundWire x PCM Stream y Channel Map (SNDW0PCMS2CM) SoundWire PCM Stream y Channel Count (SNDW0PCMS3CHC) SoundWire x PCM Stream y Channel Map (SNDW0PCMS3CM) SoundWire PCM Stream y Channel Count (SNDW0PCMS4CHC) SoundWire x PCM Stream y Channel Map (SNDW0PCMS4CM) SoundWire PCM Stream y Channel Count (SNDW0PCMS5CHC) SoundWire x PCM Stream y Channel Map (SNDW0PCMS5CM) SoundWire PCM Stream y Channel Count (SNDW0PCMS6CHC) SoundWire x PCM Stream y Channel Map (SNDW0PCMS6CM) SoundWire PCM Stream y Channel Count (SNDW0PCMS7CHC) SoundWire x PCM Stream y Channel Map (SNDW0PCMS7CM) SoundWire PCM Stream y Channel Count (SNDW0PCMS8CHC) SoundWire x PCM Stream y Channel Map (SNDW0PCMS8CM) SoundWire PCM Stream y Channel Count (SNDW0PCMS9CHC) SoundWire x PCM Stream y Channel Map (SNDW0PCMS9CM) SoundWire PCM Stream y Channel Count (SNDW0PCMS10CHC) SoundWire x PCM Stream y Channel Map (SNDW0PCMS10CM) SoundWire PCM Stream y Channel Count (SNDW0PCMS11CHC) SoundWire x PCM Stream y Channel Map (SNDW0PCMS11CM) SoundWire PCM Stream y Channel Count (SNDW0PCMS12CHC) SoundWire x PCM Stream y Channel Map (SNDW0PCMS12CM) SoundWire PCM Stream y Channel Count (SNDW0PCMS13CHC) SoundWire x PCM Stream y Channel Map (SNDW0PCMS13CM) SoundWire PCM Stream y Channel Count (SNDW0PCMS14CHC) SoundWire x PCM Stream y Channel Map (SNDW0PCMS14CM) SoundWire PCM Stream y Channel Count (SNDW0PCMS15CHC) SoundWire x PCM Stream y Channel Map (SNDW0PCMS15CM) MCP Config (MCP_0_Config) MCP Control (MCP_0_Control) MCP SSPStat (MCP_0_SSPStat) MCP FrameShape (MCP_0_FrameShape) MCP FrameShapeInit (MCP_0_FrameShapeInit) MCP ConfigUpdate (MCP_0_ConfigUpdate) MCP SSPCtrl (MCP_0_B0_SSPCtrl) MCP SSPCtrl (MCP_0_B1_SSPCtrl) MCP ClockCtrl (MCP_0_B0_ClockCtrl) MCP ClockCtrl (MCP_0_B1_ClockCtrl) MCP Stat (MCP_0_Stat) MCP IntStat (MCP_0_IntStat) MCP IntMask (MCP_0_IntMask) MCP PeripheryStat (MCP_0_PeripheryStat) MCP PeripheryIntStat0 (MCP_0_PeripheryIntStat0) MCP PeripheryIntStat1 (MCP_0_PeripheryIntStat1) MCP PeripheryIntMask0 (MCP_0_PeripheryIntMask0) MCP PeripheryIntMask1 (MCP_0_PeripheryIntMask1) MCP PortIntStat (MCP_0_PortIntStat) MCP PDIStat (MCP_0_PDIStat) MCP FIFOLevel (MCP_0_FIFOLevel) MCP FIFOStat (MCP_0_FIFOStat) DP Config (DP_0_0_B0_Config) DP ChannelEn (DP_0_0_B0_ChannelEn) DP SampleCtrl (DP_0_0_B0_SampleCtrl) DP OffsetCtrl (DP_0_0_B0_OffsetCtrl) DP HCtrl (DP_0_0_B0_HCtrl) DP AsyncCtrl (DP_0_0_B0_AsyncCtrl) DP Config (DP_0_0_B1_Config) DP ChannelEn (DP_0_0_B1_ChannelEn) DP SampleCtrl (DP_0_0_B1_SampleCtrl) DP OffsetCtrl (DP_0_0_B1_OffsetCtrl) DP HCtrl (DP_0_0_B1_HCtrl) DP AsyncCtrl (DP_0_0_B1_AsyncCtrl) DP Port Ctrl (DP_0_0_Port_Ctrl) DP Config (DP_0_1_B0_Config) DP ChannelEn (DP_0_1_B0_ChannelEn) DP SampleCtrl (DP_0_1_B0_SampleCtrl) DP OffsetCtrl (DP_0_1_B0_OffsetCtrl) DP HCtrl (DP_0_1_B0_HCtrl) DP AsyncCtrl (DP_0_1_B0_AsyncCtrl) DP Config (DP_0_1_B1_Config) DP ChannelEn (DP_0_1_B1_ChannelEn) DP SampleCtrl (DP_0_1_B1_SampleCtrl) DP OffsetCtrl (DP_0_1_B1_OffsetCtrl) DP HCtrl (DP_0_1_B1_HCtrl) DP AsyncCtrl (DP_0_1_B1_AsyncCtrl) DP Port Ctrl (DP_0_1_Port_Ctrl) DP Config (DP_0_2_B0_Config) DP ChannelEn (DP_0_2_B0_ChannelEn) DP SampleCtrl (DP_0_2_B0_SampleCtrl) DP OffsetCtrl (DP_0_2_B0_OffsetCtrl) DP HCtrl (DP_0_2_B0_HCtrl) DP AsyncCtrl (DP_0_2_B0_AsyncCtrl) DP Config (DP_0_2_B1_Config) DP ChannelEn (DP_0_2_B1_ChannelEn) DP SampleCtrl (DP_0_2_B1_SampleCtrl) DP OffsetCtrl (DP_0_2_B1_OffsetCtrl) DP HCtrl (DP_0_2_B1_HCtrl) DP AsyncCtrl (DP_0_2_B1_AsyncCtrl) DP Port Ctrl (DP_0_2_Port_Ctrl) DP Config (DP_0_3_B0_Config) DP ChannelEn (DP_0_3_B0_ChannelEn) DP SampleCtrl (DP_0_3_B0_SampleCtrl) DP OffsetCtrl (DP_0_3_B0_OffsetCtrl) DP HCtrl (DP_0_3_B0_HCtrl) DP AsyncCtrl (DP_0_3_B0_AsyncCtrl) DP Config (DP_0_3_B1_Config) DP ChannelEn (DP_0_3_B1_ChannelEn) DP SampleCtrl (DP_0_3_B1_SampleCtrl) DP OffsetCtrl (DP_0_3_B1_OffsetCtrl) DP HCtrl (DP_0_3_B1_HCtrl) DP AsyncCtrl (DP_0_3_B1_AsyncCtrl) DP Port Ctrl (DP_0_3_Port_Ctrl) DP Config (DP_0_4_B0_Config) DP ChannelEn (DP_0_4_B0_ChannelEn) DP SampleCtrl (DP_0_4_B0_SampleCtrl) DP OffsetCtrl (DP_0_4_B0_OffsetCtrl) DP HCtrl (DP_0_4_B0_HCtrl) DP AsyncCtrl (DP_0_4_B0_AsyncCtrl) DP Config (DP_0_4_B1_Config) DP ChannelEn (DP_0_4_B1_ChannelEn) DP SampleCtrl (DP_0_4_B1_SampleCtrl) DP OffsetCtrl (DP_0_4_B1_OffsetCtrl) DP HCtrl (DP_0_4_B1_HCtrl) DP AsyncCtrl (DP_0_4_B1_AsyncCtrl) DP Port Ctrl (DP_0_4_Port_Ctrl) DP Config (DP_0_5_B0_Config) DP ChannelEn (DP_0_5_B0_ChannelEn) DP SampleCtrl (DP_0_5_B0_SampleCtrl) DP OffsetCtrl (DP_0_5_B0_OffsetCtrl) DP HCtrl (DP_0_5_B0_HCtrl) DP AsyncCtrl (DP_0_5_B0_AsyncCtrl) DP Config (DP_0_5_B1_Config) DP ChannelEn (DP_0_5_B1_ChannelEn) DP SampleCtrl (DP_0_5_B1_SampleCtrl) DP OffsetCtrl (DP_0_5_B1_OffsetCtrl) DP HCtrl (DP_0_5_B1_HCtrl) DP AsyncCtrl (DP_0_5_B1_AsyncCtrl) DP Port Ctrl (DP_0_5_Port_Ctrl) DP Config (DP_0_6_B0_Config) DP ChannelEn (DP_0_6_B0_ChannelEn) DP SampleCtrl (DP_0_6_B0_SampleCtrl) DP OffsetCtrl (DP_0_6_B0_OffsetCtrl) DP HCtrl (DP_0_6_B0_HCtrl) DP AsyncCtrl (DP_0_6_B0_AsyncCtrl) DP Config (DP_0_6_B1_Config) DP ChannelEn (DP_0_6_B1_ChannelEn) DP SampleCtrl (DP_0_6_B1_SampleCtrl) DP OffsetCtrl (DP_0_6_B1_OffsetCtrl) DP HCtrl (DP_0_6_B1_HCtrl) DP AsyncCtrl (DP_0_6_B1_AsyncCtrl) DP Port Ctrl (DP_0_6_Port_Ctrl) DP Config (DP_0_7_B0_Config) DP ChannelEn (DP_0_7_B0_ChannelEn) DP SampleCtrl (DP_0_7_B0_SampleCtrl) DP OffsetCtrl (DP_0_7_B0_OffsetCtrl) DP HCtrl (DP_0_7_B0_HCtrl) DP AsyncCtrl (DP_0_7_B0_AsyncCtrl) DP Config (DP_0_7_B1_Config) DP ChannelEn (DP_0_7_B1_ChannelEn) DP SampleCtrl (DP_0_7_B1_SampleCtrl) DP OffsetCtrl (DP_0_7_B1_OffsetCtrl) DP HCtrl (DP_0_7_B1_HCtrl) DP AsyncCtrl (DP_0_7_B1_AsyncCtrl) DP Port Ctrl (DP_0_7_Port_Ctrl) DP Config (DP_0_8_B0_Config) DP ChannelEn (DP_0_8_B0_ChannelEn) DP SampleCtrl (DP_0_8_B0_SampleCtrl) DP OffsetCtrl (DP_0_8_B0_OffsetCtrl) DP HCtrl (DP_0_8_B0_HCtrl) DP AsyncCtrl (DP_0_8_B0_AsyncCtrl) DP Config (DP_0_8_B1_Config) DP ChannelEn (DP_0_8_B1_ChannelEn) DP SampleCtrl (DP_0_8_B1_SampleCtrl) DP OffsetCtrl (DP_0_8_B1_OffsetCtrl) DP HCtrl (DP_0_8_B1_HCtrl) DP AsyncCtrl (DP_0_8_B1_AsyncCtrl) DP Port Ctrl (DP_0_8_Port_Ctrl) DP Config (DP_0_9_B0_Config) DP ChannelEn (DP_0_9_B0_ChannelEn) DP SampleCtrl (DP_0_9_B0_SampleCtrl) DP OffsetCtrl (DP_0_9_B0_OffsetCtrl) DP HCtrl (DP_0_9_B0_HCtrl) DP AsyncCtrl (DP_0_9_B0_AsyncCtrl) DP Config (DP_0_9_B1_Config) DP ChannelEn (DP_0_9_B1_ChannelEn) DP SampleCtrl (DP_0_9_B1_SampleCtrl) DP OffsetCtrl (DP_0_9_B1_OffsetCtrl) DP HCtrl (DP_0_9_B1_HCtrl) DP AsyncCtrl (DP_0_9_B1_AsyncCtrl) DP Port Ctrl (DP_0_9_Port_Ctrl) DP Config (DP_0_10_B0_Config) DP ChannelEn (DP_0_10_B0_ChannelEn) DP SampleCtrl (DP_0_10_B0_SampleCtrl) DP OffsetCtrl (DP_0_10_B0_OffsetCtrl) DP HCtrl (DP_0_10_B0_HCtrl) DP AsyncCtrl (DP_0_10_B0_AsyncCtrl) DP Config (DP_0_10_B1_Config) DP ChannelEn (DP_0_10_B1_ChannelEn) DP SampleCtrl (DP_0_10_B1_SampleCtrl) DP OffsetCtrl (DP_0_10_B1_OffsetCtrl) DP HCtrl (DP_0_10_B1_HCtrl) DP AsyncCtrl (DP_0_10_B1_AsyncCtrl) DP Port Ctrl (DP_0_10_Port_Ctrl) DP Config (DP_0_11_B0_Config) DP ChannelEn (DP_0_11_B0_ChannelEn) DP SampleCtrl (DP_0_11_B0_SampleCtrl) DP OffsetCtrl (DP_0_11_B0_OffsetCtrl) DP HCtrl (DP_0_11_B0_HCtrl) DP AsyncCtrl (DP_0_11_B0_AsyncCtrl) DP Config (DP_0_11_B1_Config) DP ChannelEn (DP_0_11_B1_ChannelEn) DP SampleCtrl (DP_0_11_B1_SampleCtrl) DP OffsetCtrl (DP_0_11_B1_OffsetCtrl) DP HCtrl (DP_0_11_B1_HCtrl) DP AsyncCtrl (DP_0_11_B1_AsyncCtrl) DP Port Ctrl (DP_0_11_Port_Ctrl) DP Config (DP_0_12_B0_Config) DP ChannelEn (DP_0_12_B0_ChannelEn) DP SampleCtrl (DP_0_12_B0_SampleCtrl) DP OffsetCtrl (DP_0_12_B0_OffsetCtrl) DP HCtrl (DP_0_12_B0_HCtrl) DP AsyncCtrl (DP_0_12_B0_AsyncCtrl) DP Config (DP_0_12_B1_Config) DP ChannelEn (DP_0_12_B1_ChannelEn) DP SampleCtrl (DP_0_12_B1_SampleCtrl) DP OffsetCtrl (DP_0_12_B1_OffsetCtrl) DP HCtrl (DP_0_12_B1_HCtrl) DP AsyncCtrl (DP_0_12_B1_AsyncCtrl) DP Port Ctrl (DP_0_12_Port_Ctrl) DP Config (DP_0_13_B0_Config) DP ChannelEn (DP_0_13_B0_ChannelEn) DP SampleCtrl (DP_0_13_B0_SampleCtrl) DP OffsetCtrl (DP_0_13_B0_OffsetCtrl) DP HCtrl (DP_0_13_B0_HCtrl) DP AsyncCtrl (DP_0_13_B0_AsyncCtrl) DP Config (DP_0_13_B1_Config) DP ChannelEn (DP_0_13_B1_ChannelEn) DP SampleCtrl (DP_0_13_B1_SampleCtrl) DP OffsetCtrl (DP_0_13_B1_OffsetCtrl) DP HCtrl (DP_0_13_B1_HCtrl) DP AsyncCtrl (DP_0_13_B1_AsyncCtrl) DP Port Ctrl (DP_0_13_Port_Ctrl) DP Config (DP_0_14_B0_Config) DP ChannelEn (DP_0_14_B0_ChannelEn) DP SampleCtrl (DP_0_14_B0_SampleCtrl) DP OffsetCtrl (DP_0_14_B0_OffsetCtrl) DP HCtrl (DP_0_14_B0_HCtrl) DP AsyncCtrl (DP_0_14_B0_AsyncCtrl) DP Config (DP_0_14_B1_Config) DP ChannelEn (DP_0_14_B1_ChannelEn) DP SampleCtrl (DP_0_14_B1_SampleCtrl) DP OffsetCtrl (DP_0_14_B1_OffsetCtrl) DP HCtrl (DP_0_14_B1_HCtrl) DP AsyncCtrl (DP_0_14_B1_AsyncCtrl) DP Port Ctrl (DP_0_14_Port_Ctrl) PDI Config (PDI_0_0_Config) PDI Config (PDI_0_1_Config) PDI Config (PDI_0_2_Config) PDI Config (PDI_0_3_Config) PDI Config (PDI_0_4_Config) PDI Config (PDI_0_5_Config) PDI Config (PDI_0_6_Config) PDI Config (PDI_0_7_Config) PDI Config (PDI_0_8_Config) PDI Config (PDI_0_9_Config) PDI Config (PDI_0_10_Config) PDI Config (PDI_0_11_Config) PDI Config (PDI_0_12_Config) PDI Config (PDI_0_13_Config) PDI Config (PDI_0_14_Config) PDI Config (PDI_0_15_Config) IP MCP Config (IP_MCP_0_Config) IP MCP Control (IP_MCP_0_Control) IP MCP CmdCtrl (IP_MCP_0_CmdCtrl) IP MCP PHYCtrl (IP_MCP_0_PHYCtrl) IP MCP B0_ClockCtrl (IP_MCP_0_B0_ClockCtrl) IP MCP Stat (IP_MCP_0_Stat) IP MCP IntSet (IP_MCP_0_IntSet) IP MCP Command (IP_MCP_0_Command) SoundWire x Link Vendor Specific Control (SNDW0LVSCTL) SoundWire x Wake Enable (SNDW0WAKEEN) SoundWire x Wake Status (SNDW0WAKESTS) SoundWire x I/O Control (SNDW0IOCTL) SoundWire x AC Timing Control (SNDW0ACTMCTL) SoundWire x Microphone Privacy Control & Status (SNDW0PVCCS) SoundWire x Link Extended Capability (SNDW1LECAP) SoundWire x PCM Stream Capabilities (SNDW1PCMSCAP) SoundWire PCM Stream y Channel Count (SNDW1PCMS0CHC) SoundWire x PCM Stream y Channel Map (SNDW1PCMS0CM) SoundWire PCM Stream y Channel Count (SNDW1PCMS1CHC) SoundWire x PCM Stream y Channel Map (SNDW1PCMS1CM) SoundWire PCM Stream y Channel Count (SNDW1PCMS2CHC) SoundWire x PCM Stream y Channel Map (SNDW1PCMS2CM) SoundWire PCM Stream y Channel Count (SNDW1PCMS3CHC) SoundWire x PCM Stream y Channel Map (SNDW1PCMS3CM) SoundWire PCM Stream y Channel Count (SNDW1PCMS4CHC) SoundWire x PCM Stream y Channel Map (SNDW1PCMS4CM) SoundWire PCM Stream y Channel Count (SNDW1PCMS5CHC) SoundWire x PCM Stream y Channel Map (SNDW1PCMS5CM) SoundWire PCM Stream y Channel Count (SNDW1PCMS6CHC) SoundWire x PCM Stream y Channel Map (SNDW1PCMS6CM) SoundWire PCM Stream y Channel Count (SNDW1PCMS7CHC) SoundWire x PCM Stream y Channel Map (SNDW1PCMS7CM) SoundWire PCM Stream y Channel Count (SNDW1PCMS8CHC) SoundWire x PCM Stream y Channel Map (SNDW1PCMS8CM) SoundWire PCM Stream y Channel Count (SNDW1PCMS9CHC) SoundWire x PCM Stream y Channel Map (SNDW1PCMS9CM) SoundWire PCM Stream y Channel Count (SNDW1PCMS10CHC) SoundWire x PCM Stream y Channel Map (SNDW1PCMS10CM) SoundWire PCM Stream y Channel Count (SNDW1PCMS11CHC) SoundWire x PCM Stream y Channel Map (SNDW1PCMS11CM) SoundWire PCM Stream y Channel Count (SNDW1PCMS12CHC) SoundWire x PCM Stream y Channel Map (SNDW1PCMS12CM) SoundWire PCM Stream y Channel Count (SNDW1PCMS13CHC) SoundWire x PCM Stream y Channel Map (SNDW1PCMS13CM) SoundWire PCM Stream y Channel Count (SNDW1PCMS14CHC) SoundWire x PCM Stream y Channel Map (SNDW1PCMS14CM) SoundWire PCM Stream y Channel Count (SNDW1PCMS15CHC) SoundWire x PCM Stream y Channel Map (SNDW1PCMS15CM) MCP Config (MCP_1_Config) MCP Control (MCP_1_Control) MCP SSPStat (MCP_1_SSPStat) MCP FrameShape (MCP_1_FrameShape) MCP FrameShapeInit (MCP_1_FrameShapeInit) MCP ConfigUpdate (MCP_1_ConfigUpdate) MCP SSPCtrl (MCP_1_B0_SSPCtrl) MCP SSPCtrl (MCP_1_B1_SSPCtrl) MCP ClockCtrl (MCP_1_B0_ClockCtrl) MCP ClockCtrl (MCP_1_B1_ClockCtrl) MCP Stat (MCP_1_Stat) MCP IntStat (MCP_1_IntStat) MCP IntMask (MCP_1_IntMask) MCP PeripheryStat (MCP_1_PeripheryStat) MCP PeripheryIntStat0 (MCP_1_PeripheryIntStat0) MCP PeripheryIntStat1 (MCP_1_PeripheryIntStat1) MCP PeripheryIntMask0 (MCP_1_PeripheryIntMask0) MCP PeripheryIntMask1 (MCP_1_PeripheryIntMask1) MCP PortIntStat (MCP_1_PortIntStat) MCP PDIStat (MCP_1_PDIStat) MCP FIFOLevel (MCP_1_FIFOLevel) MCP FIFOStat (MCP_1_FIFOStat) DP Config (DP_1_0_B0_Config) DP ChannelEn (DP_1_0_B0_ChannelEn) DP SampleCtrl (DP_1_0_B0_SampleCtrl) DP OffsetCtrl (DP_1_0_B0_OffsetCtrl) DP HCtrl (DP_1_0_B0_HCtrl) DP AsyncCtrl (DP_1_0_B0_AsyncCtrl) DP Config (DP_1_0_B1_Config) DP ChannelEn (DP_1_0_B1_ChannelEn) DP SampleCtrl (DP_1_0_B1_SampleCtrl) DP OffsetCtrl (DP_1_0_B1_OffsetCtrl) DP HCtrl (DP_1_0_B1_HCtrl) DP AsyncCtrl (DP_1_0_B1_AsyncCtrl) DP Port Ctrl (DP_1_0_Port_Ctrl) DP Config (DP_1_1_B0_Config) DP ChannelEn (DP_1_1_B0_ChannelEn) DP SampleCtrl (DP_1_1_B0_SampleCtrl) DP OffsetCtrl (DP_1_1_B0_OffsetCtrl) DP HCtrl (DP_1_1_B0_HCtrl) DP AsyncCtrl (DP_1_1_B0_AsyncCtrl) DP Config (DP_1_1_B1_Config) DP ChannelEn (DP_1_1_B1_ChannelEn) DP SampleCtrl (DP_1_1_B1_SampleCtrl) DP OffsetCtrl (DP_1_1_B1_OffsetCtrl) DP HCtrl (DP_1_1_B1_HCtrl) DP AsyncCtrl (DP_1_1_B1_AsyncCtrl) DP Port Ctrl (DP_1_1_Port_Ctrl) DP Config (DP_1_2_B0_Config) DP ChannelEn (DP_1_2_B0_ChannelEn) DP SampleCtrl (DP_1_2_B0_SampleCtrl) DP OffsetCtrl (DP_1_2_B0_OffsetCtrl) DP HCtrl (DP_1_2_B0_HCtrl) DP AsyncCtrl (DP_1_2_B0_AsyncCtrl) DP Config (DP_1_2_B1_Config) DP ChannelEn (DP_1_2_B1_ChannelEn) DP SampleCtrl (DP_1_2_B1_SampleCtrl) DP OffsetCtrl (DP_1_2_B1_OffsetCtrl) DP HCtrl (DP_1_2_B1_HCtrl) DP AsyncCtrl (DP_1_2_B1_AsyncCtrl) DP Port Ctrl (DP_1_2_Port_Ctrl) DP Config (DP_1_3_B0_Config) DP ChannelEn (DP_1_3_B0_ChannelEn) DP SampleCtrl (DP_1_3_B0_SampleCtrl) DP OffsetCtrl (DP_1_3_B0_OffsetCtrl) DP HCtrl (DP_1_3_B0_HCtrl) DP AsyncCtrl (DP_1_3_B0_AsyncCtrl) DP Config (DP_1_3_B1_Config) DP ChannelEn (DP_1_3_B1_ChannelEn) DP SampleCtrl (DP_1_3_B1_SampleCtrl) DP OffsetCtrl (DP_1_3_B1_OffsetCtrl) DP HCtrl (DP_1_3_B1_HCtrl) DP AsyncCtrl (DP_1_3_B1_AsyncCtrl) DP Port Ctrl (DP_1_3_Port_Ctrl) DP Config (DP_1_4_B0_Config) DP ChannelEn (DP_1_4_B0_ChannelEn) DP SampleCtrl (DP_1_4_B0_SampleCtrl) DP OffsetCtrl (DP_1_4_B0_OffsetCtrl) DP HCtrl (DP_1_4_B0_HCtrl) DP AsyncCtrl (DP_1_4_B0_AsyncCtrl) DP Config (DP_1_4_B1_Config) DP ChannelEn (DP_1_4_B1_ChannelEn) DP SampleCtrl (DP_1_4_B1_SampleCtrl) DP OffsetCtrl (DP_1_4_B1_OffsetCtrl) DP HCtrl (DP_1_4_B1_HCtrl) DP AsyncCtrl (DP_1_4_B1_AsyncCtrl) DP Port Ctrl (DP_1_4_Port_Ctrl) DP Config (DP_1_5_B0_Config) DP ChannelEn (DP_1_5_B0_ChannelEn) DP SampleCtrl (DP_1_5_B0_SampleCtrl) DP OffsetCtrl (DP_1_5_B0_OffsetCtrl) DP HCtrl (DP_1_5_B0_HCtrl) DP AsyncCtrl (DP_1_5_B0_AsyncCtrl) DP Config (DP_1_5_B1_Config) DP ChannelEn (DP_1_5_B1_ChannelEn) DP SampleCtrl (DP_1_5_B1_SampleCtrl) DP OffsetCtrl (DP_1_5_B1_OffsetCtrl) DP HCtrl (DP_1_5_B1_HCtrl) DP AsyncCtrl (DP_1_5_B1_AsyncCtrl) DP Port Ctrl (DP_1_5_Port_Ctrl) DP Config (DP_1_6_B0_Config) DP ChannelEn (DP_1_6_B0_ChannelEn) DP SampleCtrl (DP_1_6_B0_SampleCtrl) DP OffsetCtrl (DP_1_6_B0_OffsetCtrl) DP HCtrl (DP_1_6_B0_HCtrl) DP AsyncCtrl (DP_1_6_B0_AsyncCtrl) DP Config (DP_1_6_B1_Config) DP ChannelEn (DP_1_6_B1_ChannelEn) DP SampleCtrl (DP_1_6_B1_SampleCtrl) DP OffsetCtrl (DP_1_6_B1_OffsetCtrl) DP HCtrl (DP_1_6_B1_HCtrl) DP AsyncCtrl (DP_1_6_B1_AsyncCtrl) DP Port Ctrl (DP_1_6_Port_Ctrl) DP Config (DP_1_7_B0_Config) DP ChannelEn (DP_1_7_B0_ChannelEn) DP SampleCtrl (DP_1_7_B0_SampleCtrl) DP OffsetCtrl (DP_1_7_B0_OffsetCtrl) DP HCtrl (DP_1_7_B0_HCtrl) DP AsyncCtrl (DP_1_7_B0_AsyncCtrl) DP Config (DP_1_7_B1_Config) DP ChannelEn (DP_1_7_B1_ChannelEn) DP SampleCtrl (DP_1_7_B1_SampleCtrl) DP OffsetCtrl (DP_1_7_B1_OffsetCtrl) DP HCtrl (DP_1_7_B1_HCtrl) DP AsyncCtrl (DP_1_7_B1_AsyncCtrl) DP Port Ctrl (DP_1_7_Port_Ctrl) DP Config (DP_1_8_B0_Config) DP ChannelEn (DP_1_8_B0_ChannelEn) DP SampleCtrl (DP_1_8_B0_SampleCtrl) DP OffsetCtrl (DP_1_8_B0_OffsetCtrl) DP HCtrl (DP_1_8_B0_HCtrl) DP AsyncCtrl (DP_1_8_B0_AsyncCtrl) DP Config (DP_1_8_B1_Config) DP ChannelEn (DP_1_8_B1_ChannelEn) DP SampleCtrl (DP_1_8_B1_SampleCtrl) DP OffsetCtrl (DP_1_8_B1_OffsetCtrl) DP HCtrl (DP_1_8_B1_HCtrl) DP AsyncCtrl (DP_1_8_B1_AsyncCtrl) DP Port Ctrl (DP_1_8_Port_Ctrl) DP Config (DP_1_9_B0_Config) DP ChannelEn (DP_1_9_B0_ChannelEn) DP SampleCtrl (DP_1_9_B0_SampleCtrl) DP OffsetCtrl (DP_1_9_B0_OffsetCtrl) DP HCtrl (DP_1_9_B0_HCtrl) DP AsyncCtrl (DP_1_9_B0_AsyncCtrl) DP Config (DP_1_9_B1_Config) DP ChannelEn (DP_1_9_B1_ChannelEn) DP SampleCtrl (DP_1_9_B1_SampleCtrl) DP OffsetCtrl (DP_1_9_B1_OffsetCtrl) DP HCtrl (DP_1_9_B1_HCtrl) DP AsyncCtrl (DP_1_9_B1_AsyncCtrl) DP Port Ctrl (DP_1_9_Port_Ctrl) DP Config (DP_1_10_B0_Config) DP ChannelEn (DP_1_10_B0_ChannelEn) DP SampleCtrl (DP_1_10_B0_SampleCtrl) DP OffsetCtrl (DP_1_10_B0_OffsetCtrl) DP HCtrl (DP_1_10_B0_HCtrl) DP AsyncCtrl (DP_1_10_B0_AsyncCtrl) DP Config (DP_1_10_B1_Config) DP ChannelEn (DP_1_10_B1_ChannelEn) DP SampleCtrl (DP_1_10_B1_SampleCtrl) DP OffsetCtrl (DP_1_10_B1_OffsetCtrl) DP HCtrl (DP_1_10_B1_HCtrl) DP AsyncCtrl (DP_1_10_B1_AsyncCtrl) DP Port Ctrl (DP_1_10_Port_Ctrl) DP Config (DP_1_11_B0_Config) DP ChannelEn (DP_1_11_B0_ChannelEn) DP SampleCtrl (DP_1_11_B0_SampleCtrl) DP OffsetCtrl (DP_1_11_B0_OffsetCtrl) DP HCtrl (DP_1_11_B0_HCtrl) DP AsyncCtrl (DP_1_11_B0_AsyncCtrl) DP Config (DP_1_11_B1_Config) DP ChannelEn (DP_1_11_B1_ChannelEn) DP SampleCtrl (DP_1_11_B1_SampleCtrl) DP OffsetCtrl (DP_1_11_B1_OffsetCtrl) DP HCtrl (DP_1_11_B1_HCtrl) DP AsyncCtrl (DP_1_11_B1_AsyncCtrl) DP Port Ctrl (DP_1_11_Port_Ctrl) DP Config (DP_1_12_B0_Config) DP ChannelEn (DP_1_12_B0_ChannelEn) DP SampleCtrl (DP_1_12_B0_SampleCtrl) DP OffsetCtrl (DP_1_12_B0_OffsetCtrl) DP HCtrl (DP_1_12_B0_HCtrl) DP AsyncCtrl (DP_1_12_B0_AsyncCtrl) DP Config (DP_1_12_B1_Config) DP ChannelEn (DP_1_12_B1_ChannelEn) DP SampleCtrl (DP_1_12_B1_SampleCtrl) DP OffsetCtrl (DP_1_12_B1_OffsetCtrl) DP HCtrl (DP_1_12_B1_HCtrl) DP AsyncCtrl (DP_1_12_B1_AsyncCtrl) DP Port Ctrl (DP_1_12_Port_Ctrl) DP Config (DP_1_13_B0_Config) DP ChannelEn (DP_1_13_B0_ChannelEn) DP SampleCtrl (DP_1_13_B0_SampleCtrl) DP OffsetCtrl (DP_1_13_B0_OffsetCtrl) DP HCtrl (DP_1_13_B0_HCtrl) DP AsyncCtrl (DP_1_13_B0_AsyncCtrl) DP Config (DP_1_13_B1_Config) DP ChannelEn (DP_1_13_B1_ChannelEn) DP SampleCtrl (DP_1_13_B1_SampleCtrl) DP OffsetCtrl (DP_1_13_B1_OffsetCtrl) DP HCtrl (DP_1_13_B1_HCtrl) DP AsyncCtrl (DP_1_13_B1_AsyncCtrl) DP Port Ctrl (DP_1_13_Port_Ctrl) DP Config (DP_1_14_B0_Config) DP ChannelEn (DP_1_14_B0_ChannelEn) DP SampleCtrl (DP_1_14_B0_SampleCtrl) DP OffsetCtrl (DP_1_14_B0_OffsetCtrl) DP HCtrl (DP_1_14_B0_HCtrl) DP AsyncCtrl (DP_1_14_B0_AsyncCtrl) DP Config (DP_1_14_B1_Config) DP ChannelEn (DP_1_14_B1_ChannelEn) DP SampleCtrl (DP_1_14_B1_SampleCtrl) DP OffsetCtrl (DP_1_14_B1_OffsetCtrl) DP HCtrl (DP_1_14_B1_HCtrl) DP AsyncCtrl (DP_1_14_B1_AsyncCtrl) DP Port Ctrl (DP_1_14_Port_Ctrl) PDI Config (PDI_1_0_Config) PDI Config (PDI_1_1_Config) PDI Config (PDI_1_2_Config) PDI Config (PDI_1_3_Config) PDI Config (PDI_1_4_Config) PDI Config (PDI_1_5_Config) PDI Config (PDI_1_6_Config) PDI Config (PDI_1_7_Config) PDI Config (PDI_1_8_Config) PDI Config (PDI_1_9_Config) PDI Config (PDI_1_10_Config) PDI Config (PDI_1_11_Config) PDI Config (PDI_1_12_Config) PDI Config (PDI_1_13_Config) PDI Config (PDI_1_14_Config) PDI Config (PDI_1_15_Config) IP MCP Config (IP_MCP_1_Config) IP MCP Control (IP_MCP_1_Control) IP MCP CmdCtrl (IP_MCP_1_CmdCtrl) IP MCP PHYCtrl (IP_MCP_1_PHYCtrl) IP MCP B0_ClockCtrl (IP_MCP_1_B0_ClockCtrl) IP MCP Stat (IP_MCP_1_Stat) IP MCP IntSet (IP_MCP_1_IntSet) IP MCP Command (IP_MCP_1_Command) SoundWire x Link Vendor Specific Control (SNDW1LVSCTL) SoundWire x Wake Enable (SNDW1WAKEEN) SoundWire x Wake Status (SNDW1WAKESTS) SoundWire x I/O Control (SNDW1IOCTL) SoundWire x AC Timing Control (SNDW1ACTMCTL) SoundWire x Microphone Privacy Control & Status (SNDW1PVCCS) SoundWire x Link Extended Capability (SNDW2LECAP) SoundWire x PCM Stream Capabilities (SNDW2PCMSCAP) SoundWire PCM Stream y Channel Count (SNDW2PCMS0CHC) SoundWire x PCM Stream y Channel Map (SNDW2PCMS0CM) SoundWire PCM Stream y Channel Count (SNDW2PCMS1CHC) SoundWire x PCM Stream y Channel Map (SNDW2PCMS1CM) SoundWire PCM Stream y Channel Count (SNDW2PCMS2CHC) SoundWire x PCM Stream y Channel Map (SNDW2PCMS2CM) SoundWire PCM Stream y Channel Count (SNDW2PCMS3CHC) SoundWire x PCM Stream y Channel Map (SNDW2PCMS3CM) SoundWire PCM Stream y Channel Count (SNDW2PCMS4CHC) SoundWire x PCM Stream y Channel Map (SNDW2PCMS4CM) SoundWire PCM Stream y Channel Count (SNDW2PCMS5CHC) SoundWire x PCM Stream y Channel Map (SNDW2PCMS5CM) SoundWire PCM Stream y Channel Count (SNDW2PCMS6CHC) SoundWire x PCM Stream y Channel Map (SNDW2PCMS6CM) SoundWire PCM Stream y Channel Count (SNDW2PCMS7CHC) SoundWire x PCM Stream y Channel Map (SNDW2PCMS7CM) SoundWire PCM Stream y Channel Count (SNDW2PCMS8CHC) SoundWire x PCM Stream y Channel Map (SNDW2PCMS8CM) SoundWire PCM Stream y Channel Count (SNDW2PCMS9CHC) SoundWire x PCM Stream y Channel Map (SNDW2PCMS9CM) SoundWire PCM Stream y Channel Count (SNDW2PCMS10CHC) SoundWire x PCM Stream y Channel Map (SNDW2PCMS10CM) SoundWire PCM Stream y Channel Count (SNDW2PCMS11CHC) SoundWire x PCM Stream y Channel Map (SNDW2PCMS11CM) SoundWire PCM Stream y Channel Count (SNDW2PCMS12CHC) SoundWire x PCM Stream y Channel Map (SNDW2PCMS12CM) SoundWire PCM Stream y Channel Count (SNDW2PCMS13CHC) SoundWire x PCM Stream y Channel Map (SNDW2PCMS13CM) SoundWire PCM Stream y Channel Count (SNDW2PCMS14CHC) SoundWire x PCM Stream y Channel Map (SNDW2PCMS14CM) SoundWire PCM Stream y Channel Count (SNDW2PCMS15CHC) SoundWire x PCM Stream y Channel Map (SNDW2PCMS15CM) MCP Config (MCP_2_Config) MCP Control (MCP_2_Control) MCP SSPStat (MCP_2_SSPStat) MCP FrameShape (MCP_2_FrameShape) MCP FrameShapeInit (MCP_2_FrameShapeInit) MCP ConfigUpdate (MCP_2_ConfigUpdate) MCP SSPCtrl (MCP_2_B0_SSPCtrl) MCP SSPCtrl (MCP_2_B1_SSPCtrl) MCP ClockCtrl (MCP_2_B0_ClockCtrl) MCP ClockCtrl (MCP_2_B1_ClockCtrl) MCP Stat (MCP_2_Stat) MCP IntStat (MCP_2_IntStat) MCP IntMask (MCP_2_IntMask) MCP PeripheryStat (MCP_2_PeripheryStat) MCP PeripheryIntStat0 (MCP_2_PeripheryIntStat0) MCP PeripheryIntStat1 (MCP_2_PeripheryIntStat1) MCP PeripheryIntMask0 (MCP_2_PeripheryIntMask0) MCP PeripheryIntMask1 (MCP_2_PeripheryIntMask1) MCP PortIntStat (MCP_2_PortIntStat) MCP PDIStat (MCP_2_PDIStat) MCP FIFOLevel (MCP_2_FIFOLevel) MCP FIFOStat (MCP_2_FIFOStat) DP Config (DP_2_0_B0_Config) DP ChannelEn (DP_2_0_B0_ChannelEn) DP SampleCtrl (DP_2_0_B0_SampleCtrl) DP OffsetCtrl (DP_2_0_B0_OffsetCtrl) DP HCtrl (DP_2_0_B0_HCtrl) DP AsyncCtrl (DP_2_0_B0_AsyncCtrl) DP Config (DP_2_0_B1_Config) DP ChannelEn (DP_2_0_B1_ChannelEn) DP SampleCtrl (DP_2_0_B1_SampleCtrl) DP OffsetCtrl (DP_2_0_B1_OffsetCtrl) DP HCtrl (DP_2_0_B1_HCtrl) DP AsyncCtrl (DP_2_0_B1_AsyncCtrl) DP Port Ctrl (DP_2_0_Port_Ctrl) DP Config (DP_2_1_B0_Config) DP ChannelEn (DP_2_1_B0_ChannelEn) DP SampleCtrl (DP_2_1_B0_SampleCtrl) DP OffsetCtrl (DP_2_1_B0_OffsetCtrl) DP HCtrl (DP_2_1_B0_HCtrl) DP AsyncCtrl (DP_2_1_B0_AsyncCtrl) DP Config (DP_2_1_B1_Config) DP ChannelEn (DP_2_1_B1_ChannelEn) DP SampleCtrl (DP_2_1_B1_SampleCtrl) DP OffsetCtrl (DP_2_1_B1_OffsetCtrl) DP HCtrl (DP_2_1_B1_HCtrl) DP AsyncCtrl (DP_2_1_B1_AsyncCtrl) DP Port Ctrl (DP_2_1_Port_Ctrl) DP Config (DP_2_2_B0_Config) DP ChannelEn (DP_2_2_B0_ChannelEn) DP SampleCtrl (DP_2_2_B0_SampleCtrl) DP OffsetCtrl (DP_2_2_B0_OffsetCtrl) DP HCtrl (DP_2_2_B0_HCtrl) DP AsyncCtrl (DP_2_2_B0_AsyncCtrl) DP Config (DP_2_2_B1_Config) DP ChannelEn (DP_2_2_B1_ChannelEn) DP SampleCtrl (DP_2_2_B1_SampleCtrl) DP OffsetCtrl (DP_2_2_B1_OffsetCtrl) DP HCtrl (DP_2_2_B1_HCtrl) DP AsyncCtrl (DP_2_2_B1_AsyncCtrl) DP Port Ctrl (DP_2_2_Port_Ctrl) DP Config (DP_2_3_B0_Config) DP ChannelEn (DP_2_3_B0_ChannelEn) DP SampleCtrl (DP_2_3_B0_SampleCtrl) DP OffsetCtrl (DP_2_3_B0_OffsetCtrl) DP HCtrl (DP_2_3_B0_HCtrl) DP AsyncCtrl (DP_2_3_B0_AsyncCtrl) DP Config (DP_2_3_B1_Config) DP ChannelEn (DP_2_3_B1_ChannelEn) DP SampleCtrl (DP_2_3_B1_SampleCtrl) DP OffsetCtrl (DP_2_3_B1_OffsetCtrl) DP HCtrl (DP_2_3_B1_HCtrl) DP AsyncCtrl (DP_2_3_B1_AsyncCtrl) DP Port Ctrl (DP_2_3_Port_Ctrl) DP Config (DP_2_4_B0_Config) DP ChannelEn (DP_2_4_B0_ChannelEn) DP SampleCtrl (DP_2_4_B0_SampleCtrl) DP OffsetCtrl (DP_2_4_B0_OffsetCtrl) DP HCtrl (DP_2_4_B0_HCtrl) DP AsyncCtrl (DP_2_4_B0_AsyncCtrl) DP Config (DP_2_4_B1_Config) DP ChannelEn (DP_2_4_B1_ChannelEn) DP SampleCtrl (DP_2_4_B1_SampleCtrl) DP OffsetCtrl (DP_2_4_B1_OffsetCtrl) DP HCtrl (DP_2_4_B1_HCtrl) DP AsyncCtrl (DP_2_4_B1_AsyncCtrl) DP Port Ctrl (DP_2_4_Port_Ctrl) DP Config (DP_2_5_B0_Config) DP ChannelEn (DP_2_5_B0_ChannelEn) DP SampleCtrl (DP_2_5_B0_SampleCtrl) DP OffsetCtrl (DP_2_5_B0_OffsetCtrl) DP HCtrl (DP_2_5_B0_HCtrl) DP AsyncCtrl (DP_2_5_B0_AsyncCtrl) DP Config (DP_2_5_B1_Config) DP ChannelEn (DP_2_5_B1_ChannelEn) DP SampleCtrl (DP_2_5_B1_SampleCtrl) DP OffsetCtrl (DP_2_5_B1_OffsetCtrl) DP HCtrl (DP_2_5_B1_HCtrl) DP AsyncCtrl (DP_2_5_B1_AsyncCtrl) DP Port Ctrl (DP_2_5_Port_Ctrl) DP Config (DP_2_6_B0_Config) DP ChannelEn (DP_2_6_B0_ChannelEn) DP SampleCtrl (DP_2_6_B0_SampleCtrl) DP OffsetCtrl (DP_2_6_B0_OffsetCtrl) DP HCtrl (DP_2_6_B0_HCtrl) DP AsyncCtrl (DP_2_6_B0_AsyncCtrl) DP Config (DP_2_6_B1_Config) DP ChannelEn (DP_2_6_B1_ChannelEn) DP SampleCtrl (DP_2_6_B1_SampleCtrl) DP OffsetCtrl (DP_2_6_B1_OffsetCtrl) DP HCtrl (DP_2_6_B1_HCtrl) DP AsyncCtrl (DP_2_6_B1_AsyncCtrl) DP Port Ctrl (DP_2_6_Port_Ctrl) DP Config (DP_2_7_B0_Config) DP ChannelEn (DP_2_7_B0_ChannelEn) DP SampleCtrl (DP_2_7_B0_SampleCtrl) DP OffsetCtrl (DP_2_7_B0_OffsetCtrl) DP HCtrl (DP_2_7_B0_HCtrl) DP AsyncCtrl (DP_2_7_B0_AsyncCtrl) DP Config (DP_2_7_B1_Config) DP ChannelEn (DP_2_7_B1_ChannelEn) DP SampleCtrl (DP_2_7_B1_SampleCtrl) DP OffsetCtrl (DP_2_7_B1_OffsetCtrl) DP HCtrl (DP_2_7_B1_HCtrl) DP AsyncCtrl (DP_2_7_B1_AsyncCtrl) DP Port Ctrl (DP_2_7_Port_Ctrl) DP Config (DP_2_8_B0_Config) DP ChannelEn (DP_2_8_B0_ChannelEn) DP SampleCtrl (DP_2_8_B0_SampleCtrl) DP OffsetCtrl (DP_2_8_B0_OffsetCtrl) DP HCtrl (DP_2_8_B0_HCtrl) DP AsyncCtrl (DP_2_8_B0_AsyncCtrl) DP Config (DP_2_8_B1_Config) DP ChannelEn (DP_2_8_B1_ChannelEn) DP SampleCtrl (DP_2_8_B1_SampleCtrl) DP OffsetCtrl (DP_2_8_B1_OffsetCtrl) DP HCtrl (DP_2_8_B1_HCtrl) DP AsyncCtrl (DP_2_8_B1_AsyncCtrl) DP Port Ctrl (DP_2_8_Port_Ctrl) DP Config (DP_2_9_B0_Config) DP ChannelEn (DP_2_9_B0_ChannelEn) DP SampleCtrl (DP_2_9_B0_SampleCtrl) DP OffsetCtrl (DP_2_9_B0_OffsetCtrl) DP HCtrl (DP_2_9_B0_HCtrl) DP AsyncCtrl (DP_2_9_B0_AsyncCtrl) DP Config (DP_2_9_B1_Config) DP ChannelEn (DP_2_9_B1_ChannelEn) DP SampleCtrl (DP_2_9_B1_SampleCtrl) DP OffsetCtrl (DP_2_9_B1_OffsetCtrl) DP HCtrl (DP_2_9_B1_HCtrl) DP AsyncCtrl (DP_2_9_B1_AsyncCtrl) DP Port Ctrl (DP_2_9_Port_Ctrl) DP Config (DP_2_10_B0_Config) DP ChannelEn (DP_2_10_B0_ChannelEn) DP SampleCtrl (DP_2_10_B0_SampleCtrl) DP OffsetCtrl (DP_2_10_B0_OffsetCtrl) DP HCtrl (DP_2_10_B0_HCtrl) DP AsyncCtrl (DP_2_10_B0_AsyncCtrl) DP Config (DP_2_10_B1_Config) DP ChannelEn (DP_2_10_B1_ChannelEn) DP SampleCtrl (DP_2_10_B1_SampleCtrl) DP OffsetCtrl (DP_2_10_B1_OffsetCtrl) DP HCtrl (DP_2_10_B1_HCtrl) DP AsyncCtrl (DP_2_10_B1_AsyncCtrl) DP Port Ctrl (DP_2_10_Port_Ctrl) DP Config (DP_2_11_B0_Config) DP ChannelEn (DP_2_11_B0_ChannelEn) DP SampleCtrl (DP_2_11_B0_SampleCtrl) DP OffsetCtrl (DP_2_11_B0_OffsetCtrl) DP HCtrl (DP_2_11_B0_HCtrl) DP AsyncCtrl (DP_2_11_B0_AsyncCtrl) DP Config (DP_2_11_B1_Config) DP ChannelEn (DP_2_11_B1_ChannelEn) DP SampleCtrl (DP_2_11_B1_SampleCtrl) DP OffsetCtrl (DP_2_11_B1_OffsetCtrl) DP HCtrl (DP_2_11_B1_HCtrl) DP AsyncCtrl (DP_2_11_B1_AsyncCtrl) DP Port Ctrl (DP_2_11_Port_Ctrl) DP Config (DP_2_12_B0_Config) DP ChannelEn (DP_2_12_B0_ChannelEn) DP SampleCtrl (DP_2_12_B0_SampleCtrl) DP OffsetCtrl (DP_2_12_B0_OffsetCtrl) DP HCtrl (DP_2_12_B0_HCtrl) DP AsyncCtrl (DP_2_12_B0_AsyncCtrl) DP Config (DP_2_12_B1_Config) DP ChannelEn (DP_2_12_B1_ChannelEn) DP SampleCtrl (DP_2_12_B1_SampleCtrl) DP OffsetCtrl (DP_2_12_B1_OffsetCtrl) DP HCtrl (DP_2_12_B1_HCtrl) DP AsyncCtrl (DP_2_12_B1_AsyncCtrl) DP Port Ctrl (DP_2_12_Port_Ctrl) DP Config (DP_2_13_B0_Config) DP ChannelEn (DP_2_13_B0_ChannelEn) DP SampleCtrl (DP_2_13_B0_SampleCtrl) DP OffsetCtrl (DP_2_13_B0_OffsetCtrl) DP HCtrl (DP_2_13_B0_HCtrl) DP AsyncCtrl (DP_2_13_B0_AsyncCtrl) DP Config (DP_2_13_B1_Config) DP ChannelEn (DP_2_13_B1_ChannelEn) DP SampleCtrl (DP_2_13_B1_SampleCtrl) DP OffsetCtrl (DP_2_13_B1_OffsetCtrl) DP HCtrl (DP_2_13_B1_HCtrl) DP AsyncCtrl (DP_2_13_B1_AsyncCtrl) DP Port Ctrl (DP_2_13_Port_Ctrl) DP Config (DP_2_14_B0_Config) DP ChannelEn (DP_2_14_B0_ChannelEn) DP SampleCtrl (DP_2_14_B0_SampleCtrl) DP OffsetCtrl (DP_2_14_B0_OffsetCtrl) DP HCtrl (DP_2_14_B0_HCtrl) DP AsyncCtrl (DP_2_14_B0_AsyncCtrl) DP Config (DP_2_14_B1_Config) DP ChannelEn (DP_2_14_B1_ChannelEn) DP SampleCtrl (DP_2_14_B1_SampleCtrl) DP OffsetCtrl (DP_2_14_B1_OffsetCtrl) DP HCtrl (DP_2_14_B1_HCtrl) DP AsyncCtrl (DP_2_14_B1_AsyncCtrl) DP Port Ctrl (DP_2_14_Port_Ctrl) PDI Config (PDI_2_0_Config) PDI Config (PDI_2_1_Config) PDI Config (PDI_2_2_Config) PDI Config (PDI_2_3_Config) PDI Config (PDI_2_4_Config) PDI Config (PDI_2_5_Config) PDI Config (PDI_2_6_Config) PDI Config (PDI_2_7_Config) PDI Config (PDI_2_8_Config) PDI Config (PDI_2_9_Config) PDI Config (PDI_2_10_Config) PDI Config (PDI_2_11_Config) PDI Config (PDI_2_12_Config) PDI Config (PDI_2_13_Config) PDI Config (PDI_2_14_Config) PDI Config (PDI_2_15_Config) IP MCP Config (IP_MCP_2_Config) IP MCP Control (IP_MCP_2_Control) IP MCP CmdCtrl (IP_MCP_2_CmdCtrl) IP MCP PHYCtrl (IP_MCP_2_PHYCtrl) IP MCP B0_ClockCtrl (IP_MCP_2_B0_ClockCtrl) IP MCP Stat (IP_MCP_2_Stat) IP MCP IntSet (IP_MCP_2_IntSet) IP MCP Command (IP_MCP_2_Command) SoundWire x Link Vendor Specific Control (SNDW2LVSCTL) SoundWire x Wake Enable (SNDW2WAKEEN) SoundWire x Wake Status (SNDW2WAKESTS) SoundWire x I/O Control (SNDW2IOCTL) SoundWire x AC Timing Control (SNDW2ACTMCTL) SoundWire x Microphone Privacy Control & Status (SNDW2PVCCS) SoundWire x Link Extended Capability (SNDW3LECAP) SoundWire x PCM Stream Capabilities (SNDW3PCMSCAP) SoundWire PCM Stream y Channel Count (SNDW3PCMS0CHC) SoundWire x PCM Stream y Channel Map (SNDW3PCMS0CM) SoundWire PCM Stream y Channel Count (SNDW3PCMS1CHC) SoundWire x PCM Stream y Channel Map (SNDW3PCMS1CM) SoundWire PCM Stream y Channel Count (SNDW3PCMS2CHC) SoundWire x PCM Stream y Channel Map (SNDW3PCMS2CM) SoundWire PCM Stream y Channel Count (SNDW3PCMS3CHC) SoundWire x PCM Stream y Channel Map (SNDW3PCMS3CM) SoundWire PCM Stream y Channel Count (SNDW3PCMS4CHC) SoundWire x PCM Stream y Channel Map (SNDW3PCMS4CM) SoundWire PCM Stream y Channel Count (SNDW3PCMS5CHC) SoundWire x PCM Stream y Channel Map (SNDW3PCMS5CM) SoundWire PCM Stream y Channel Count (SNDW3PCMS6CHC) SoundWire x PCM Stream y Channel Map (SNDW3PCMS6CM) SoundWire PCM Stream y Channel Count (SNDW3PCMS7CHC) SoundWire x PCM Stream y Channel Map (SNDW3PCMS7CM) SoundWire PCM Stream y Channel Count (SNDW3PCMS8CHC) SoundWire x PCM Stream y Channel Map (SNDW3PCMS8CM) SoundWire PCM Stream y Channel Count (SNDW3PCMS9CHC) SoundWire x PCM Stream y Channel Map (SNDW3PCMS9CM) SoundWire PCM Stream y Channel Count (SNDW3PCMS10CHC) SoundWire x PCM Stream y Channel Map (SNDW3PCMS10CM) SoundWire PCM Stream y Channel Count (SNDW3PCMS11CHC) SoundWire x PCM Stream y Channel Map (SNDW3PCMS11CM) SoundWire PCM Stream y Channel Count (SNDW3PCMS12CHC) SoundWire x PCM Stream y Channel Map (SNDW3PCMS12CM) SoundWire PCM Stream y Channel Count (SNDW3PCMS13CHC) SoundWire x PCM Stream y Channel Map (SNDW3PCMS13CM) SoundWire PCM Stream y Channel Count (SNDW3PCMS14CHC) SoundWire x PCM Stream y Channel Map (SNDW3PCMS14CM) SoundWire PCM Stream y Channel Count (SNDW3PCMS15CHC) SoundWire x PCM Stream y Channel Map (SNDW3PCMS15CM) MCP Config (MCP_3_Config) MCP Control (MCP_3_Control) MCP SSPStat (MCP_3_SSPStat) MCP FrameShape (MCP_3_FrameShape) MCP FrameShapeInit (MCP_3_FrameShapeInit) MCP ConfigUpdate (MCP_3_ConfigUpdate) MCP SSPCtrl (MCP_3_B0_SSPCtrl) MCP SSPCtrl (MCP_3_B1_SSPCtrl) MCP ClockCtrl (MCP_3_B0_ClockCtrl) MCP ClockCtrl (MCP_3_B1_ClockCtrl) MCP Stat (MCP_3_Stat) MCP IntStat (MCP_3_IntStat) MCP IntMask (MCP_3_IntMask) MCP PeripheryStat (MCP_3_PeripheryStat) MCP PeripheryIntStat0 (MCP_3_PeripheryIntStat0) MCP PeripheryIntStat1 (MCP_3_PeripheryIntStat1) MCP PeripheryIntMask0 (MCP_3_PeripheryIntMask0) MCP PeripheryIntMask1 (MCP_3_PeripheryIntMask1) MCP PortIntStat (MCP_3_PortIntStat) MCP PDIStat (MCP_3_PDIStat) MCP FIFOLevel (MCP_3_FIFOLevel) MCP FIFOStat (MCP_3_FIFOStat) DP Config (DP_3_0_B0_Config) DP ChannelEn (DP_3_0_B0_ChannelEn) DP SampleCtrl (DP_3_0_B0_SampleCtrl) DP OffsetCtrl (DP_3_0_B0_OffsetCtrl) DP HCtrl (DP_3_0_B0_HCtrl) DP AsyncCtrl (DP_3_0_B0_AsyncCtrl) DP Config (DP_3_0_B1_Config) DP ChannelEn (DP_3_0_B1_ChannelEn) DP SampleCtrl (DP_3_0_B1_SampleCtrl) DP OffsetCtrl (DP_3_0_B1_OffsetCtrl) DP HCtrl (DP_3_0_B1_HCtrl) DP AsyncCtrl (DP_3_0_B1_AsyncCtrl) DP Port Ctrl (DP_3_0_Port_Ctrl) DP Config (DP_3_1_B0_Config) DP ChannelEn (DP_3_1_B0_ChannelEn) DP SampleCtrl (DP_3_1_B0_SampleCtrl) DP OffsetCtrl (DP_3_1_B0_OffsetCtrl) DP HCtrl (DP_3_1_B0_HCtrl) DP AsyncCtrl (DP_3_1_B0_AsyncCtrl) DP Config (DP_3_1_B1_Config) DP ChannelEn (DP_3_1_B1_ChannelEn) DP SampleCtrl (DP_3_1_B1_SampleCtrl) DP OffsetCtrl (DP_3_1_B1_OffsetCtrl) DP HCtrl (DP_3_1_B1_HCtrl) DP AsyncCtrl (DP_3_1_B1_AsyncCtrl) DP Port Ctrl (DP_3_1_Port_Ctrl) DP Config (DP_3_2_B0_Config) DP ChannelEn (DP_3_2_B0_ChannelEn) DP SampleCtrl (DP_3_2_B0_SampleCtrl) DP OffsetCtrl (DP_3_2_B0_OffsetCtrl) DP HCtrl (DP_3_2_B0_HCtrl) DP AsyncCtrl (DP_3_2_B0_AsyncCtrl) DP Config (DP_3_2_B1_Config) DP ChannelEn (DP_3_2_B1_ChannelEn) DP SampleCtrl (DP_3_2_B1_SampleCtrl) DP OffsetCtrl (DP_3_2_B1_OffsetCtrl) DP HCtrl (DP_3_2_B1_HCtrl) DP AsyncCtrl (DP_3_2_B1_AsyncCtrl) DP Port Ctrl (DP_3_2_Port_Ctrl) DP Config (DP_3_3_B0_Config) DP ChannelEn (DP_3_3_B0_ChannelEn) DP SampleCtrl (DP_3_3_B0_SampleCtrl) DP OffsetCtrl (DP_3_3_B0_OffsetCtrl) DP HCtrl (DP_3_3_B0_HCtrl) DP AsyncCtrl (DP_3_3_B0_AsyncCtrl) DP Config (DP_3_3_B1_Config) DP ChannelEn (DP_3_3_B1_ChannelEn) DP SampleCtrl (DP_3_3_B1_SampleCtrl) DP OffsetCtrl (DP_3_3_B1_OffsetCtrl) DP HCtrl (DP_3_3_B1_HCtrl) DP AsyncCtrl (DP_3_3_B1_AsyncCtrl) DP Port Ctrl (DP_3_3_Port_Ctrl) DP Config (DP_3_4_B0_Config) DP ChannelEn (DP_3_4_B0_ChannelEn) DP SampleCtrl (DP_3_4_B0_SampleCtrl) DP OffsetCtrl (DP_3_4_B0_OffsetCtrl) DP HCtrl (DP_3_4_B0_HCtrl) DP AsyncCtrl (DP_3_4_B0_AsyncCtrl) DP Config (DP_3_4_B1_Config) DP ChannelEn (DP_3_4_B1_ChannelEn) DP SampleCtrl (DP_3_4_B1_SampleCtrl) DP OffsetCtrl (DP_3_4_B1_OffsetCtrl) DP HCtrl (DP_3_4_B1_HCtrl) DP AsyncCtrl (DP_3_4_B1_AsyncCtrl) DP Port Ctrl (DP_3_4_Port_Ctrl) DP Config (DP_3_5_B0_Config) DP ChannelEn (DP_3_5_B0_ChannelEn) DP SampleCtrl (DP_3_5_B0_SampleCtrl) DP OffsetCtrl (DP_3_5_B0_OffsetCtrl) DP HCtrl (DP_3_5_B0_HCtrl) DP AsyncCtrl (DP_3_5_B0_AsyncCtrl) DP Config (DP_3_5_B1_Config) DP ChannelEn (DP_3_5_B1_ChannelEn) DP SampleCtrl (DP_3_5_B1_SampleCtrl) DP OffsetCtrl (DP_3_5_B1_OffsetCtrl) DP HCtrl (DP_3_5_B1_HCtrl) DP AsyncCtrl (DP_3_5_B1_AsyncCtrl) DP Port Ctrl (DP_3_5_Port_Ctrl) DP Config (DP_3_6_B0_Config) DP ChannelEn (DP_3_6_B0_ChannelEn) DP SampleCtrl (DP_3_6_B0_SampleCtrl) DP OffsetCtrl (DP_3_6_B0_OffsetCtrl) DP HCtrl (DP_3_6_B0_HCtrl) DP AsyncCtrl (DP_3_6_B0_AsyncCtrl) DP Config (DP_3_6_B1_Config) DP ChannelEn (DP_3_6_B1_ChannelEn) DP SampleCtrl (DP_3_6_B1_SampleCtrl) DP OffsetCtrl (DP_3_6_B1_OffsetCtrl) DP HCtrl (DP_3_6_B1_HCtrl) DP AsyncCtrl (DP_3_6_B1_AsyncCtrl) DP Port Ctrl (DP_3_6_Port_Ctrl) DP Config (DP_3_7_B0_Config) DP ChannelEn (DP_3_7_B0_ChannelEn) DP SampleCtrl (DP_3_7_B0_SampleCtrl) DP OffsetCtrl (DP_3_7_B0_OffsetCtrl) DP HCtrl (DP_3_7_B0_HCtrl) DP AsyncCtrl (DP_3_7_B0_AsyncCtrl) DP Config (DP_3_7_B1_Config) DP ChannelEn (DP_3_7_B1_ChannelEn) DP SampleCtrl (DP_3_7_B1_SampleCtrl) DP OffsetCtrl (DP_3_7_B1_OffsetCtrl) DP HCtrl (DP_3_7_B1_HCtrl) DP AsyncCtrl (DP_3_7_B1_AsyncCtrl) DP Port Ctrl (DP_3_7_Port_Ctrl) DP Config (DP_3_8_B0_Config) DP ChannelEn (DP_3_8_B0_ChannelEn) DP SampleCtrl (DP_3_8_B0_SampleCtrl) DP OffsetCtrl (DP_3_8_B0_OffsetCtrl) DP HCtrl (DP_3_8_B0_HCtrl) DP AsyncCtrl (DP_3_8_B0_AsyncCtrl) DP Config (DP_3_8_B1_Config) DP ChannelEn (DP_3_8_B1_ChannelEn) DP SampleCtrl (DP_3_8_B1_SampleCtrl) DP OffsetCtrl (DP_3_8_B1_OffsetCtrl) DP HCtrl (DP_3_8_B1_HCtrl) DP AsyncCtrl (DP_3_8_B1_AsyncCtrl) DP Port Ctrl (DP_3_8_Port_Ctrl) DP Config (DP_3_9_B0_Config) DP ChannelEn (DP_3_9_B0_ChannelEn) DP SampleCtrl (DP_3_9_B0_SampleCtrl) DP OffsetCtrl (DP_3_9_B0_OffsetCtrl) DP HCtrl (DP_3_9_B0_HCtrl) DP AsyncCtrl (DP_3_9_B0_AsyncCtrl) DP Config (DP_3_9_B1_Config) DP ChannelEn (DP_3_9_B1_ChannelEn) DP SampleCtrl (DP_3_9_B1_SampleCtrl) DP OffsetCtrl (DP_3_9_B1_OffsetCtrl) DP HCtrl (DP_3_9_B1_HCtrl) DP AsyncCtrl (DP_3_9_B1_AsyncCtrl) DP Port Ctrl (DP_3_9_Port_Ctrl) DP Config (DP_3_10_B0_Config) DP ChannelEn (DP_3_10_B0_ChannelEn) DP SampleCtrl (DP_3_10_B0_SampleCtrl) DP OffsetCtrl (DP_3_10_B0_OffsetCtrl) DP HCtrl (DP_3_10_B0_HCtrl) DP AsyncCtrl (DP_3_10_B0_AsyncCtrl) DP Config (DP_3_10_B1_Config) DP ChannelEn (DP_3_10_B1_ChannelEn) DP SampleCtrl (DP_3_10_B1_SampleCtrl) DP OffsetCtrl (DP_3_10_B1_OffsetCtrl) DP HCtrl (DP_3_10_B1_HCtrl) DP AsyncCtrl (DP_3_10_B1_AsyncCtrl) DP Port Ctrl (DP_3_10_Port_Ctrl) DP Config (DP_3_11_B0_Config) DP ChannelEn (DP_3_11_B0_ChannelEn) DP SampleCtrl (DP_3_11_B0_SampleCtrl) DP OffsetCtrl (DP_3_11_B0_OffsetCtrl) DP HCtrl (DP_3_11_B0_HCtrl) DP AsyncCtrl (DP_3_11_B0_AsyncCtrl) DP Config (DP_3_11_B1_Config) DP ChannelEn (DP_3_11_B1_ChannelEn) DP SampleCtrl (DP_3_11_B1_SampleCtrl) DP OffsetCtrl (DP_3_11_B1_OffsetCtrl) DP HCtrl (DP_3_11_B1_HCtrl) DP AsyncCtrl (DP_3_11_B1_AsyncCtrl) DP Port Ctrl (DP_3_11_Port_Ctrl) DP Config (DP_3_12_B0_Config) DP ChannelEn (DP_3_12_B0_ChannelEn) DP SampleCtrl (DP_3_12_B0_SampleCtrl) DP OffsetCtrl (DP_3_12_B0_OffsetCtrl) DP HCtrl (DP_3_12_B0_HCtrl) DP AsyncCtrl (DP_3_12_B0_AsyncCtrl) DP Config (DP_3_12_B1_Config) DP ChannelEn (DP_3_12_B1_ChannelEn) DP SampleCtrl (DP_3_12_B1_SampleCtrl) DP OffsetCtrl (DP_3_12_B1_OffsetCtrl) DP HCtrl (DP_3_12_B1_HCtrl) DP AsyncCtrl (DP_3_12_B1_AsyncCtrl) DP Port Ctrl (DP_3_12_Port_Ctrl) DP Config (DP_3_13_B0_Config) DP ChannelEn (DP_3_13_B0_ChannelEn) DP SampleCtrl (DP_3_13_B0_SampleCtrl) DP OffsetCtrl (DP_3_13_B0_OffsetCtrl) DP HCtrl (DP_3_13_B0_HCtrl) DP AsyncCtrl (DP_3_13_B0_AsyncCtrl) DP Config (DP_3_13_B1_Config) DP ChannelEn (DP_3_13_B1_ChannelEn) DP SampleCtrl (DP_3_13_B1_SampleCtrl) DP OffsetCtrl (DP_3_13_B1_OffsetCtrl) DP HCtrl (DP_3_13_B1_HCtrl) DP AsyncCtrl (DP_3_13_B1_AsyncCtrl) DP Port Ctrl (DP_3_13_Port_Ctrl) DP Config (DP_3_14_B0_Config) DP ChannelEn (DP_3_14_B0_ChannelEn) DP SampleCtrl (DP_3_14_B0_SampleCtrl) DP OffsetCtrl (DP_3_14_B0_OffsetCtrl) DP HCtrl (DP_3_14_B0_HCtrl) DP AsyncCtrl (DP_3_14_B0_AsyncCtrl) DP Config (DP_3_14_B1_Config) DP ChannelEn (DP_3_14_B1_ChannelEn) DP SampleCtrl (DP_3_14_B1_SampleCtrl) DP OffsetCtrl (DP_3_14_B1_OffsetCtrl) DP HCtrl (DP_3_14_B1_HCtrl) DP AsyncCtrl (DP_3_14_B1_AsyncCtrl) DP Port Ctrl (DP_3_14_Port_Ctrl) PDI Config (PDI_3_0_Config) PDI Config (PDI_3_1_Config) PDI Config (PDI_3_2_Config) PDI Config (PDI_3_3_Config) PDI Config (PDI_3_4_Config) PDI Config (PDI_3_5_Config) PDI Config (PDI_3_6_Config) PDI Config (PDI_3_7_Config) PDI Config (PDI_3_8_Config) PDI Config (PDI_3_9_Config) PDI Config (PDI_3_10_Config) PDI Config (PDI_3_11_Config) PDI Config (PDI_3_12_Config) PDI Config (PDI_3_13_Config) PDI Config (PDI_3_14_Config) PDI Config (PDI_3_15_Config) IP MCP Config (IP_MCP_3_Config) IP MCP Control (IP_MCP_3_Control) IP MCP CmdCtrl (IP_MCP_3_CmdCtrl) IP MCP PHYCtrl (IP_MCP_3_PHYCtrl) IP MCP B0_ClockCtrl (IP_MCP_3_B0_ClockCtrl) IP MCP Stat (IP_MCP_3_Stat) IP MCP IntSet (IP_MCP_3_IntSet) IP MCP Command (IP_MCP_3_Command) SoundWire x Link Vendor Specific Control (SNDW3LVSCTL) SoundWire x Wake Enable (SNDW3WAKEEN) SoundWire x Wake Status (SNDW3WAKESTS) SoundWire x I/O Control (SNDW3IOCTL) SoundWire x AC Timing Control (SNDW3ACTMCTL) SoundWire x Microphone Privacy Control & Status (SNDW3PVCCS) SoundWire x Link Extended Capability (SNDW4LECAP) SoundWire x PCM Stream Capabilities (SNDW4PCMSCAP) SoundWire PCM Stream y Channel Count (SNDW4PCMS0CHC) SoundWire x PCM Stream y Channel Map (SNDW4PCMS0CM) SoundWire PCM Stream y Channel Count (SNDW4PCMS1CHC) SoundWire x PCM Stream y Channel Map (SNDW4PCMS1CM) SoundWire PCM Stream y Channel Count (SNDW4PCMS2CHC) SoundWire x PCM Stream y Channel Map (SNDW4PCMS2CM) SoundWire PCM Stream y Channel Count (SNDW4PCMS3CHC) SoundWire x PCM Stream y Channel Map (SNDW4PCMS3CM) SoundWire PCM Stream y Channel Count (SNDW4PCMS4CHC) SoundWire x PCM Stream y Channel Map (SNDW4PCMS4CM) SoundWire PCM Stream y Channel Count (SNDW4PCMS5CHC) SoundWire x PCM Stream y Channel Map (SNDW4PCMS5CM) SoundWire PCM Stream y Channel Count (SNDW4PCMS6CHC) SoundWire x PCM Stream y Channel Map (SNDW4PCMS6CM) SoundWire PCM Stream y Channel Count (SNDW4PCMS7CHC) SoundWire x PCM Stream y Channel Map (SNDW4PCMS7CM) SoundWire PCM Stream y Channel Count (SNDW4PCMS8CHC) SoundWire x PCM Stream y Channel Map (SNDW4PCMS8CM) SoundWire PCM Stream y Channel Count (SNDW4PCMS9CHC) SoundWire x PCM Stream y Channel Map (SNDW4PCMS9CM) SoundWire PCM Stream y Channel Count (SNDW4PCMS10CHC) SoundWire x PCM Stream y Channel Map (SNDW4PCMS10CM) SoundWire PCM Stream y Channel Count (SNDW4PCMS11CHC) SoundWire x PCM Stream y Channel Map (SNDW4PCMS11CM) SoundWire PCM Stream y Channel Count (SNDW4PCMS12CHC) SoundWire x PCM Stream y Channel Map (SNDW4PCMS12CM) SoundWire PCM Stream y Channel Count (SNDW4PCMS13CHC) SoundWire x PCM Stream y Channel Map (SNDW4PCMS13CM) SoundWire PCM Stream y Channel Count (SNDW4PCMS14CHC) SoundWire x PCM Stream y Channel Map (SNDW4PCMS14CM) SoundWire PCM Stream y Channel Count (SNDW4PCMS15CHC) SoundWire x PCM Stream y Channel Map (SNDW4PCMS15CM) MCP Config (MCP_4_Config) MCP Control (MCP_4_Control) MCP SSPStat (MCP_4_SSPStat) MCP FrameShape (MCP_4_FrameShape) MCP FrameShapeInit (MCP_4_FrameShapeInit) MCP ConfigUpdate (MCP_4_ConfigUpdate) MCP SSPCtrl (MCP_4_B0_SSPCtrl) MCP SSPCtrl (MCP_4_B1_SSPCtrl) MCP ClockCtrl (MCP_4_B0_ClockCtrl) MCP ClockCtrl (MCP_4_B1_ClockCtrl) MCP Stat (MCP_4_Stat) MCP IntStat (MCP_4_IntStat) MCP IntMask (MCP_4_IntMask) MCP PeripheryStat (MCP_4_PeripheryStat) MCP PeripheryIntStat0 (MCP_4_PeripheryIntStat0) MCP PeripheryIntStat1 (MCP_4_PeripheryIntStat1) MCP PeripheryIntMask0 (MCP_4_PeripheryIntMask0) MCP PeripheryIntMask1 (MCP_4_PeripheryIntMask1) MCP PortIntStat (MCP_4_PortIntStat) MCP PDIStat (MCP_4_PDIStat) MCP FIFOLevel (MCP_4_FIFOLevel) MCP FIFOStat (MCP_4_FIFOStat) DP Config (DP_4_0_B0_Config) DP ChannelEn (DP_4_0_B0_ChannelEn) DP SampleCtrl (DP_4_0_B0_SampleCtrl) DP OffsetCtrl (DP_4_0_B0_OffsetCtrl) DP HCtrl (DP_4_0_B0_HCtrl) DP AsyncCtrl (DP_4_0_B0_AsyncCtrl) DP Config (DP_4_0_B1_Config) DP ChannelEn (DP_4_0_B1_ChannelEn) DP SampleCtrl (DP_4_0_B1_SampleCtrl) DP OffsetCtrl (DP_4_0_B1_OffsetCtrl) DP HCtrl (DP_4_0_B1_HCtrl) DP AsyncCtrl (DP_4_0_B1_AsyncCtrl) DP Port Ctrl (DP_4_0_Port_Ctrl) DP Config (DP_4_1_B0_Config) DP ChannelEn (DP_4_1_B0_ChannelEn) DP SampleCtrl (DP_4_1_B0_SampleCtrl) DP OffsetCtrl (DP_4_1_B0_OffsetCtrl) DP HCtrl (DP_4_1_B0_HCtrl) DP AsyncCtrl (DP_4_1_B0_AsyncCtrl) DP Config (DP_4_1_B1_Config) DP ChannelEn (DP_4_1_B1_ChannelEn) DP SampleCtrl (DP_4_1_B1_SampleCtrl) DP OffsetCtrl (DP_4_1_B1_OffsetCtrl) DP HCtrl (DP_4_1_B1_HCtrl) DP AsyncCtrl (DP_4_1_B1_AsyncCtrl) DP Port Ctrl (DP_4_1_Port_Ctrl) DP Config (DP_4_2_B0_Config) DP ChannelEn (DP_4_2_B0_ChannelEn) DP SampleCtrl (DP_4_2_B0_SampleCtrl) DP OffsetCtrl (DP_4_2_B0_OffsetCtrl) DP HCtrl (DP_4_2_B0_HCtrl) DP AsyncCtrl (DP_4_2_B0_AsyncCtrl) DP Config (DP_4_2_B1_Config) DP ChannelEn (DP_4_2_B1_ChannelEn) DP SampleCtrl (DP_4_2_B1_SampleCtrl) DP OffsetCtrl (DP_4_2_B1_OffsetCtrl) DP HCtrl (DP_4_2_B1_HCtrl) DP AsyncCtrl (DP_4_2_B1_AsyncCtrl) DP Port Ctrl (DP_4_2_Port_Ctrl) DP Config (DP_4_3_B0_Config) DP ChannelEn (DP_4_3_B0_ChannelEn) DP SampleCtrl (DP_4_3_B0_SampleCtrl) DP OffsetCtrl (DP_4_3_B0_OffsetCtrl) DP HCtrl (DP_4_3_B0_HCtrl) DP AsyncCtrl (DP_4_3_B0_AsyncCtrl) DP Config (DP_4_3_B1_Config) DP ChannelEn (DP_4_3_B1_ChannelEn) DP SampleCtrl (DP_4_3_B1_SampleCtrl) DP OffsetCtrl (DP_4_3_B1_OffsetCtrl) DP HCtrl (DP_4_3_B1_HCtrl) DP AsyncCtrl (DP_4_3_B1_AsyncCtrl) DP Port Ctrl (DP_4_3_Port_Ctrl) DP Config (DP_4_4_B0_Config) DP ChannelEn (DP_4_4_B0_ChannelEn) DP SampleCtrl (DP_4_4_B0_SampleCtrl) DP OffsetCtrl (DP_4_4_B0_OffsetCtrl) DP HCtrl (DP_4_4_B0_HCtrl) DP AsyncCtrl (DP_4_4_B0_AsyncCtrl) DP Config (DP_4_4_B1_Config) DP ChannelEn (DP_4_4_B1_ChannelEn) DP SampleCtrl (DP_4_4_B1_SampleCtrl) DP OffsetCtrl (DP_4_4_B1_OffsetCtrl) DP HCtrl (DP_4_4_B1_HCtrl) DP AsyncCtrl (DP_4_4_B1_AsyncCtrl) DP Port Ctrl (DP_4_4_Port_Ctrl) DP Config (DP_4_5_B0_Config) DP ChannelEn (DP_4_5_B0_ChannelEn) DP SampleCtrl (DP_4_5_B0_SampleCtrl) DP OffsetCtrl (DP_4_5_B0_OffsetCtrl) DP HCtrl (DP_4_5_B0_HCtrl) DP AsyncCtrl (DP_4_5_B0_AsyncCtrl) DP Config (DP_4_5_B1_Config) DP ChannelEn (DP_4_5_B1_ChannelEn) DP SampleCtrl (DP_4_5_B1_SampleCtrl) DP OffsetCtrl (DP_4_5_B1_OffsetCtrl) DP HCtrl (DP_4_5_B1_HCtrl) DP AsyncCtrl (DP_4_5_B1_AsyncCtrl) DP Port Ctrl (DP_4_5_Port_Ctrl) DP Config (DP_4_6_B0_Config) DP ChannelEn (DP_4_6_B0_ChannelEn) DP SampleCtrl (DP_4_6_B0_SampleCtrl) DP OffsetCtrl (DP_4_6_B0_OffsetCtrl) DP HCtrl (DP_4_6_B0_HCtrl) DP AsyncCtrl (DP_4_6_B0_AsyncCtrl) DP Config (DP_4_6_B1_Config) DP ChannelEn (DP_4_6_B1_ChannelEn) DP SampleCtrl (DP_4_6_B1_SampleCtrl) DP OffsetCtrl (DP_4_6_B1_OffsetCtrl) DP HCtrl (DP_4_6_B1_HCtrl) DP AsyncCtrl (DP_4_6_B1_AsyncCtrl) DP Port Ctrl (DP_4_6_Port_Ctrl) DP Config (DP_4_7_B0_Config) DP ChannelEn (DP_4_7_B0_ChannelEn) DP SampleCtrl (DP_4_7_B0_SampleCtrl) DP OffsetCtrl (DP_4_7_B0_OffsetCtrl) DP HCtrl (DP_4_7_B0_HCtrl) DP AsyncCtrl (DP_4_7_B0_AsyncCtrl) DP Config (DP_4_7_B1_Config) DP ChannelEn (DP_4_7_B1_ChannelEn) DP SampleCtrl (DP_4_7_B1_SampleCtrl) DP OffsetCtrl (DP_4_7_B1_OffsetCtrl) DP HCtrl (DP_4_7_B1_HCtrl) DP AsyncCtrl (DP_4_7_B1_AsyncCtrl) DP Port Ctrl (DP_4_7_Port_Ctrl) DP Config (DP_4_8_B0_Config) DP ChannelEn (DP_4_8_B0_ChannelEn) DP SampleCtrl (DP_4_8_B0_SampleCtrl) DP OffsetCtrl (DP_4_8_B0_OffsetCtrl) DP HCtrl (DP_4_8_B0_HCtrl) DP AsyncCtrl (DP_4_8_B0_AsyncCtrl) DP Config (DP_4_8_B1_Config) DP ChannelEn (DP_4_8_B1_ChannelEn) DP SampleCtrl (DP_4_8_B1_SampleCtrl) DP OffsetCtrl (DP_4_8_B1_OffsetCtrl) DP HCtrl (DP_4_8_B1_HCtrl) DP AsyncCtrl (DP_4_8_B1_AsyncCtrl) DP Port Ctrl (DP_4_8_Port_Ctrl) DP Config (DP_4_9_B0_Config) DP ChannelEn (DP_4_9_B0_ChannelEn) DP SampleCtrl (DP_4_9_B0_SampleCtrl) DP OffsetCtrl (DP_4_9_B0_OffsetCtrl) DP HCtrl (DP_4_9_B0_HCtrl) DP AsyncCtrl (DP_4_9_B0_AsyncCtrl) DP Config (DP_4_9_B1_Config) DP ChannelEn (DP_4_9_B1_ChannelEn) DP SampleCtrl (DP_4_9_B1_SampleCtrl) DP OffsetCtrl (DP_4_9_B1_OffsetCtrl) DP HCtrl (DP_4_9_B1_HCtrl) DP AsyncCtrl (DP_4_9_B1_AsyncCtrl) DP Port Ctrl (DP_4_9_Port_Ctrl) DP Config (DP_4_10_B0_Config) DP ChannelEn (DP_4_10_B0_ChannelEn) DP SampleCtrl (DP_4_10_B0_SampleCtrl) DP OffsetCtrl (DP_4_10_B0_OffsetCtrl) DP HCtrl (DP_4_10_B0_HCtrl) DP AsyncCtrl (DP_4_10_B0_AsyncCtrl) DP Config (DP_4_10_B1_Config) DP ChannelEn (DP_4_10_B1_ChannelEn) DP SampleCtrl (DP_4_10_B1_SampleCtrl) DP OffsetCtrl (DP_4_10_B1_OffsetCtrl) DP HCtrl (DP_4_10_B1_HCtrl) DP AsyncCtrl (DP_4_10_B1_AsyncCtrl) DP Port Ctrl (DP_4_10_Port_Ctrl) DP Config (DP_4_11_B0_Config) DP ChannelEn (DP_4_11_B0_ChannelEn) DP SampleCtrl (DP_4_11_B0_SampleCtrl) DP OffsetCtrl (DP_4_11_B0_OffsetCtrl) DP HCtrl (DP_4_11_B0_HCtrl) DP AsyncCtrl (DP_4_11_B0_AsyncCtrl) DP Config (DP_4_11_B1_Config) DP ChannelEn (DP_4_11_B1_ChannelEn) DP SampleCtrl (DP_4_11_B1_SampleCtrl) DP OffsetCtrl (DP_4_11_B1_OffsetCtrl) DP HCtrl (DP_4_11_B1_HCtrl) DP AsyncCtrl (DP_4_11_B1_AsyncCtrl) DP Port Ctrl (DP_4_11_Port_Ctrl) DP Config (DP_4_12_B0_Config) DP ChannelEn (DP_4_12_B0_ChannelEn) DP SampleCtrl (DP_4_12_B0_SampleCtrl) DP OffsetCtrl (DP_4_12_B0_OffsetCtrl) DP HCtrl (DP_4_12_B0_HCtrl) DP AsyncCtrl (DP_4_12_B0_AsyncCtrl) DP Config (DP_4_12_B1_Config) DP ChannelEn (DP_4_12_B1_ChannelEn) DP SampleCtrl (DP_4_12_B1_SampleCtrl) DP OffsetCtrl (DP_4_12_B1_OffsetCtrl) DP HCtrl (DP_4_12_B1_HCtrl) DP AsyncCtrl (DP_4_12_B1_AsyncCtrl) DP Port Ctrl (DP_4_12_Port_Ctrl) DP Config (DP_4_13_B0_Config) DP ChannelEn (DP_4_13_B0_ChannelEn) DP SampleCtrl (DP_4_13_B0_SampleCtrl) DP OffsetCtrl (DP_4_13_B0_OffsetCtrl) DP HCtrl (DP_4_13_B0_HCtrl) DP AsyncCtrl (DP_4_13_B0_AsyncCtrl) DP Config (DP_4_13_B1_Config) DP ChannelEn (DP_4_13_B1_ChannelEn) DP SampleCtrl (DP_4_13_B1_SampleCtrl) DP OffsetCtrl (DP_4_13_B1_OffsetCtrl) DP HCtrl (DP_4_13_B1_HCtrl) DP AsyncCtrl (DP_4_13_B1_AsyncCtrl) DP Port Ctrl (DP_4_13_Port_Ctrl) DP Config (DP_4_14_B0_Config) DP ChannelEn (DP_4_14_B0_ChannelEn) DP SampleCtrl (DP_4_14_B0_SampleCtrl) DP OffsetCtrl (DP_4_14_B0_OffsetCtrl) DP HCtrl (DP_4_14_B0_HCtrl) DP AsyncCtrl (DP_4_14_B0_AsyncCtrl) DP Config (DP_4_14_B1_Config) DP ChannelEn (DP_4_14_B1_ChannelEn) DP SampleCtrl (DP_4_14_B1_SampleCtrl) DP OffsetCtrl (DP_4_14_B1_OffsetCtrl) DP HCtrl (DP_4_14_B1_HCtrl) DP AsyncCtrl (DP_4_14_B1_AsyncCtrl) DP Port Ctrl (DP_4_14_Port_Ctrl) PDI Config (PDI_4_0_Config) PDI Config (PDI_4_1_Config) PDI Config (PDI_4_2_Config) PDI Config (PDI_4_3_Config) PDI Config (PDI_4_4_Config) PDI Config (PDI_4_5_Config) PDI Config (PDI_4_6_Config) PDI Config (PDI_4_7_Config) PDI Config (PDI_4_8_Config) PDI Config (PDI_4_9_Config) PDI Config (PDI_4_10_Config) PDI Config (PDI_4_11_Config) PDI Config (PDI_4_12_Config) PDI Config (PDI_4_13_Config) PDI Config (PDI_4_14_Config) PDI Config (PDI_4_15_Config) IP MCP Config (IP_MCP_4_Config) IP MCP Control (IP_MCP_4_Control) IP MCP CmdCtrl (IP_MCP_4_CmdCtrl) IP MCP PHYCtrl (IP_MCP_4_PHYCtrl) IP MCP B0_ClockCtrl (IP_MCP_4_B0_ClockCtrl) IP MCP Stat (IP_MCP_4_Stat) IP MCP IntSet (IP_MCP_4_IntSet) IP MCP Command (IP_MCP_4_Command) SoundWire x Link Vendor Specific Control (SNDW4LVSCTL) SoundWire x Wake Enable (SNDW4WAKEEN) SoundWire x Wake Status (SNDW4WAKESTS) SoundWire x I/O Control (SNDW4IOCTL) SoundWire x AC Timing Control (SNDW4ACTMCTL) SoundWire x Microphone Privacy Control & Status (SNDW4PVCCS)
Global Capabilities (GCAP)
Minor Version (VMIN)
Major Version (VMAJ)
Output Payload Capability (OUTPAY)
Input Payload Capability (INPAY)
Global Control (GCTL)
Wake Enable (WAKEEN)
Wake Status (WAKESTS)
Global Status (GSTS)
Global Capabilities 2 (GCAP2)
Linked List Capabilities Header (LLCH)
Output Stream Payload Capability (OUTSTRMPAY)
Input Stream Payload Capability (INSTRMPAY)
Interrupt Control (INTCTL)
Interrupt Status (INTSTS)
Wall Clock Counter (WALCLK)
Stream Synchronization (SSYNC)
CORB Lower Base Address (CORBLBASE)
CORB Upper Base Address (CORBUBASE)
CORB Write Pointer (CORBWP)
CORB Read Pointer (CORBRP)
CORB Control (CORBCTL)
CORB Status (CORBSTS)
CORB Size (CORBSIZE)
RIRB Lower Base Address (RIRBLBASE)
RIRB Upper Base Address (RIRBUBASE)
RIRB Write Pointer (RIRBWP)
Response Interrupt Count (RINTCNT)
RIRB Control (RIRBCTL)
RIRB Status (RIRBSTS)
RIRB Size (RIRBSIZE)
Immediate Command (IC)
Immediate Response (IR)
Immediate Command Status (ICS)
DMA Position Lower Base Address (DPLBASE)
DMA Position Upper Base Address (DPUBASE)
Input Stream Descriptor x Control (ISD0CTL_B0)
Input Stream Descriptor x Control (ISD0CTL_B2)
Input Stream Descriptor x Status (ISD0STS)
Input Stream Descriptor x Link Position in Buffer (ISD0LPIB)
Input Stream Descriptor x Cyclic Buffer Length (ISD0CBL)
Input Stream Descriptor x Last Valid Index (ISD0LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD0FIFOW)
Input Stream Descriptor x FIFO Size (ISD0FIFOS)
Input Stream Descriptor x Format (ISD0FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD0BDLPLBA)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD0BDLPUBA)
Input Stream Descriptor x Control (ISD1CTL_B0)
Input Stream Descriptor x Control (ISD1CTL_B2)
Input Stream Descriptor x Status (ISD1STS)
Input Stream Descriptor x Link Position in Buffer (ISD1LPIB)
Input Stream Descriptor x Cyclic Buffer Length (ISD1CBL)
Input Stream Descriptor x Last Valid Index (ISD1LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD1FIFOW)
Input Stream Descriptor x FIFO Size (ISD1FIFOS)
Input Stream Descriptor x Format (ISD1FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD1BDLPLBA)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD1BDLPUBA)
Input Stream Descriptor x Control (ISD2CTL_B0)
Input Stream Descriptor x Control (ISD2CTL_B2)
Input Stream Descriptor x Status (ISD2STS)
Input Stream Descriptor x Link Position in Buffer (ISD2LPIB)
Input Stream Descriptor x Cyclic Buffer Length (ISD2CBL)
Input Stream Descriptor x Last Valid Index (ISD2LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD2FIFOW)
Input Stream Descriptor x FIFO Size (ISD2FIFOS)
Input Stream Descriptor x Format (ISD2FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD2BDLPLBA)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD2BDLPUBA)
Input Stream Descriptor x Control (ISD3CTL_B0)
Input Stream Descriptor x Control (ISD3CTL_B2)
Input Stream Descriptor x Status (ISD3STS)
Input Stream Descriptor x Link Position in Buffer (ISD3LPIB)
Input Stream Descriptor x Cyclic Buffer Length (ISD3CBL)
Input Stream Descriptor x Last Valid Index (ISD3LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD3FIFOW)
Input Stream Descriptor x FIFO Size (ISD3FIFOS)
Input Stream Descriptor x Format (ISD3FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD3BDLPLBA)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD3BDLPUBA)
Input Stream Descriptor x Control (ISD4CTL_B0)
Input Stream Descriptor x Control (ISD4CTL_B2)
Input Stream Descriptor x Status (ISD4STS)
Input Stream Descriptor x Link Position in Buffer (ISD4LPIB)
Input Stream Descriptor x Cyclic Buffer Length (ISD4CBL)
Input Stream Descriptor x Last Valid Index (ISD4LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD4FIFOW)
Input Stream Descriptor x FIFO Size (ISD4FIFOS)
Input Stream Descriptor x Format (ISD4FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD4BDLPLBA)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD4BDLPUBA)
Input Stream Descriptor x Control (ISD5CTL_B0)
Input Stream Descriptor x Control (ISD5CTL_B2)
Input Stream Descriptor x Status (ISD5STS)
Input Stream Descriptor x Link Position in Buffer (ISD5LPIB)
Input Stream Descriptor x Cyclic Buffer Length (ISD5CBL)
Input Stream Descriptor x Last Valid Index (ISD5LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD5FIFOW)
Input Stream Descriptor x FIFO Size (ISD5FIFOS)
Input Stream Descriptor x Format (ISD5FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD5BDLPLBA)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD5BDLPUBA)
Input Stream Descriptor x Control (ISD6CTL_B0)
Input Stream Descriptor x Control (ISD6CTL_B2)
Input Stream Descriptor x Status (ISD6STS)
Input Stream Descriptor x Link Position in Buffer (ISD6LPIB)
Input Stream Descriptor x Cyclic Buffer Length (ISD6CBL)
Input Stream Descriptor x Last Valid Index (ISD6LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD6FIFOW)
Input Stream Descriptor x FIFO Size (ISD6FIFOS)
Input Stream Descriptor x Format (ISD6FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD6BDLPLBA)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD6BDLPUBA)
Input Stream Descriptor x Control (ISD7CTL_B0)
Input Stream Descriptor x Control (ISD7CTL_B2)
Input Stream Descriptor x Status (ISD7STS)
Input Stream Descriptor x Link Position in Buffer (ISD7LPIB)
Input Stream Descriptor x Cyclic Buffer Length (ISD7CBL)
Input Stream Descriptor x Last Valid Index (ISD7LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD7FIFOW)
Input Stream Descriptor x FIFO Size (ISD7FIFOS)
Input Stream Descriptor x Format (ISD7FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD7BDLPLBA)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD7BDLPUBA)
Input Stream Descriptor x Control (ISD8CTL_B0)
Input Stream Descriptor x Control (ISD8CTL_B2)
Input Stream Descriptor x Status (ISD8STS)
Input Stream Descriptor x Link Position in Buffer (ISD8LPIB)
Input Stream Descriptor x Cyclic Buffer Length (ISD8CBL)
Input Stream Descriptor x Last Valid Index (ISD8LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD8FIFOW)
Input Stream Descriptor x FIFO Size (ISD8FIFOS)
Input Stream Descriptor x Format (ISD8FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD8BDLPLBA)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD8BDLPUBA)
Input Stream Descriptor x Control (ISD9CTL_B0)
Input Stream Descriptor x Control (ISD9CTL_B2)
Input Stream Descriptor x Status (ISD9STS)
Input Stream Descriptor x Link Position in Buffer (ISD9LPIB)
Input Stream Descriptor x Cyclic Buffer Length (ISD9CBL)
Input Stream Descriptor x Last Valid Index (ISD9LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD9FIFOW)
Input Stream Descriptor x FIFO Size (ISD9FIFOS)
Input Stream Descriptor x Format (ISD9FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD9BDLPLBA)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD9BDLPUBA)
Input Stream Descriptor x Control (ISD10CTL_B0)
Input Stream Descriptor x Control (ISD10CTL_B2)
Input Stream Descriptor x Status (ISD10STS)
Input Stream Descriptor x Link Position in Buffer (ISD10LPIB)
Input Stream Descriptor x Cyclic Buffer Length (ISD10CBL)
Input Stream Descriptor x Last Valid Index (ISD10LVI)
Input Stream Descriptor x FIFO Eviction Watermark (ISD10FIFOW)
Input Stream Descriptor x FIFO Size (ISD10FIFOS)
Input Stream Descriptor x Format (ISD10FMT)
Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD10BDLPLBA)
Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD10BDLPUBA)
Output Stream Descriptor x Control (OSD0CTL_B0)
Output Stream Descriptor x Control (OSD0CTL_B2)
Output Stream Descriptor x Status (OSD0STS)
Output Stream Descriptor x Link Position in Buffer (OSD0LPIB)
Output Stream Descriptor x Cyclic Buffer Length (OSD0CBL)
Output Stream Descriptor x Last Valid Index (OSD0LVI)
Output Stream Descriptor x FIFO Eviction Watermark (OSD0FIFOW)
Output Stream Descriptor x FIFO Size (OSD0FIFOS)
Output Stream Descriptor x Format (OSD0FMT)
Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD0BDLPLBA)
Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD0BDLPUBA)
Output Stream Descriptor x Control (OSD1CTL_B0)
Output Stream Descriptor x Control (OSD1CTL_B2)
Output Stream Descriptor x Status (OSD1STS)
Output Stream Descriptor x Link Position in Buffer (OSD1LPIB)
Output Stream Descriptor x Cyclic Buffer Length (OSD1CBL)
Output Stream Descriptor x Last Valid Index (OSD1LVI)
Output Stream Descriptor x FIFO Eviction Watermark (OSD1FIFOW)
Output Stream Descriptor x FIFO Size (OSD1FIFOS)
Output Stream Descriptor x Format (OSD1FMT)
Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD1BDLPLBA)
Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD1BDLPUBA)
Output Stream Descriptor x Control (OSD2CTL_B0)
Output Stream Descriptor x Control (OSD2CTL_B2)
Output Stream Descriptor x Status (OSD2STS)
Output Stream Descriptor x Link Position in Buffer (OSD2LPIB)
Output Stream Descriptor x Cyclic Buffer Length (OSD2CBL)
Output Stream Descriptor x Last Valid Index (OSD2LVI)
Output Stream Descriptor x FIFO Eviction Watermark (OSD2FIFOW)
Output Stream Descriptor x FIFO Size (OSD2FIFOS)
Output Stream Descriptor x Format (OSD2FMT)
Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD2BDLPLBA)
Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD2BDLPUBA)
Output Stream Descriptor x Control (OSD3CTL_B0)
Output Stream Descriptor x Control (OSD3CTL_B2)
Output Stream Descriptor x Status (OSD3STS)
Output Stream Descriptor x Link Position in Buffer (OSD3LPIB)
Output Stream Descriptor x Cyclic Buffer Length (OSD3CBL)
Output Stream Descriptor x Last Valid Index (OSD3LVI)
Output Stream Descriptor x FIFO Eviction Watermark (OSD3FIFOW)
Output Stream Descriptor x FIFO Size (OSD3FIFOS)
Output Stream Descriptor x Format (OSD3FMT)
Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD3BDLPLBA)
Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD3BDLPUBA)
Output Stream Descriptor x Control (OSD4CTL_B0)
Output Stream Descriptor x Control (OSD4CTL_B2)
Output Stream Descriptor x Status (OSD4STS)
Output Stream Descriptor x Link Position in Buffer (OSD4LPIB)
Output Stream Descriptor x Cyclic Buffer Length (OSD4CBL)
Output Stream Descriptor x Last Valid Index (OSD4LVI)
Output Stream Descriptor x FIFO Eviction Watermark (OSD4FIFOW)
Output Stream Descriptor x FIFO Size (OSD4FIFOS)
Output Stream Descriptor x Format (OSD4FMT)
Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD4BDLPLBA)
Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD4BDLPUBA)
Output Stream Descriptor x Control (OSD5CTL_B0)
Output Stream Descriptor x Control (OSD5CTL_B2)
Output Stream Descriptor x Status (OSD5STS)
Output Stream Descriptor x Link Position in Buffer (OSD5LPIB)
Output Stream Descriptor x Cyclic Buffer Length (OSD5CBL)
Output Stream Descriptor x Last Valid Index (OSD5LVI)
Output Stream Descriptor x FIFO Eviction Watermark (OSD5FIFOW)
Output Stream Descriptor x FIFO Size (OSD5FIFOS)
Output Stream Descriptor x Format (OSD5FMT)
Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD5BDLPLBA)
Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD5BDLPUBA)
Output Stream Descriptor x Control (OSD6CTL_B0)
Output Stream Descriptor x Control (OSD6CTL_B2)
Output Stream Descriptor x Status (OSD6STS)
Output Stream Descriptor x Link Position in Buffer (OSD6LPIB)
Output Stream Descriptor x Cyclic Buffer Length (OSD6CBL)
Output Stream Descriptor x Last Valid Index (OSD6LVI)
Output Stream Descriptor x FIFO Eviction Watermark (OSD6FIFOW)
Output Stream Descriptor x FIFO Size (OSD6FIFOS)
Output Stream Descriptor x Format (OSD6FMT)
Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD6BDLPLBA)
Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD6BDLPUBA)
Output Stream Descriptor x Control (OSD7CTL_B0)
Output Stream Descriptor x Control (OSD7CTL_B2)
Output Stream Descriptor x Status (OSD7STS)
Output Stream Descriptor x Link Position in Buffer (OSD7LPIB)
Output Stream Descriptor x Cyclic Buffer Length (OSD7CBL)
Output Stream Descriptor x Last Valid Index (OSD7LVI)
Output Stream Descriptor x FIFO Eviction Watermark (OSD7FIFOW)
Output Stream Descriptor x FIFO Size (OSD7FIFOS)
Output Stream Descriptor x Format (OSD7FMT)
Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD7BDLPLBA)
Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD7BDLPUBA)
Output Stream Descriptor x Control (OSD8CTL_B0)
Output Stream Descriptor x Control (OSD8CTL_B2)
Output Stream Descriptor x Status (OSD8STS)
Output Stream Descriptor x Link Position in Buffer (OSD8LPIB)
Output Stream Descriptor x Cyclic Buffer Length (OSD8CBL)
Output Stream Descriptor x Last Valid Index (OSD8LVI)
Output Stream Descriptor x FIFO Eviction Watermark (OSD8FIFOW)
Output Stream Descriptor x FIFO Size (OSD8FIFOS)
Output Stream Descriptor x Format (OSD8FMT)
Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD8BDLPLBA)
Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD8BDLPUBA)
DMA Resume Capability Header (DRSMCH)
DMA Resume Control (DRSMCTL)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD0DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD1DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD2DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD3DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD4DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD5DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD6DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD7DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD8DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD9DPIBR)
Input Stream Descriptor x DMA Position in Buffer Resume (ISD10DPIBR)
Output Stream Descriptor x DMA Position in Buffer Resume (OSD0DPIBR)
Output Stream Descriptor x DMA Position in Buffer Resume (OSD1DPIBR)
Output Stream Descriptor x DMA Position in Buffer Resume (OSD2DPIBR)
Output Stream Descriptor x DMA Position in Buffer Resume (OSD3DPIBR)
Output Stream Descriptor x DMA Position in Buffer Resume (OSD4DPIBR)
Output Stream Descriptor x DMA Position in Buffer Resume (OSD5DPIBR)
Output Stream Descriptor x DMA Position in Buffer Resume (OSD6DPIBR)
Output Stream Descriptor x DMA Position in Buffer Resume (OSD7DPIBR)
Output Stream Descriptor x DMA Position in Buffer Resume (OSD8DPIBR)
Software Position Based FIFO Capability Header (SPBFCH)
Software Position Based FIFO Control (SPBFCTL)
Input Stream Descriptor x Software Position in Buffer (ISD0SPIB)
Input Stream Descriptor x Max FIFO Size (ISD0MAXFIFOS)
Input Stream Descriptor x Software Position in Buffer (ISD1SPIB)
Input Stream Descriptor x Max FIFO Size (ISD1MAXFIFOS)
Input Stream Descriptor x Software Position in Buffer (ISD2SPIB)
Input Stream Descriptor x Max FIFO Size (ISD2MAXFIFOS)
Input Stream Descriptor x Software Position in Buffer (ISD3SPIB)
Input Stream Descriptor x Max FIFO Size (ISD3MAXFIFOS)
Input Stream Descriptor x Software Position in Buffer (ISD4SPIB)
Input Stream Descriptor x Max FIFO Size (ISD4MAXFIFOS)
Input Stream Descriptor x Software Position in Buffer (ISD5SPIB)
Input Stream Descriptor x Max FIFO Size (ISD5MAXFIFOS)
Input Stream Descriptor x Software Position in Buffer (ISD6SPIB)
Input Stream Descriptor x Max FIFO Size (ISD6MAXFIFOS)
Input Stream Descriptor x Software Position in Buffer (ISD7SPIB)
Input Stream Descriptor x Max FIFO Size (ISD7MAXFIFOS)
Input Stream Descriptor x Software Position in Buffer (ISD8SPIB)
Input Stream Descriptor x Max FIFO Size (ISD8MAXFIFOS)
Input Stream Descriptor x Software Position in Buffer (ISD9SPIB)
Input Stream Descriptor x Max FIFO Size (ISD9MAXFIFOS)
Input Stream Descriptor x Software Position in Buffer (ISD10SPIB)
Input Stream Descriptor x Max FIFO Size (ISD10MAXFIFOS)
Output Stream Descriptor x Software Position in Buffer (OSD0SPIB)
Output Stream Descriptor x Max FIFO Size (OSD0MAXFIFOS)
Output Stream Descriptor x Software Position in Buffer (OSD1SPIB)
Output Stream Descriptor x Max FIFO Size (OSD1MAXFIFOS)
Output Stream Descriptor x Software Position in Buffer (OSD2SPIB)
Output Stream Descriptor x Max FIFO Size (OSD2MAXFIFOS)
Output Stream Descriptor x Software Position in Buffer (OSD3SPIB)
Output Stream Descriptor x Max FIFO Size (OSD3MAXFIFOS)
Output Stream Descriptor x Software Position in Buffer (OSD4SPIB)
Output Stream Descriptor x Max FIFO Size (OSD4MAXFIFOS)
Output Stream Descriptor x Software Position in Buffer (OSD5SPIB)
Output Stream Descriptor x Max FIFO Size (OSD5MAXFIFOS)
Output Stream Descriptor x Software Position in Buffer (OSD6SPIB)
Output Stream Descriptor x Max FIFO Size (OSD6MAXFIFOS)
Output Stream Descriptor x Software Position in Buffer (OSD7SPIB)
Output Stream Descriptor x Max FIFO Size (OSD7MAXFIFOS)
Output Stream Descriptor x Software Position in Buffer (OSD8SPIB)
Output Stream Descriptor x Max FIFO Size (OSD8MAXFIFOS)
Processing Pipe Capability Header (PPCH)
Processing Pipe Control (PPCTL)
Processing Pipe Status (PPSTS)
Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC0LLPL)
Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC0LLPU)
Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC0LDPL)
Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC0LDPU)
Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC1LLPL)
Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC1LLPU)
Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC1LDPL)
Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC1LDPU)
Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC2LLPL)
Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC2LLPU)
Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC2LDPL)
Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC2LDPU)
Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC3LLPL)
Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC3LLPU)
Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC3LDPL)
Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC3LDPU)
Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC4LLPL)
Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC4LLPU)
Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC4LDPL)
Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC4LDPU)
Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC5LLPL)
Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC5LLPU)
Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC5LDPL)
Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC5LDPU)
Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC6LLPL)
Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC6LLPU)
Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC6LDPL)
Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC6LDPU)
Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC7LLPL)
Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC7LLPU)
Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC7LDPL)
Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC7LDPU)
Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC8LLPL)
Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC8LLPU)
Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC8LDPL)
Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC8LDPU)
Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC9LLPL)
Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC9LLPU)
Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC9LDPL)
Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC9LDPU)
Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC10LLPL)
Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC10LLPU)
Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC10LDPL)
Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC10LDPU)
Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC0LLPL)
Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC0LLPU)
Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC0LDPL)
Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC0LDPU)
Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC1LLPL)
Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC1LLPU)
Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC1LDPL)
Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC1LDPU)
Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC2LLPL)
Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC2LLPU)
Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC2LDPL)
Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC2LDPU)
Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC3LLPL)
Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC3LLPU)
Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC3LDPL)
Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC3LDPU)
Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC4LLPL)
Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC4LLPU)
Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC4LDPL)
Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC4LDPU)
Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC5LLPL)
Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC5LLPU)
Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC5LDPL)
Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC5LDPU)
Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC6LLPL)
Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC6LLPU)
Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC6LDPL)
Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC6LDPU)
Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC7LLPL)
Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC7LLPU)
Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC7LDPL)
Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC7LDPU)
Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC8LLPL)
Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC8LLPU)
Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC8LDPL)
Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC8LDPU)
Input Processing Pipe Link Connection x Control (IPPLC0CTL)
Input Processing Pipe Link Connection x Format (IPPLC0FMT)
Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC0LLPL)
Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC0LLPU)
Input Processing Pipe Link Connection x Control (IPPLC1CTL)
Input Processing Pipe Link Connection x Format (IPPLC1FMT)
Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC1LLPL)
Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC1LLPU)
Input Processing Pipe Link Connection x Control (IPPLC2CTL)
Input Processing Pipe Link Connection x Format (IPPLC2FMT)
Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC2LLPL)
Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC2LLPU)
Input Processing Pipe Link Connection x Control (IPPLC3CTL)
Input Processing Pipe Link Connection x Format (IPPLC3FMT)
Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC3LLPL)
Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC3LLPU)
Input Processing Pipe Link Connection x Control (IPPLC4CTL)
Input Processing Pipe Link Connection x Format (IPPLC4FMT)
Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC4LLPL)
Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC4LLPU)
Input Processing Pipe Link Connection x Control (IPPLC5CTL)
Input Processing Pipe Link Connection x Format (IPPLC5FMT)
Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC5LLPL)
Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC5LLPU)
Input Processing Pipe Link Connection x Control (IPPLC6CTL)
Input Processing Pipe Link Connection x Format (IPPLC6FMT)
Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC6LLPL)
Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC6LLPU)
Input Processing Pipe Link Connection x Control (IPPLC7CTL)
Input Processing Pipe Link Connection x Format (IPPLC7FMT)
Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC7LLPL)
Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC7LLPU)
Input Processing Pipe Link Connection x Control (IPPLC8CTL)
Input Processing Pipe Link Connection x Format (IPPLC8FMT)
Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC8LLPL)
Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC8LLPU)
Input Processing Pipe Link Connection x Control (IPPLC9CTL)
Input Processing Pipe Link Connection x Format (IPPLC9FMT)
Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC9LLPL)
Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC9LLPU)
Input Processing Pipe Link Connection x Control (IPPLC10CTL)
Input Processing Pipe Link Connection x Format (IPPLC10FMT)
Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC10LLPL)
Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC10LLPU)
Output Processing Pipe Link Connection x Control (OPPLC0CTL)
Output Processing Pipe Link Connection x Format (OPPLC0FMT)
Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC0LLPL)
Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC0LLPU)
Output Processing Pipe Link Connection x Control (OPPLC1CTL)
Output Processing Pipe Link Connection x Format (OPPLC1FMT)
Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC1LLPL)
Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC1LLPU)
Output Processing Pipe Link Connection x Control (OPPLC2CTL)
Output Processing Pipe Link Connection x Format (OPPLC2FMT)
Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC2LLPL)
Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC2LLPU)
Output Processing Pipe Link Connection x Control (OPPLC3CTL)
Output Processing Pipe Link Connection x Format (OPPLC3FMT)
Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC3LLPL)
Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC3LLPU)
Output Processing Pipe Link Connection x Control (OPPLC4CTL)
Output Processing Pipe Link Connection x Format (OPPLC4FMT)
Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC4LLPL)
Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC4LLPU)
Output Processing Pipe Link Connection x Control (OPPLC5CTL)
Output Processing Pipe Link Connection x Format (OPPLC5FMT)
Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC5LLPL)
Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC5LLPU)
Output Processing Pipe Link Connection x Control (OPPLC6CTL)
Output Processing Pipe Link Connection x Format (OPPLC6FMT)
Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC6LLPL)
Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC6LLPU)
Output Processing Pipe Link Connection x Control (OPPLC7CTL)
Output Processing Pipe Link Connection x Format (OPPLC7FMT)
Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC7LLPL)
Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC7LLPU)
Output Processing Pipe Link Connection x Control (OPPLC8CTL)
Output Processing Pipe Link Connection x Format (OPPLC8FMT)
Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC8LLPL)
Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC8LLPU)
Multiple Links Capability Header (MLCH)
Multiple Links Capability Declaration (MLCD)
HD-A Link Capabilities (HDALCAP)
HD-A Link Control (HDALCTL)
HD-A Link Output Stream ID Valid (HDALOSIDV)
HD-A Link SDI IDentifiers (HDALSDIID)
iDisp-A Link Capabilities (IDALCAP)
iDisp-A Link Control (IDALCTL)
iDisp-A Link Output Stream ID Valid (IDALOSIDV)
iDisp-A Link SDI IDentifiers (IDALSDIID)
iDisp-A Link Per Stream Output Overhead (IDALPSOO)
iDisp-A Link Per Stream Input Overhead (IDALPSIO)
iDisp-A Link Wall Frame Counter (IDALWALFC)
iDisp-A Link 6 MHz Output Payload Capability (IDALOUTPAY6)
iDisp-A Link 12 MHz Output Payload Capability (IDALOUTPAY12)
iDisp-A Link 24 MHz Output Payload Capability (IDALOUTPAY24)
iDisp-A Link 48 MHz Output Payload Capability (IDALOUTPAY48)
iDisp-A Link 96 MHz Output Payload Capability (IDALOUTPAY96)
iDisp-A Link 6 MHz Input Payload Capability (IDALINPAY6)
iDisp-A Link 12 MHz Input Payload Capability (IDALINPAY12)
iDisp-A Link 24 MHz Input Payload Capability (IDALINPAY24)
iDisp-A Link 48 MHz Input Payload Capability (IDALINPAY48)
iDisp-A Link 96 MHz Input Payload Capability (IDALINPAY96)
DMIC Link Capabilities (DMICLCAP)
DMIC Link Control (DMICLCTL)
DMIC Link Output Stream ID Valid (DMICLOSIDV)
DMIC Link SDI IDentifiers (DMICLSDIID)
DMIC Link Synchronization (DMICLSYNC)
DMIC Link Extension Pointer (DMICLEPTR)
I2S / PCM Link Capabilities (I2SLCAP)
I2S / PCM Link Control (I2SLCTL)
I2S / PCM Link Output Stream ID Valid (I2SLOSIDV)
I2S / PCM Link SDI IDentifiers (I2SLSDIID0)
I2S / PCM Link Synchronization (I2SLSYNC)
I2S / PCM Link Extension Pointer (I2SLEPTR)
USB Audio Offload Link Capabilities (UAOLCAP)
USB Audio Offload Link Control (UAOLCTL)
USB Audio Offload Link Output Stream ID Valid (UAOLOSIDV)
USB Audio Offload Link SDI IDentifiers (UAOLSDIID)
USB Audio Offload Link Extension Pointer (UAOLEPTR)
SoundWire Link Capabilities (SNDWLCAP)
SoundWire Link Control (SNDWLCTL)
SoundWire Link Output Stream ID Valid (SNDWLOSIDV)
SoundWire Link SDI IDentifiers (SNDWLSDIID0)
SoundWire Link SDI IDentifiers (SNDWLSDIID1)
SoundWire Link SDI IDentifiers (SNDWLSDIID2)
SoundWire Link SDI IDentifiers (SNDWLSDIID3)
SoundWire Link SDI IDentifiers (SNDWLSDIID4)
SoundWire Link Synchronization (SNDWLSYNC)
SoundWire Link Extension Pointer (SNDWLEPTR)
IOSF Status (IOSFSTS)
Traffic Class Assignments (TCA)
Transfer Traffic Class Configuration (TTCCFG)
Codec Configuration (CDCCFG)
Host PCI Configuration Control (HfPCICFGCTL)
Fuse Value (FUSVAL)
Set ID Value (DW0) (SETIDVAL0)
Set ID Value (DW1) (SETIDVAL1)
Hard Strap Value (HSTRVAL)
Soft Strap Value (SSTRVAL)
HD-A Hardware Initialization (DW0) (HDAHWI0)
HD-A Hardware Initialization (DW1) (HDAHWI1)
Host PCI Configuration Hardware Initialization (DW 0) (HfPCICFGHWI0)
Host PCI Configuration Hardware Initialization (DW 1) (HfPCICFGHWI1)
Host PCI Configuration Soft Strap Value (DW 0) (HfPCICFGSSV0)
Host PCI Configuration Soft Strap Value (DW 1) (HfPCICFGSSV1)
Host PCI Configuration Hardware Initialization Select (HfPCICFGHWIS)
Power Management / Clock Capability (HfPMCCAP)
Power Management / Clock Control (HST) Pointer (HfPMCCHPTR)
Clock Control (HfCLKCTL)
Clock Status (HfCLKSTS)
Power Control (HfPWRCTL)
Power Status (HfPWRSTS)
Power Control 2 (HfPWRCTL2)
Power Status 2 (HfPWRSTS2)
D0i3 Control (D0I3C)
Function Configuration (FNCFG)
Wall Clock Counter Alias (WALCLKA)
Input Stream Descriptor x Link Position in Buffer Alias (ISD0LPIBA)
Input Stream Descriptor x Link Position in Buffer Alias (ISD1LPIBA)
Input Stream Descriptor x Link Position in Buffer Alias (ISD2LPIBA)
Input Stream Descriptor x Link Position in Buffer Alias (ISD3LPIBA)
Input Stream Descriptor x Link Position in Buffer Alias (ISD4LPIBA)
Input Stream Descriptor x Link Position in Buffer Alias (ISD5LPIBA)
Input Stream Descriptor x Link Position in Buffer Alias (ISD6LPIBA)
Input Stream Descriptor x Link Position in Buffer Alias (ISD7LPIBA)
Input Stream Descriptor x Link Position in Buffer Alias (ISD8LPIBA)
Input Stream Descriptor x Link Position in Buffer Alias (ISD9LPIBA)
Input Stream Descriptor x Link Position in Buffer Alias (ISD10LPIBA)
Output Stream Descriptor x Link Position in Buffer Alias (OSD0LPIBA)
Output Stream Descriptor x Link Position in Buffer Alias (OSD1LPIBA)
Output Stream Descriptor x Link Position in Buffer Alias (OSD2LPIBA)
Output Stream Descriptor x Link Position in Buffer Alias (OSD3LPIBA)
Output Stream Descriptor x Link Position in Buffer Alias (OSD4LPIBA)
Output Stream Descriptor x Link Position in Buffer Alias (OSD5LPIBA)
Output Stream Descriptor x Link Position in Buffer Alias (OSD6LPIBA)
Output Stream Descriptor x Link Position in Buffer Alias (OSD7LPIBA)
Output Stream Descriptor x Link Position in Buffer Alias (OSD8LPIBA)
USB Audio Offload Link x PCM Stream Capabilities (UAOL0PCMSCAP)
USB Audio Offload Link x PCM Stream y Channel Count (UAOL0PCMS0CHC)
USB Audio Offload Link x PCM Stream y Channel Map (UAOL0PCMS0CM)
USB Audio Offload Link x PCM Stream y Channel Count (UAOL0PCMS1CHC)
USB Audio Offload Link x PCM Stream y Channel Map (UAOL0PCMS1CM)
USB Audio Offload Link x PCM Stream y Channel Count (UAOL0PCMS2CHC)
USB Audio Offload Link x PCM Stream y Channel Map (UAOL0PCMS2CM)
USB Audio Offload Link x PCM Stream y Channel Count (UAOL0PCMS3CHC)
USB Audio Offload Link x PCM Stream y Channel Map (UAOL0PCMS3CM)
USB Audio Offload Link x PCM Stream y Channel Count (UAOL0PCMS4CHC)
USB Audio Offload Link x PCM Stream y Channel Map (UAOL0PCMS4CM)
USB Audio Offload Link x PCM Stream y Channel Count (UAOL0PCMS5CHC)
USB Audio Offload Link x PCM Stream y Channel Map (UAOL0PCMS5CM)
USB Audio Offload Link x Target Bus / Device / Function (UAOL0TBDF)
USB Audio Offload Link x Output Payload Capability (UAOL0OPC)
USB Audio Offload Link x Input Payload Capability (UAOL0IPC)
USB Audio Offload Link x Frame Counter (UAOL0FC)
USB Audio Offload Link x Frame Adjustment (UAOL0FA)
USB Audio Offload Link x Immediate Command (UAOL0IC)
USB Audio Offload Link x Immediate Response (UAOL0IR)
USB Audio Offload Link x Immediate Command Payload y (UAOL0ICP0)
USB Audio Offload Link x Immediate Command Payload y (UAOL0ICP1)
USB Audio Offload Link x Immediate Command Payload y (UAOL0ICP2)
USB Audio Offload Link x Immediate Command Payload y (UAOL0ICP3)
USB Audio Offload Link x Immediate Response Payload y (UAOL0IRP0)
USB Audio Offload Link x Immediate Response Payload y (UAOL0IRP1)
USB Audio Offload Link x Immediate Response Payload y (UAOL0IRP2)
USB Audio Offload Link x Immediate Response Payload y (UAOL0IRP3)
USB Audio Offload Link x PCM Stream y Format (UAOL0PCMS0CTL)
USB Audio Offload Link x PCM Stream y Status (UAOL0PCMS0STS)
USB Audio Offload Link x PCM Stream y Fractional Rate Adjustment (UAOL0PCMS0RA)
USB Audio Offload Link x PCM Stream y FIFO Address (UAOL0PCMS0FSA)
USB Audio Offload Link x PCM Stream y Format (UAOL0PCMS1CTL)
USB Audio Offload Link x PCM Stream y Status (UAOL0PCMS1STS)
USB Audio Offload Link x PCM Stream y Fractional Rate Adjustment (UAOL0PCMS1RA)
USB Audio Offload Link x PCM Stream y FIFO Address (UAOL0PCMS1FSA)
USB Audio Offload Link x PCM Stream y Format (UAOL0PCMS2CTL)
USB Audio Offload Link x PCM Stream y Status (UAOL0PCMS2STS)
USB Audio Offload Link x PCM Stream y Fractional Rate Adjustment (UAOL0PCMS2RA)
USB Audio Offload Link x PCM Stream y FIFO Address (UAOL0PCMS2FSA)
USB Audio Offload Link x PCM Stream y Format (UAOL0PCMS3CTL)
USB Audio Offload Link x PCM Stream y Status (UAOL0PCMS3STS)
USB Audio Offload Link x PCM Stream y Fractional Rate Adjustment (UAOL0PCMS3RA)
USB Audio Offload Link x PCM Stream y FIFO Address (UAOL0PCMS3FSA)
USB Audio Offload Link x PCM Stream y Format (UAOL0PCMS4CTL)
USB Audio Offload Link x PCM Stream y Status (UAOL0PCMS4STS)
USB Audio Offload Link x PCM Stream y Fractional Rate Adjustment (UAOL0PCMS4RA)
USB Audio Offload Link x PCM Stream y FIFO Address (UAOL0PCMS4FSA)
USB Audio Offload Link x PCM Stream y Format (UAOL0PCMS5CTL)
USB Audio Offload Link x PCM Stream y Status (UAOL0PCMS5STS)
USB Audio Offload Link x PCM Stream y Fractional Rate Adjustment (UAOL0PCMS5RA)
USB Audio Offload Link x PCM Stream y FIFO Address (UAOL0PCMS5FSA)
USB Audio Offload Link x Vendor Specific Control (UAOL0VSCTL)
Digital Microphone x PCM Stream Capabilities (DMIC0PCMSCAP)
Digital Microphone PCM Stream y Channel Count (DMIC0PCMS0CHC)
Digital Microphone x PCM Stream y Channel Map (DMIC0PCMS0CM)
Digital Microphone PCM Stream y Channel Count (DMIC0PCMS1CHC)
Digital Microphone x PCM Stream y Channel Map (DMIC0PCMS1CM)
Microphone HiQ Output Control and Status Register (OUTCONTROL0)
Microphone HiQ Channel Status Register (OUTSTATUS0)
Microphone Data Readout and Test Registers (OUTDATA0)
Microphone HiQ Output Control and Status Register (OUTCONTROL1)
Microphone HiQ Channel Status Register (OUTSTATUS1)
Microphone Data Readout and Test Registers (OUTDATA1)
CIC Filter Control Register (PDMCTRL0_CIC_CONTROL)
CIC Filter Configuration Register (PDMCTRL0_CIC_CONFIG)
Microphone Control Register (PDMCTRL0_MIC_CONTROL)
FIR Filter Control Register (PDMCTRL0_FIR_CONTROL_A)
FIR Filter Configuration Register (PDMCTRL0_FIR_CONFIG_A)
DC Offset Control Register, left channel (PDMCTRL0_DC_OFFSET_LEFT_A)
DC Offset Control Register, right channel (PDMCTRL0_DC_OFFSET_RIGHT_A)
Output Gain Control Register, left channel (PDMCTRL0_OUT_GAIN_LEFT_A)
Output Gain Control Register, right channel (PDMCTRL0_OUT_GAIN_RIGHT_A)
FIR Filter Control Register (PDMCTRL0_FIR_CONTROL_B)
FIR Filter Configuration Register (PDMCTRL0_FIR_CONFIG_B)
DC Offset Control Register, left channel (PDMCTRL0_DC_OFFSET_LEFT_B)
DC Offset Control Register, right channel (PDMCTRL0_DC_OFFSET_RIGHT_B)
Output Gain Control Register, left channel (PDMCTRL0_OUT_GAIN_LEFT_B)
Output Gain Control Register, right channel (PDMCTRL0_OUT_GAIN_RIGHT_B)
CIC Filter Control Register (PDMCTRL1_CIC_CONTROL)
CIC Filter Configuration Register (PDMCTRL1_CIC_CONFIG)
Microphone Control Register (PDMCTRL1_MIC_CONTROL)
FIR Filter Control Register (PDMCTRL1_FIR_CONTROL_A)
FIR Filter Configuration Register (PDMCTRL1_FIR_CONFIG_A)
DC Offset Control Register, left channel (PDMCTRL1_DC_OFFSET_LEFT_A)
DC Offset Control Register, right channel (PDMCTRL1_DC_OFFSET_RIGHT_A)
Output Gain Control Register, left channel (PDMCTRL1_OUT_GAIN_LEFT_A)
Output Gain Control Register, right channel (PDMCTRL1_OUT_GAIN_RIGHT_A)
FIR Filter Control Register (PDMCTRL1_FIR_CONTROL_B)
FIR Filter Configuration Register (PDMCTRL1_FIR_CONFIG_B)
DC Offset Control Register, left channel (PDMCTRL1_DC_OFFSET_LEFT_B)
DC Offset Control Register, right channel (PDMCTRL1_DC_OFFSET_RIGHT_B)
Output Gain Control Register, left channel (PDMCTRL1_OUT_GAIN_LEFT_B)
Output Gain Control Register, right channel (PDMCTRL1_OUT_GAIN_RIGHT_B)
Digital Microphone x Link Vendor Specific Control (DMIC0LVSCTL)
Digital Microphone x Privacy Control & Status (DMIC0PVCCS)
I2S x PCM Stream Capabilities (I2S0PCMSCAP)
I2S x PCM Stream y Channel Count (I2S0PCMS0CHC)
I2S x PCM Stream y Channel Map (I2S0PCMS0CM)
I2S x PCM Stream y Channel Count (I2S0PCMS1CHC)
I2S x PCM Stream y Channel Map (I2S0PCMS1CM)
I2S x PCM Stream y Channel Count (I2S0PCMS2CHC)
I2S x PCM Stream y Channel Map (I2S0PCMS2CM)
I2S x PCM Stream y Channel Count (I2S0PCMS3CHC)
I2S x PCM Stream y Channel Map (I2S0PCMS3CM)
I2S x PCM Stream y Channel Count (I2S0PCMS4CHC)
I2S x PCM Stream y Channel Map (I2S0PCMS4CM)
I2S x PCM Stream y Channel Count (I2S0PCMS5CHC)
I2S x PCM Stream y Channel Map (I2S0PCMS5CM)
I2S x PCM Stream y Channel Count (I2S0PCMS6CHC)
I2S x PCM Stream y Channel Map (I2S0PCMS6CM)
I2S x PCM Stream y Channel Count (I2S0PCMS7CHC)
I2S x PCM Stream y Channel Map (I2S0PCMS7CM)
I2S x PCM Stream y Channel Count (I2S0PCMS8CHC)
I2S x PCM Stream y Channel Map (I2S0PCMS8CM)
I2S x PCM Stream y Channel Count (I2S0PCMS9CHC)
I2S x PCM Stream y Channel Map (I2S0PCMS9CM)
I2S x PCM Stream y Channel Count (I2S0PCMS10CHC)
I2S x PCM Stream y Channel Map (I2S0PCMS10CM)
I2S x PCM Stream y Channel Count (I2S0PCMS11CHC)
I2S x PCM Stream y Channel Map (I2S0PCMS11CM)
I2S x PCM Stream y Channel Count (I2S0PCMS12CHC)
I2S x PCM Stream y Channel Map (I2S0PCMS12CM)
I2S x PCM Stream y Channel Count (I2S0PCMS13CHC)
I2S x PCM Stream y Channel Map (I2S0PCMS13CM)
I2S x PCM Stream y Channel Count (I2S0PCMS14CHC)
I2S x PCM Stream y Channel Map (I2S0PCMS14CM)
I2S x PCM Stream y Channel Count (I2S0PCMS15CHC)
I2S x PCM Stream y Channel Map (I2S0PCMS15CM)
SSP x Control 0 (I2S0_SSC0)
SSP x Control 1 (I2S0_SSC1)
SSP x Status (I2S0_SSS)
SSP x Time Out (I2S0_SSTO)
SSP x Programmable Serial Protocol (I2S0_SSPSP)
SSP x Time Slot Status (I2S0_SSTSS)
SSP x Command / Status 2 (I2S0_SSC2)
SSP x Programmable Serial Protocol 2 (I2S0_SSPSP2)
SSP x Reserved 2 (I2S0_SSRSVD2)
SSP x IO Control (I2S0_SSIOC)
SSP x Global Frame Synchronization (I2S0_SSGFS)
SSP x Multi Input DMA y Control / Status (I2S0_SSMID0CS)
SSP x Multi Input DMA y Data (I2S0_SSMID0D)
SSP x Multi Input DMA y Time Slot Active (I2S0_SSMID0TSA)
SSP x Multi Input DMA y Control / Status (I2S0_SSMID1CS)
SSP x Multi Input DMA y Data (I2S0_SSMID1D)
SSP x Multi Input DMA y Time Slot Active (I2S0_SSMID1TSA)
SSP x Multi Input DMA y Control / Status (I2S0_SSMID2CS)
SSP x Multi Input DMA y Data (I2S0_SSMID2D)
SSP x Multi Input DMA y Time Slot Active (I2S0_SSMID2TSA)
SSP x Multi Input DMA y Control / Status (I2S0_SSMID3CS)
SSP x Multi Input DMA y Data (I2S0_SSMID3D)
SSP x Multi Input DMA y Time Slot Active (I2S0_SSMID3TSA)
SSP x Multi Input DMA y Control / Status (I2S0_SSMID4CS)
SSP x Multi Input DMA y Data (I2S0_SSMID4D)
SSP x Multi Input DMA y Time Slot Active (I2S0_SSMID4TSA)
SSP x Multi Input DMA y Control / Status (I2S0_SSMID5CS)
SSP x Multi Input DMA y Data (I2S0_SSMID5D)
SSP x Multi Input DMA y Time Slot Active (I2S0_SSMID5TSA)
SSP x Multi Input DMA y Control / Status (I2S0_SSMID6CS)
SSP x Multi Input DMA y Data (I2S0_SSMID6D)
SSP x Multi Input DMA y Time Slot Active (I2S0_SSMID6TSA)
SSP x Multi Input DMA y Control / Status (I2S0_SSMID7CS)
SSP x Multi Input DMA y Data (I2S0_SSMID7D)
SSP x Multi Input DMA y Time Slot Active (I2S0_SSMID7TSA)
SSP x Multi Output DMA y Control / Status (I2S0_SSMOD0CS)
SSP x Multi Output DMA y Data (I2S0_SSMOD0D)
SSP x Multi Output DMA y Time Slot Active (I2S0_SSMOD0TSA)
SSP x Multi Output DMA y Control / Status (I2S0_SSMOD1CS)
SSP x Multi Output DMA y Data (I2S0_SSMOD1D)
SSP x Multi Output DMA y Time Slot Active (I2S0_SSMOD1TSA)
SSP x Multi Output DMA y Control / Status (I2S0_SSMOD2CS)
SSP x Multi Output DMA y Data (I2S0_SSMOD2D)
SSP x Multi Output DMA y Time Slot Active (I2S0_SSMOD2TSA)
SSP x Multi Output DMA y Control / Status (I2S0_SSMOD3CS)
SSP x Multi Output DMA y Data (I2S0_SSMOD3D)
SSP x Multi Output DMA y Time Slot Active (I2S0_SSMOD3TSA)
SSP x Multi Output DMA y Control / Status (I2S0_SSMOD4CS)
SSP x Multi Output DMA y Data (I2S0_SSMOD4D)
SSP x Multi Output DMA y Time Slot Active (I2S0_SSMOD4TSA)
SSP x Multi Output DMA y Control / Status (I2S0_SSMOD5CS)
SSP x Multi Output DMA y Data (I2S0_SSMOD5D)
SSP x Multi Output DMA y Time Slot Active (I2S0_SSMOD5TSA)
SSP x Multi Output DMA y Control / Status (I2S0_SSMOD6CS)
SSP x Multi Output DMA y Data (I2S0_SSMOD6D)
SSP x Multi Output DMA y Time Slot Active (I2S0_SSMOD6TSA)
SSP x Multi Output DMA y Control / Status (I2S0_SSMOD7CS)
SSP x Multi Output DMA y Data (I2S0_SSMOD7D)
SSP x Multi Output DMA y Time Slot Active (I2S0_SSMOD7TSA)
I2S x Link Vendor Specific Control (I2S0LVSCTL)
I2S x PCM Stream Capabilities (I2S1PCMSCAP)
I2S x PCM Stream y Channel Count (I2S1PCMS0CHC)
I2S x PCM Stream y Channel Map (I2S1PCMS0CM)
I2S x PCM Stream y Channel Count (I2S1PCMS1CHC)
I2S x PCM Stream y Channel Map (I2S1PCMS1CM)
I2S x PCM Stream y Channel Count (I2S1PCMS2CHC)
I2S x PCM Stream y Channel Map (I2S1PCMS2CM)
I2S x PCM Stream y Channel Count (I2S1PCMS3CHC)
I2S x PCM Stream y Channel Map (I2S1PCMS3CM)
I2S x PCM Stream y Channel Count (I2S1PCMS4CHC)
I2S x PCM Stream y Channel Map (I2S1PCMS4CM)
I2S x PCM Stream y Channel Count (I2S1PCMS5CHC)
I2S x PCM Stream y Channel Map (I2S1PCMS5CM)
I2S x PCM Stream y Channel Count (I2S1PCMS6CHC)
I2S x PCM Stream y Channel Map (I2S1PCMS6CM)
I2S x PCM Stream y Channel Count (I2S1PCMS7CHC)
I2S x PCM Stream y Channel Map (I2S1PCMS7CM)
I2S x PCM Stream y Channel Count (I2S1PCMS8CHC)
I2S x PCM Stream y Channel Map (I2S1PCMS8CM)
I2S x PCM Stream y Channel Count (I2S1PCMS9CHC)
I2S x PCM Stream y Channel Map (I2S1PCMS9CM)
I2S x PCM Stream y Channel Count (I2S1PCMS10CHC)
I2S x PCM Stream y Channel Map (I2S1PCMS10CM)
I2S x PCM Stream y Channel Count (I2S1PCMS11CHC)
I2S x PCM Stream y Channel Map (I2S1PCMS11CM)
I2S x PCM Stream y Channel Count (I2S1PCMS12CHC)
I2S x PCM Stream y Channel Map (I2S1PCMS12CM)
I2S x PCM Stream y Channel Count (I2S1PCMS13CHC)
I2S x PCM Stream y Channel Map (I2S1PCMS13CM)
I2S x PCM Stream y Channel Count (I2S1PCMS14CHC)
I2S x PCM Stream y Channel Map (I2S1PCMS14CM)
I2S x PCM Stream y Channel Count (I2S1PCMS15CHC)
I2S x PCM Stream y Channel Map (I2S1PCMS15CM)
SSP x Control 0 (I2S1_SSC0)
SSP x Control 1 (I2S1_SSC1)
SSP x Status (I2S1_SSS)
SSP x Time Out (I2S1_SSTO)
SSP x Programmable Serial Protocol (I2S1_SSPSP)
SSP x Time Slot Status (I2S1_SSTSS)
SSP x Command / Status 2 (I2S1_SSC2)
SSP x Programmable Serial Protocol 2 (I2S1_SSPSP2)
SSP x IO Control (I2S1_SSIOC)
SSP x Global Frame Synchronization (I2S1_SSGFS)
SSP x Multi Input DMA y Control / Status (I2S1_SSMID0CS)
SSP x Multi Input DMA y Data (I2S1_SSMID0D)
SSP x Multi Input DMA y Time Slot Active (I2S1_SSMID0TSA)
SSP x Multi Input DMA y Control / Status (I2S1_SSMID1CS)
SSP x Multi Input DMA y Data (I2S1_SSMID1D)
SSP x Multi Input DMA y Time Slot Active (I2S1_SSMID1TSA)
SSP x Multi Input DMA y Control / Status (I2S1_SSMID2CS)
SSP x Multi Input DMA y Data (I2S1_SSMID2D)
SSP x Multi Input DMA y Time Slot Active (I2S1_SSMID2TSA)
SSP x Multi Input DMA y Control / Status (I2S1_SSMID3CS)
SSP x Multi Input DMA y Data (I2S1_SSMID3D)
SSP x Multi Input DMA y Time Slot Active (I2S1_SSMID3TSA)
SSP x Multi Input DMA y Control / Status (I2S1_SSMID4CS)
SSP x Multi Input DMA y Data (I2S1_SSMID4D)
SSP x Multi Input DMA y Time Slot Active (I2S1_SSMID4TSA)
SSP x Multi Input DMA y Control / Status (I2S1_SSMID5CS)
SSP x Multi Input DMA y Data (I2S1_SSMID5D)
SSP x Multi Input DMA y Time Slot Active (I2S1_SSMID5TSA)
SSP x Multi Input DMA y Control / Status (I2S1_SSMID6CS)
SSP x Multi Input DMA y Data (I2S1_SSMID6D)
SSP x Multi Input DMA y Time Slot Active (I2S1_SSMID6TSA)
SSP x Multi Input DMA y Control / Status (I2S1_SSMID7CS)
SSP x Multi Input DMA y Data (I2S1_SSMID7D)
SSP x Multi Input DMA y Time Slot Active (I2S1_SSMID7TSA)
SSP x Multi Output DMA y Control / Status (I2S1_SSMOD0CS)
SSP x Multi Output DMA y Data (I2S1_SSMOD0D)
SSP x Multi Output DMA y Time Slot Active (I2S1_SSMOD0TSA)
SSP x Multi Output DMA y Control / Status (I2S1_SSMOD1CS)
SSP x Multi Output DMA y Data (I2S1_SSMOD1D)
SSP x Multi Output DMA y Time Slot Active (I2S1_SSMOD1TSA)
SSP x Multi Output DMA y Control / Status (I2S1_SSMOD2CS)
SSP x Multi Output DMA y Data (I2S1_SSMOD2D)
SSP x Multi Output DMA y Time Slot Active (I2S1_SSMOD2TSA)
SSP x Multi Output DMA y Control / Status (I2S1_SSMOD3CS)
SSP x Multi Output DMA y Data (I2S1_SSMOD3D)
SSP x Multi Output DMA y Time Slot Active (I2S1_SSMOD3TSA)
SSP x Multi Output DMA y Control / Status (I2S1_SSMOD4CS)
SSP x Multi Output DMA y Data (I2S1_SSMOD4D)
SSP x Multi Output DMA y Time Slot Active (I2S1_SSMOD4TSA)
SSP x Multi Output DMA y Control / Status (I2S1_SSMOD5CS)
SSP x Multi Output DMA y Data (I2S1_SSMOD5D)
SSP x Multi Output DMA y Time Slot Active (I2S1_SSMOD5TSA)
SSP x Multi Output DMA y Control / Status (I2S1_SSMOD6CS)
SSP x Multi Output DMA y Data (I2S1_SSMOD6D)
SSP x Multi Output DMA y Time Slot Active (I2S1_SSMOD6TSA)
SSP x Multi Output DMA y Control / Status (I2S1_SSMOD7CS)
SSP x Multi Output DMA y Data (I2S1_SSMOD7D)
SSP x Multi Output DMA y Time Slot Active (I2S1_SSMOD7TSA)
I2S x Link Vendor Specific Control (I2S1LVSCTL)
I2S x PCM Stream Capabilities (I2S2PCMSCAP)
I2S x PCM Stream y Channel Count (I2S2PCMS0CHC)
I2S x PCM Stream y Channel Map (I2S2PCMS0CM)
I2S x PCM Stream y Channel Count (I2S2PCMS1CHC)
I2S x PCM Stream y Channel Map (I2S2PCMS1CM)
I2S x PCM Stream y Channel Count (I2S2PCMS2CHC)
I2S x PCM Stream y Channel Map (I2S2PCMS2CM)
I2S x PCM Stream y Channel Count (I2S2PCMS3CHC)
I2S x PCM Stream y Channel Map (I2S2PCMS3CM)
I2S x PCM Stream y Channel Count (I2S2PCMS4CHC)
I2S x PCM Stream y Channel Map (I2S2PCMS4CM)
I2S x PCM Stream y Channel Count (I2S2PCMS5CHC)
I2S x PCM Stream y Channel Map (I2S2PCMS5CM)
I2S x PCM Stream y Channel Count (I2S2PCMS6CHC)
I2S x PCM Stream y Channel Map (I2S2PCMS6CM)
I2S x PCM Stream y Channel Count (I2S2PCMS7CHC)
I2S x PCM Stream y Channel Map (I2S2PCMS7CM)
I2S x PCM Stream y Channel Count (I2S2PCMS8CHC)
I2S x PCM Stream y Channel Map (I2S2PCMS8CM)
I2S x PCM Stream y Channel Count (I2S2PCMS9CHC)
I2S x PCM Stream y Channel Map (I2S2PCMS9CM)
I2S x PCM Stream y Channel Count (I2S2PCMS10CHC)
I2S x PCM Stream y Channel Map (I2S2PCMS10CM)
I2S x PCM Stream y Channel Count (I2S2PCMS11CHC)
I2S x PCM Stream y Channel Map (I2S2PCMS11CM)
I2S x PCM Stream y Channel Count (I2S2PCMS12CHC)
I2S x PCM Stream y Channel Map (I2S2PCMS12CM)
I2S x PCM Stream y Channel Count (I2S2PCMS13CHC)
I2S x PCM Stream y Channel Map (I2S2PCMS13CM)
I2S x PCM Stream y Channel Count (I2S2PCMS14CHC)
I2S x PCM Stream y Channel Map (I2S2PCMS14CM)
I2S x PCM Stream y Channel Count (I2S2PCMS15CHC)
I2S x PCM Stream y Channel Map (I2S2PCMS15CM)
SSP x Control 0 (I2S2_SSC0)
SSP x Control 1 (I2S2_SSC1)
SSP x Status (I2S2_SSS)
SSP x Time Out (I2S2_SSTO)
SSP x Programmable Serial Protocol (I2S2_SSPSP)
SSP x Time Slot Status (I2S2_SSTSS)
SSP x Command / Status 2 (I2S2_SSC2)
SSP x Programmable Serial Protocol 2 (I2S2_SSPSP2)
SSP x IO Control (I2S2_SSIOC)
SSP x Global Frame Synchronization (I2S2_SSGFS)
SSP x Multi Input DMA y Control / Status (I2S2_SSMID0CS)
SSP x Multi Input DMA y Data (I2S2_SSMID0D)
SSP x Multi Input DMA y Time Slot Active (I2S2_SSMID0TSA)
SSP x Multi Input DMA y Control / Status (I2S2_SSMID1CS)
SSP x Multi Input DMA y Data (I2S2_SSMID1D)
SSP x Multi Input DMA y Time Slot Active (I2S2_SSMID1TSA)
SSP x Multi Input DMA y Control / Status (I2S2_SSMID2CS)
SSP x Multi Input DMA y Data (I2S2_SSMID2D)
SSP x Multi Input DMA y Time Slot Active (I2S2_SSMID2TSA)
SSP x Multi Input DMA y Control / Status (I2S2_SSMID3CS)
SSP x Multi Input DMA y Data (I2S2_SSMID3D)
SSP x Multi Input DMA y Time Slot Active (I2S2_SSMID3TSA)
SSP x Multi Input DMA y Control / Status (I2S2_SSMID4CS)
SSP x Multi Input DMA y Data (I2S2_SSMID4D)
SSP x Multi Input DMA y Time Slot Active (I2S2_SSMID4TSA)
SSP x Multi Input DMA y Control / Status (I2S2_SSMID5CS)
SSP x Multi Input DMA y Data (I2S2_SSMID5D)
SSP x Multi Input DMA y Time Slot Active (I2S2_SSMID5TSA)
SSP x Multi Input DMA y Control / Status (I2S2_SSMID6CS)
SSP x Multi Input DMA y Data (I2S2_SSMID6D)
SSP x Multi Input DMA y Time Slot Active (I2S2_SSMID6TSA)
SSP x Multi Input DMA y Control / Status (I2S2_SSMID7CS)
SSP x Multi Input DMA y Data (I2S2_SSMID7D)
SSP x Multi Input DMA y Time Slot Active (I2S2_SSMID7TSA)
SSP x Multi Output DMA y Control / Status (I2S2_SSMOD0CS)
SSP x Multi Output DMA y Data (I2S2_SSMOD0D)
SSP x Multi Output DMA y Time Slot Active (I2S2_SSMOD0TSA)
SSP x Multi Output DMA y Control / Status (I2S2_SSMOD1CS)
SSP x Multi Output DMA y Data (I2S2_SSMOD1D)
SSP x Multi Output DMA y Time Slot Active (I2S2_SSMOD1TSA)
SSP x Multi Output DMA y Control / Status (I2S2_SSMOD2CS)
SSP x Multi Output DMA y Data (I2S2_SSMOD2D)
SSP x Multi Output DMA y Time Slot Active (I2S2_SSMOD2TSA)
SSP x Multi Output DMA y Control / Status (I2S2_SSMOD3CS)
SSP x Multi Output DMA y Data (I2S2_SSMOD3D)
SSP x Multi Output DMA y Time Slot Active (I2S2_SSMOD3TSA)
SSP x Multi Output DMA y Control / Status (I2S2_SSMOD4CS)
SSP x Multi Output DMA y Data (I2S2_SSMOD4D)
SSP x Multi Output DMA y Time Slot Active (I2S2_SSMOD4TSA)
SSP x Multi Output DMA y Control / Status (I2S2_SSMOD5CS)
SSP x Multi Output DMA y Data (I2S2_SSMOD5D)
SSP x Multi Output DMA y Time Slot Active (I2S2_SSMOD5TSA)
SSP x Multi Output DMA y Control / Status (I2S2_SSMOD6CS)
SSP x Multi Output DMA y Data (I2S2_SSMOD6D)
SSP x Multi Output DMA y Time Slot Active (I2S2_SSMOD6TSA)
SSP x Multi Output DMA y Control / Status (I2S2_SSMOD7CS)
SSP x Multi Output DMA y Data (I2S2_SSMOD7D)
SSP x Multi Output DMA y Time Slot Active (I2S2_SSMOD7TSA)
I2S x Link Vendor Specific Control (I2S2LVSCTL)
SoundWire x Link Extended Capability (SNDW0LECAP)
SoundWire x PCM Stream Capabilities (SNDW0PCMSCAP)
SoundWire PCM Stream y Channel Count (SNDW0PCMS0CHC)
SoundWire x PCM Stream y Channel Map (SNDW0PCMS0CM)
SoundWire PCM Stream y Channel Count (SNDW0PCMS1CHC)
SoundWire x PCM Stream y Channel Map (SNDW0PCMS1CM)
SoundWire PCM Stream y Channel Count (SNDW0PCMS2CHC)
SoundWire x PCM Stream y Channel Map (SNDW0PCMS2CM)
SoundWire PCM Stream y Channel Count (SNDW0PCMS3CHC)
SoundWire x PCM Stream y Channel Map (SNDW0PCMS3CM)
SoundWire PCM Stream y Channel Count (SNDW0PCMS4CHC)
SoundWire x PCM Stream y Channel Map (SNDW0PCMS4CM)
SoundWire PCM Stream y Channel Count (SNDW0PCMS5CHC)
SoundWire x PCM Stream y Channel Map (SNDW0PCMS5CM)
SoundWire PCM Stream y Channel Count (SNDW0PCMS6CHC)
SoundWire x PCM Stream y Channel Map (SNDW0PCMS6CM)
SoundWire PCM Stream y Channel Count (SNDW0PCMS7CHC)
SoundWire x PCM Stream y Channel Map (SNDW0PCMS7CM)
SoundWire PCM Stream y Channel Count (SNDW0PCMS8CHC)
SoundWire x PCM Stream y Channel Map (SNDW0PCMS8CM)
SoundWire PCM Stream y Channel Count (SNDW0PCMS9CHC)
SoundWire x PCM Stream y Channel Map (SNDW0PCMS9CM)
SoundWire PCM Stream y Channel Count (SNDW0PCMS10CHC)
SoundWire x PCM Stream y Channel Map (SNDW0PCMS10CM)
SoundWire PCM Stream y Channel Count (SNDW0PCMS11CHC)
SoundWire x PCM Stream y Channel Map (SNDW0PCMS11CM)
SoundWire PCM Stream y Channel Count (SNDW0PCMS12CHC)
SoundWire x PCM Stream y Channel Map (SNDW0PCMS12CM)
SoundWire PCM Stream y Channel Count (SNDW0PCMS13CHC)
SoundWire x PCM Stream y Channel Map (SNDW0PCMS13CM)
SoundWire PCM Stream y Channel Count (SNDW0PCMS14CHC)
SoundWire x PCM Stream y Channel Map (SNDW0PCMS14CM)
SoundWire PCM Stream y Channel Count (SNDW0PCMS15CHC)
SoundWire x PCM Stream y Channel Map (SNDW0PCMS15CM)
MCP Config (MCP_0_Config)
MCP Control (MCP_0_Control)
MCP SSPStat (MCP_0_SSPStat)
MCP FrameShape (MCP_0_FrameShape)
MCP FrameShapeInit (MCP_0_FrameShapeInit)
MCP ConfigUpdate (MCP_0_ConfigUpdate)
MCP SSPCtrl (MCP_0_B0_SSPCtrl)
MCP SSPCtrl (MCP_0_B1_SSPCtrl)
MCP ClockCtrl (MCP_0_B0_ClockCtrl)
MCP ClockCtrl (MCP_0_B1_ClockCtrl)
MCP Stat (MCP_0_Stat)
MCP IntStat (MCP_0_IntStat)
MCP IntMask (MCP_0_IntMask)
MCP PeripheryStat (MCP_0_PeripheryStat)
MCP PeripheryIntStat0 (MCP_0_PeripheryIntStat0)
MCP PeripheryIntStat1 (MCP_0_PeripheryIntStat1)
MCP PeripheryIntMask0 (MCP_0_PeripheryIntMask0)
MCP PeripheryIntMask1 (MCP_0_PeripheryIntMask1)
MCP PortIntStat (MCP_0_PortIntStat)
MCP PDIStat (MCP_0_PDIStat)
MCP FIFOLevel (MCP_0_FIFOLevel)
MCP FIFOStat (MCP_0_FIFOStat)
DP Config (DP_0_0_B0_Config)
DP ChannelEn (DP_0_0_B0_ChannelEn)
DP SampleCtrl (DP_0_0_B0_SampleCtrl)
DP OffsetCtrl (DP_0_0_B0_OffsetCtrl)
DP HCtrl (DP_0_0_B0_HCtrl)
DP AsyncCtrl (DP_0_0_B0_AsyncCtrl)
DP Config (DP_0_0_B1_Config)
DP ChannelEn (DP_0_0_B1_ChannelEn)
DP SampleCtrl (DP_0_0_B1_SampleCtrl)
DP OffsetCtrl (DP_0_0_B1_OffsetCtrl)
DP HCtrl (DP_0_0_B1_HCtrl)
DP AsyncCtrl (DP_0_0_B1_AsyncCtrl)
DP Port Ctrl (DP_0_0_Port_Ctrl)
DP Config (DP_0_1_B0_Config)
DP ChannelEn (DP_0_1_B0_ChannelEn)
DP SampleCtrl (DP_0_1_B0_SampleCtrl)
DP OffsetCtrl (DP_0_1_B0_OffsetCtrl)
DP HCtrl (DP_0_1_B0_HCtrl)
DP AsyncCtrl (DP_0_1_B0_AsyncCtrl)
DP Config (DP_0_1_B1_Config)
DP ChannelEn (DP_0_1_B1_ChannelEn)
DP SampleCtrl (DP_0_1_B1_SampleCtrl)
DP OffsetCtrl (DP_0_1_B1_OffsetCtrl)
DP HCtrl (DP_0_1_B1_HCtrl)
DP AsyncCtrl (DP_0_1_B1_AsyncCtrl)
DP Port Ctrl (DP_0_1_Port_Ctrl)
DP Config (DP_0_2_B0_Config)
DP ChannelEn (DP_0_2_B0_ChannelEn)
DP SampleCtrl (DP_0_2_B0_SampleCtrl)
DP OffsetCtrl (DP_0_2_B0_OffsetCtrl)
DP HCtrl (DP_0_2_B0_HCtrl)
DP AsyncCtrl (DP_0_2_B0_AsyncCtrl)
DP Config (DP_0_2_B1_Config)
DP ChannelEn (DP_0_2_B1_ChannelEn)
DP SampleCtrl (DP_0_2_B1_SampleCtrl)
DP OffsetCtrl (DP_0_2_B1_OffsetCtrl)
DP HCtrl (DP_0_2_B1_HCtrl)
DP AsyncCtrl (DP_0_2_B1_AsyncCtrl)
DP Port Ctrl (DP_0_2_Port_Ctrl)
DP Config (DP_0_3_B0_Config)
DP ChannelEn (DP_0_3_B0_ChannelEn)
DP SampleCtrl (DP_0_3_B0_SampleCtrl)
DP OffsetCtrl (DP_0_3_B0_OffsetCtrl)
DP HCtrl (DP_0_3_B0_HCtrl)
DP AsyncCtrl (DP_0_3_B0_AsyncCtrl)
DP Config (DP_0_3_B1_Config)
DP ChannelEn (DP_0_3_B1_ChannelEn)
DP SampleCtrl (DP_0_3_B1_SampleCtrl)
DP OffsetCtrl (DP_0_3_B1_OffsetCtrl)
DP HCtrl (DP_0_3_B1_HCtrl)
DP AsyncCtrl (DP_0_3_B1_AsyncCtrl)
DP Port Ctrl (DP_0_3_Port_Ctrl)
DP Config (DP_0_4_B0_Config)
DP ChannelEn (DP_0_4_B0_ChannelEn)
DP SampleCtrl (DP_0_4_B0_SampleCtrl)
DP OffsetCtrl (DP_0_4_B0_OffsetCtrl)
DP HCtrl (DP_0_4_B0_HCtrl)
DP AsyncCtrl (DP_0_4_B0_AsyncCtrl)
DP Config (DP_0_4_B1_Config)
DP ChannelEn (DP_0_4_B1_ChannelEn)
DP SampleCtrl (DP_0_4_B1_SampleCtrl)
DP OffsetCtrl (DP_0_4_B1_OffsetCtrl)
DP HCtrl (DP_0_4_B1_HCtrl)
DP AsyncCtrl (DP_0_4_B1_AsyncCtrl)
DP Port Ctrl (DP_0_4_Port_Ctrl)
DP Config (DP_0_5_B0_Config)
DP ChannelEn (DP_0_5_B0_ChannelEn)
DP SampleCtrl (DP_0_5_B0_SampleCtrl)
DP OffsetCtrl (DP_0_5_B0_OffsetCtrl)
DP HCtrl (DP_0_5_B0_HCtrl)
DP AsyncCtrl (DP_0_5_B0_AsyncCtrl)
DP Config (DP_0_5_B1_Config)
DP ChannelEn (DP_0_5_B1_ChannelEn)
DP SampleCtrl (DP_0_5_B1_SampleCtrl)
DP OffsetCtrl (DP_0_5_B1_OffsetCtrl)
DP HCtrl (DP_0_5_B1_HCtrl)
DP AsyncCtrl (DP_0_5_B1_AsyncCtrl)
DP Port Ctrl (DP_0_5_Port_Ctrl)
DP Config (DP_0_6_B0_Config)
DP ChannelEn (DP_0_6_B0_ChannelEn)
DP SampleCtrl (DP_0_6_B0_SampleCtrl)
DP OffsetCtrl (DP_0_6_B0_OffsetCtrl)
DP HCtrl (DP_0_6_B0_HCtrl)
DP AsyncCtrl (DP_0_6_B0_AsyncCtrl)
DP Config (DP_0_6_B1_Config)
DP ChannelEn (DP_0_6_B1_ChannelEn)
DP SampleCtrl (DP_0_6_B1_SampleCtrl)
DP OffsetCtrl (DP_0_6_B1_OffsetCtrl)
DP HCtrl (DP_0_6_B1_HCtrl)
DP AsyncCtrl (DP_0_6_B1_AsyncCtrl)
DP Port Ctrl (DP_0_6_Port_Ctrl)
DP Config (DP_0_7_B0_Config)
DP ChannelEn (DP_0_7_B0_ChannelEn)
DP SampleCtrl (DP_0_7_B0_SampleCtrl)
DP OffsetCtrl (DP_0_7_B0_OffsetCtrl)
DP HCtrl (DP_0_7_B0_HCtrl)
DP AsyncCtrl (DP_0_7_B0_AsyncCtrl)
DP Config (DP_0_7_B1_Config)
DP ChannelEn (DP_0_7_B1_ChannelEn)
DP SampleCtrl (DP_0_7_B1_SampleCtrl)
DP OffsetCtrl (DP_0_7_B1_OffsetCtrl)
DP HCtrl (DP_0_7_B1_HCtrl)
DP AsyncCtrl (DP_0_7_B1_AsyncCtrl)
DP Port Ctrl (DP_0_7_Port_Ctrl)
DP Config (DP_0_8_B0_Config)
DP ChannelEn (DP_0_8_B0_ChannelEn)
DP SampleCtrl (DP_0_8_B0_SampleCtrl)
DP OffsetCtrl (DP_0_8_B0_OffsetCtrl)
DP HCtrl (DP_0_8_B0_HCtrl)
DP AsyncCtrl (DP_0_8_B0_AsyncCtrl)
DP Config (DP_0_8_B1_Config)
DP ChannelEn (DP_0_8_B1_ChannelEn)
DP SampleCtrl (DP_0_8_B1_SampleCtrl)
DP OffsetCtrl (DP_0_8_B1_OffsetCtrl)
DP HCtrl (DP_0_8_B1_HCtrl)
DP AsyncCtrl (DP_0_8_B1_AsyncCtrl)
DP Port Ctrl (DP_0_8_Port_Ctrl)
DP Config (DP_0_9_B0_Config)
DP ChannelEn (DP_0_9_B0_ChannelEn)
DP SampleCtrl (DP_0_9_B0_SampleCtrl)
DP OffsetCtrl (DP_0_9_B0_OffsetCtrl)
DP HCtrl (DP_0_9_B0_HCtrl)
DP AsyncCtrl (DP_0_9_B0_AsyncCtrl)
DP Config (DP_0_9_B1_Config)
DP ChannelEn (DP_0_9_B1_ChannelEn)
DP SampleCtrl (DP_0_9_B1_SampleCtrl)
DP OffsetCtrl (DP_0_9_B1_OffsetCtrl)
DP HCtrl (DP_0_9_B1_HCtrl)
DP AsyncCtrl (DP_0_9_B1_AsyncCtrl)
DP Port Ctrl (DP_0_9_Port_Ctrl)
DP Config (DP_0_10_B0_Config)
DP ChannelEn (DP_0_10_B0_ChannelEn)
DP SampleCtrl (DP_0_10_B0_SampleCtrl)
DP OffsetCtrl (DP_0_10_B0_OffsetCtrl)
DP HCtrl (DP_0_10_B0_HCtrl)
DP AsyncCtrl (DP_0_10_B0_AsyncCtrl)
DP Config (DP_0_10_B1_Config)
DP ChannelEn (DP_0_10_B1_ChannelEn)
DP SampleCtrl (DP_0_10_B1_SampleCtrl)
DP OffsetCtrl (DP_0_10_B1_OffsetCtrl)
DP HCtrl (DP_0_10_B1_HCtrl)
DP AsyncCtrl (DP_0_10_B1_AsyncCtrl)
DP Port Ctrl (DP_0_10_Port_Ctrl)
DP Config (DP_0_11_B0_Config)
DP ChannelEn (DP_0_11_B0_ChannelEn)
DP SampleCtrl (DP_0_11_B0_SampleCtrl)
DP OffsetCtrl (DP_0_11_B0_OffsetCtrl)
DP HCtrl (DP_0_11_B0_HCtrl)
DP AsyncCtrl (DP_0_11_B0_AsyncCtrl)
DP Config (DP_0_11_B1_Config)
DP ChannelEn (DP_0_11_B1_ChannelEn)
DP SampleCtrl (DP_0_11_B1_SampleCtrl)
DP OffsetCtrl (DP_0_11_B1_OffsetCtrl)
DP HCtrl (DP_0_11_B1_HCtrl)
DP AsyncCtrl (DP_0_11_B1_AsyncCtrl)
DP Port Ctrl (DP_0_11_Port_Ctrl)
DP Config (DP_0_12_B0_Config)
DP ChannelEn (DP_0_12_B0_ChannelEn)
DP SampleCtrl (DP_0_12_B0_SampleCtrl)
DP OffsetCtrl (DP_0_12_B0_OffsetCtrl)
DP HCtrl (DP_0_12_B0_HCtrl)
DP AsyncCtrl (DP_0_12_B0_AsyncCtrl)
DP Config (DP_0_12_B1_Config)
DP ChannelEn (DP_0_12_B1_ChannelEn)
DP SampleCtrl (DP_0_12_B1_SampleCtrl)
DP OffsetCtrl (DP_0_12_B1_OffsetCtrl)
DP HCtrl (DP_0_12_B1_HCtrl)
DP AsyncCtrl (DP_0_12_B1_AsyncCtrl)
DP Port Ctrl (DP_0_12_Port_Ctrl)
DP Config (DP_0_13_B0_Config)
DP ChannelEn (DP_0_13_B0_ChannelEn)
DP SampleCtrl (DP_0_13_B0_SampleCtrl)
DP OffsetCtrl (DP_0_13_B0_OffsetCtrl)
DP HCtrl (DP_0_13_B0_HCtrl)
DP AsyncCtrl (DP_0_13_B0_AsyncCtrl)
DP Config (DP_0_13_B1_Config)
DP ChannelEn (DP_0_13_B1_ChannelEn)
DP SampleCtrl (DP_0_13_B1_SampleCtrl)
DP OffsetCtrl (DP_0_13_B1_OffsetCtrl)
DP HCtrl (DP_0_13_B1_HCtrl)
DP AsyncCtrl (DP_0_13_B1_AsyncCtrl)
DP Port Ctrl (DP_0_13_Port_Ctrl)
DP Config (DP_0_14_B0_Config)
DP ChannelEn (DP_0_14_B0_ChannelEn)
DP SampleCtrl (DP_0_14_B0_SampleCtrl)
DP OffsetCtrl (DP_0_14_B0_OffsetCtrl)
DP HCtrl (DP_0_14_B0_HCtrl)
DP AsyncCtrl (DP_0_14_B0_AsyncCtrl)
DP Config (DP_0_14_B1_Config)
DP ChannelEn (DP_0_14_B1_ChannelEn)
DP SampleCtrl (DP_0_14_B1_SampleCtrl)
DP OffsetCtrl (DP_0_14_B1_OffsetCtrl)
DP HCtrl (DP_0_14_B1_HCtrl)
DP AsyncCtrl (DP_0_14_B1_AsyncCtrl)
DP Port Ctrl (DP_0_14_Port_Ctrl)
PDI Config (PDI_0_0_Config)
PDI Config (PDI_0_1_Config)
PDI Config (PDI_0_2_Config)
PDI Config (PDI_0_3_Config)
PDI Config (PDI_0_4_Config)
PDI Config (PDI_0_5_Config)
PDI Config (PDI_0_6_Config)
PDI Config (PDI_0_7_Config)
PDI Config (PDI_0_8_Config)
PDI Config (PDI_0_9_Config)
PDI Config (PDI_0_10_Config)
PDI Config (PDI_0_11_Config)
PDI Config (PDI_0_12_Config)
PDI Config (PDI_0_13_Config)
PDI Config (PDI_0_14_Config)
PDI Config (PDI_0_15_Config)
IP MCP Config (IP_MCP_0_Config)
IP MCP Control (IP_MCP_0_Control)
IP MCP CmdCtrl (IP_MCP_0_CmdCtrl)
IP MCP PHYCtrl (IP_MCP_0_PHYCtrl)
IP MCP B0_ClockCtrl (IP_MCP_0_B0_ClockCtrl)
IP MCP Stat (IP_MCP_0_Stat)
IP MCP IntSet (IP_MCP_0_IntSet)
IP MCP Command (IP_MCP_0_Command)
SoundWire x Link Vendor Specific Control (SNDW0LVSCTL)
SoundWire x Wake Enable (SNDW0WAKEEN)
SoundWire x Wake Status (SNDW0WAKESTS)
SoundWire x I/O Control (SNDW0IOCTL)
SoundWire x AC Timing Control (SNDW0ACTMCTL)
SoundWire x Microphone Privacy Control & Status (SNDW0PVCCS)
SoundWire x Link Extended Capability (SNDW1LECAP)
SoundWire x PCM Stream Capabilities (SNDW1PCMSCAP)
SoundWire PCM Stream y Channel Count (SNDW1PCMS0CHC)
SoundWire x PCM Stream y Channel Map (SNDW1PCMS0CM)
SoundWire PCM Stream y Channel Count (SNDW1PCMS1CHC)
SoundWire x PCM Stream y Channel Map (SNDW1PCMS1CM)
SoundWire PCM Stream y Channel Count (SNDW1PCMS2CHC)
SoundWire x PCM Stream y Channel Map (SNDW1PCMS2CM)
SoundWire PCM Stream y Channel Count (SNDW1PCMS3CHC)
SoundWire x PCM Stream y Channel Map (SNDW1PCMS3CM)
SoundWire PCM Stream y Channel Count (SNDW1PCMS4CHC)
SoundWire x PCM Stream y Channel Map (SNDW1PCMS4CM)
SoundWire PCM Stream y Channel Count (SNDW1PCMS5CHC)
SoundWire x PCM Stream y Channel Map (SNDW1PCMS5CM)
SoundWire PCM Stream y Channel Count (SNDW1PCMS6CHC)
SoundWire x PCM Stream y Channel Map (SNDW1PCMS6CM)
SoundWire PCM Stream y Channel Count (SNDW1PCMS7CHC)
SoundWire x PCM Stream y Channel Map (SNDW1PCMS7CM)
SoundWire PCM Stream y Channel Count (SNDW1PCMS8CHC)
SoundWire x PCM Stream y Channel Map (SNDW1PCMS8CM)
SoundWire PCM Stream y Channel Count (SNDW1PCMS9CHC)
SoundWire x PCM Stream y Channel Map (SNDW1PCMS9CM)
SoundWire PCM Stream y Channel Count (SNDW1PCMS10CHC)
SoundWire x PCM Stream y Channel Map (SNDW1PCMS10CM)
SoundWire PCM Stream y Channel Count (SNDW1PCMS11CHC)
SoundWire x PCM Stream y Channel Map (SNDW1PCMS11CM)
SoundWire PCM Stream y Channel Count (SNDW1PCMS12CHC)
SoundWire x PCM Stream y Channel Map (SNDW1PCMS12CM)
SoundWire PCM Stream y Channel Count (SNDW1PCMS13CHC)
SoundWire x PCM Stream y Channel Map (SNDW1PCMS13CM)
SoundWire PCM Stream y Channel Count (SNDW1PCMS14CHC)
SoundWire x PCM Stream y Channel Map (SNDW1PCMS14CM)
SoundWire PCM Stream y Channel Count (SNDW1PCMS15CHC)
SoundWire x PCM Stream y Channel Map (SNDW1PCMS15CM)
MCP Config (MCP_1_Config)
MCP Control (MCP_1_Control)
MCP SSPStat (MCP_1_SSPStat)
MCP FrameShape (MCP_1_FrameShape)
MCP FrameShapeInit (MCP_1_FrameShapeInit)
MCP ConfigUpdate (MCP_1_ConfigUpdate)
MCP SSPCtrl (MCP_1_B0_SSPCtrl)
MCP SSPCtrl (MCP_1_B1_SSPCtrl)
MCP ClockCtrl (MCP_1_B0_ClockCtrl)
MCP ClockCtrl (MCP_1_B1_ClockCtrl)
MCP Stat (MCP_1_Stat)
MCP IntStat (MCP_1_IntStat)
MCP IntMask (MCP_1_IntMask)
MCP PeripheryStat (MCP_1_PeripheryStat)
MCP PeripheryIntStat0 (MCP_1_PeripheryIntStat0)
MCP PeripheryIntStat1 (MCP_1_PeripheryIntStat1)
MCP PeripheryIntMask0 (MCP_1_PeripheryIntMask0)
MCP PeripheryIntMask1 (MCP_1_PeripheryIntMask1)
MCP PortIntStat (MCP_1_PortIntStat)
MCP PDIStat (MCP_1_PDIStat)
MCP FIFOLevel (MCP_1_FIFOLevel)
MCP FIFOStat (MCP_1_FIFOStat)
DP Config (DP_1_0_B0_Config)
DP ChannelEn (DP_1_0_B0_ChannelEn)
DP SampleCtrl (DP_1_0_B0_SampleCtrl)
DP OffsetCtrl (DP_1_0_B0_OffsetCtrl)
DP HCtrl (DP_1_0_B0_HCtrl)
DP AsyncCtrl (DP_1_0_B0_AsyncCtrl)
DP Config (DP_1_0_B1_Config)
DP ChannelEn (DP_1_0_B1_ChannelEn)
DP SampleCtrl (DP_1_0_B1_SampleCtrl)
DP OffsetCtrl (DP_1_0_B1_OffsetCtrl)
DP HCtrl (DP_1_0_B1_HCtrl)
DP AsyncCtrl (DP_1_0_B1_AsyncCtrl)
DP Port Ctrl (DP_1_0_Port_Ctrl)
DP Config (DP_1_1_B0_Config)
DP ChannelEn (DP_1_1_B0_ChannelEn)
DP SampleCtrl (DP_1_1_B0_SampleCtrl)
DP OffsetCtrl (DP_1_1_B0_OffsetCtrl)
DP HCtrl (DP_1_1_B0_HCtrl)
DP AsyncCtrl (DP_1_1_B0_AsyncCtrl)
DP Config (DP_1_1_B1_Config)
DP ChannelEn (DP_1_1_B1_ChannelEn)
DP SampleCtrl (DP_1_1_B1_SampleCtrl)
DP OffsetCtrl (DP_1_1_B1_OffsetCtrl)
DP HCtrl (DP_1_1_B1_HCtrl)
DP AsyncCtrl (DP_1_1_B1_AsyncCtrl)
DP Port Ctrl (DP_1_1_Port_Ctrl)
DP Config (DP_1_2_B0_Config)
DP ChannelEn (DP_1_2_B0_ChannelEn)
DP SampleCtrl (DP_1_2_B0_SampleCtrl)
DP OffsetCtrl (DP_1_2_B0_OffsetCtrl)
DP HCtrl (DP_1_2_B0_HCtrl)
DP AsyncCtrl (DP_1_2_B0_AsyncCtrl)
DP Config (DP_1_2_B1_Config)
DP ChannelEn (DP_1_2_B1_ChannelEn)
DP SampleCtrl (DP_1_2_B1_SampleCtrl)
DP OffsetCtrl (DP_1_2_B1_OffsetCtrl)
DP HCtrl (DP_1_2_B1_HCtrl)
DP AsyncCtrl (DP_1_2_B1_AsyncCtrl)
DP Port Ctrl (DP_1_2_Port_Ctrl)
DP Config (DP_1_3_B0_Config)
DP ChannelEn (DP_1_3_B0_ChannelEn)
DP SampleCtrl (DP_1_3_B0_SampleCtrl)
DP OffsetCtrl (DP_1_3_B0_OffsetCtrl)
DP HCtrl (DP_1_3_B0_HCtrl)
DP AsyncCtrl (DP_1_3_B0_AsyncCtrl)
DP Config (DP_1_3_B1_Config)
DP ChannelEn (DP_1_3_B1_ChannelEn)
DP SampleCtrl (DP_1_3_B1_SampleCtrl)
DP OffsetCtrl (DP_1_3_B1_OffsetCtrl)
DP HCtrl (DP_1_3_B1_HCtrl)
DP AsyncCtrl (DP_1_3_B1_AsyncCtrl)
DP Port Ctrl (DP_1_3_Port_Ctrl)
DP Config (DP_1_4_B0_Config)
DP ChannelEn (DP_1_4_B0_ChannelEn)
DP SampleCtrl (DP_1_4_B0_SampleCtrl)
DP OffsetCtrl (DP_1_4_B0_OffsetCtrl)
DP HCtrl (DP_1_4_B0_HCtrl)
DP AsyncCtrl (DP_1_4_B0_AsyncCtrl)
DP Config (DP_1_4_B1_Config)
DP ChannelEn (DP_1_4_B1_ChannelEn)
DP SampleCtrl (DP_1_4_B1_SampleCtrl)
DP OffsetCtrl (DP_1_4_B1_OffsetCtrl)
DP HCtrl (DP_1_4_B1_HCtrl)
DP AsyncCtrl (DP_1_4_B1_AsyncCtrl)
DP Port Ctrl (DP_1_4_Port_Ctrl)
DP Config (DP_1_5_B0_Config)
DP ChannelEn (DP_1_5_B0_ChannelEn)
DP SampleCtrl (DP_1_5_B0_SampleCtrl)
DP OffsetCtrl (DP_1_5_B0_OffsetCtrl)
DP HCtrl (DP_1_5_B0_HCtrl)
DP AsyncCtrl (DP_1_5_B0_AsyncCtrl)
DP Config (DP_1_5_B1_Config)
DP ChannelEn (DP_1_5_B1_ChannelEn)
DP SampleCtrl (DP_1_5_B1_SampleCtrl)
DP OffsetCtrl (DP_1_5_B1_OffsetCtrl)
DP HCtrl (DP_1_5_B1_HCtrl)
DP AsyncCtrl (DP_1_5_B1_AsyncCtrl)
DP Port Ctrl (DP_1_5_Port_Ctrl)
DP Config (DP_1_6_B0_Config)
DP ChannelEn (DP_1_6_B0_ChannelEn)
DP SampleCtrl (DP_1_6_B0_SampleCtrl)
DP OffsetCtrl (DP_1_6_B0_OffsetCtrl)
DP HCtrl (DP_1_6_B0_HCtrl)
DP AsyncCtrl (DP_1_6_B0_AsyncCtrl)
DP Config (DP_1_6_B1_Config)
DP ChannelEn (DP_1_6_B1_ChannelEn)
DP SampleCtrl (DP_1_6_B1_SampleCtrl)
DP OffsetCtrl (DP_1_6_B1_OffsetCtrl)
DP HCtrl (DP_1_6_B1_HCtrl)
DP AsyncCtrl (DP_1_6_B1_AsyncCtrl)
DP Port Ctrl (DP_1_6_Port_Ctrl)
DP Config (DP_1_7_B0_Config)
DP ChannelEn (DP_1_7_B0_ChannelEn)
DP SampleCtrl (DP_1_7_B0_SampleCtrl)
DP OffsetCtrl (DP_1_7_B0_OffsetCtrl)
DP HCtrl (DP_1_7_B0_HCtrl)
DP AsyncCtrl (DP_1_7_B0_AsyncCtrl)
DP Config (DP_1_7_B1_Config)
DP ChannelEn (DP_1_7_B1_ChannelEn)
DP SampleCtrl (DP_1_7_B1_SampleCtrl)
DP OffsetCtrl (DP_1_7_B1_OffsetCtrl)
DP HCtrl (DP_1_7_B1_HCtrl)
DP AsyncCtrl (DP_1_7_B1_AsyncCtrl)
DP Port Ctrl (DP_1_7_Port_Ctrl)
DP Config (DP_1_8_B0_Config)
DP ChannelEn (DP_1_8_B0_ChannelEn)
DP SampleCtrl (DP_1_8_B0_SampleCtrl)
DP OffsetCtrl (DP_1_8_B0_OffsetCtrl)
DP HCtrl (DP_1_8_B0_HCtrl)
DP AsyncCtrl (DP_1_8_B0_AsyncCtrl)
DP Config (DP_1_8_B1_Config)
DP ChannelEn (DP_1_8_B1_ChannelEn)
DP SampleCtrl (DP_1_8_B1_SampleCtrl)
DP OffsetCtrl (DP_1_8_B1_OffsetCtrl)
DP HCtrl (DP_1_8_B1_HCtrl)
DP AsyncCtrl (DP_1_8_B1_AsyncCtrl)
DP Port Ctrl (DP_1_8_Port_Ctrl)
DP Config (DP_1_9_B0_Config)
DP ChannelEn (DP_1_9_B0_ChannelEn)
DP SampleCtrl (DP_1_9_B0_SampleCtrl)
DP OffsetCtrl (DP_1_9_B0_OffsetCtrl)
DP HCtrl (DP_1_9_B0_HCtrl)
DP AsyncCtrl (DP_1_9_B0_AsyncCtrl)
DP Config (DP_1_9_B1_Config)
DP ChannelEn (DP_1_9_B1_ChannelEn)
DP SampleCtrl (DP_1_9_B1_SampleCtrl)
DP OffsetCtrl (DP_1_9_B1_OffsetCtrl)
DP HCtrl (DP_1_9_B1_HCtrl)
DP AsyncCtrl (DP_1_9_B1_AsyncCtrl)
DP Port Ctrl (DP_1_9_Port_Ctrl)
DP Config (DP_1_10_B0_Config)
DP ChannelEn (DP_1_10_B0_ChannelEn)
DP SampleCtrl (DP_1_10_B0_SampleCtrl)
DP OffsetCtrl (DP_1_10_B0_OffsetCtrl)
DP HCtrl (DP_1_10_B0_HCtrl)
DP AsyncCtrl (DP_1_10_B0_AsyncCtrl)
DP Config (DP_1_10_B1_Config)
DP ChannelEn (DP_1_10_B1_ChannelEn)
DP SampleCtrl (DP_1_10_B1_SampleCtrl)
DP OffsetCtrl (DP_1_10_B1_OffsetCtrl)
DP HCtrl (DP_1_10_B1_HCtrl)
DP AsyncCtrl (DP_1_10_B1_AsyncCtrl)
DP Port Ctrl (DP_1_10_Port_Ctrl)
DP Config (DP_1_11_B0_Config)
DP ChannelEn (DP_1_11_B0_ChannelEn)
DP SampleCtrl (DP_1_11_B0_SampleCtrl)
DP OffsetCtrl (DP_1_11_B0_OffsetCtrl)
DP HCtrl (DP_1_11_B0_HCtrl)
DP AsyncCtrl (DP_1_11_B0_AsyncCtrl)
DP Config (DP_1_11_B1_Config)
DP ChannelEn (DP_1_11_B1_ChannelEn)
DP SampleCtrl (DP_1_11_B1_SampleCtrl)
DP OffsetCtrl (DP_1_11_B1_OffsetCtrl)
DP HCtrl (DP_1_11_B1_HCtrl)
DP AsyncCtrl (DP_1_11_B1_AsyncCtrl)
DP Port Ctrl (DP_1_11_Port_Ctrl)
DP Config (DP_1_12_B0_Config)
DP ChannelEn (DP_1_12_B0_ChannelEn)
DP SampleCtrl (DP_1_12_B0_SampleCtrl)
DP OffsetCtrl (DP_1_12_B0_OffsetCtrl)
DP HCtrl (DP_1_12_B0_HCtrl)
DP AsyncCtrl (DP_1_12_B0_AsyncCtrl)
DP Config (DP_1_12_B1_Config)
DP ChannelEn (DP_1_12_B1_ChannelEn)
DP SampleCtrl (DP_1_12_B1_SampleCtrl)
DP OffsetCtrl (DP_1_12_B1_OffsetCtrl)
DP HCtrl (DP_1_12_B1_HCtrl)
DP AsyncCtrl (DP_1_12_B1_AsyncCtrl)
DP Port Ctrl (DP_1_12_Port_Ctrl)
DP Config (DP_1_13_B0_Config)
DP ChannelEn (DP_1_13_B0_ChannelEn)
DP SampleCtrl (DP_1_13_B0_SampleCtrl)
DP OffsetCtrl (DP_1_13_B0_OffsetCtrl)
DP HCtrl (DP_1_13_B0_HCtrl)
DP AsyncCtrl (DP_1_13_B0_AsyncCtrl)
DP Config (DP_1_13_B1_Config)
DP ChannelEn (DP_1_13_B1_ChannelEn)
DP SampleCtrl (DP_1_13_B1_SampleCtrl)
DP OffsetCtrl (DP_1_13_B1_OffsetCtrl)
DP HCtrl (DP_1_13_B1_HCtrl)
DP AsyncCtrl (DP_1_13_B1_AsyncCtrl)
DP Port Ctrl (DP_1_13_Port_Ctrl)
DP Config (DP_1_14_B0_Config)
DP ChannelEn (DP_1_14_B0_ChannelEn)
DP SampleCtrl (DP_1_14_B0_SampleCtrl)
DP OffsetCtrl (DP_1_14_B0_OffsetCtrl)
DP HCtrl (DP_1_14_B0_HCtrl)
DP AsyncCtrl (DP_1_14_B0_AsyncCtrl)
DP Config (DP_1_14_B1_Config)
DP ChannelEn (DP_1_14_B1_ChannelEn)
DP SampleCtrl (DP_1_14_B1_SampleCtrl)
DP OffsetCtrl (DP_1_14_B1_OffsetCtrl)
DP HCtrl (DP_1_14_B1_HCtrl)
DP AsyncCtrl (DP_1_14_B1_AsyncCtrl)
DP Port Ctrl (DP_1_14_Port_Ctrl)
PDI Config (PDI_1_0_Config)
PDI Config (PDI_1_1_Config)
PDI Config (PDI_1_2_Config)
PDI Config (PDI_1_3_Config)
PDI Config (PDI_1_4_Config)
PDI Config (PDI_1_5_Config)
PDI Config (PDI_1_6_Config)
PDI Config (PDI_1_7_Config)
PDI Config (PDI_1_8_Config)
PDI Config (PDI_1_9_Config)
PDI Config (PDI_1_10_Config)
PDI Config (PDI_1_11_Config)
PDI Config (PDI_1_12_Config)
PDI Config (PDI_1_13_Config)
PDI Config (PDI_1_14_Config)
PDI Config (PDI_1_15_Config)
IP MCP Config (IP_MCP_1_Config)
IP MCP Control (IP_MCP_1_Control)
IP MCP CmdCtrl (IP_MCP_1_CmdCtrl)
IP MCP PHYCtrl (IP_MCP_1_PHYCtrl)
IP MCP B0_ClockCtrl (IP_MCP_1_B0_ClockCtrl)
IP MCP Stat (IP_MCP_1_Stat)
IP MCP IntSet (IP_MCP_1_IntSet)
IP MCP Command (IP_MCP_1_Command)
SoundWire x Link Vendor Specific Control (SNDW1LVSCTL)
SoundWire x Wake Enable (SNDW1WAKEEN)
SoundWire x Wake Status (SNDW1WAKESTS)
SoundWire x I/O Control (SNDW1IOCTL)
SoundWire x AC Timing Control (SNDW1ACTMCTL)
SoundWire x Microphone Privacy Control & Status (SNDW1PVCCS)
SoundWire x Link Extended Capability (SNDW2LECAP)
SoundWire x PCM Stream Capabilities (SNDW2PCMSCAP)
SoundWire PCM Stream y Channel Count (SNDW2PCMS0CHC)
SoundWire x PCM Stream y Channel Map (SNDW2PCMS0CM)
SoundWire PCM Stream y Channel Count (SNDW2PCMS1CHC)
SoundWire x PCM Stream y Channel Map (SNDW2PCMS1CM)
SoundWire PCM Stream y Channel Count (SNDW2PCMS2CHC)
SoundWire x PCM Stream y Channel Map (SNDW2PCMS2CM)
SoundWire PCM Stream y Channel Count (SNDW2PCMS3CHC)
SoundWire x PCM Stream y Channel Map (SNDW2PCMS3CM)
SoundWire PCM Stream y Channel Count (SNDW2PCMS4CHC)
SoundWire x PCM Stream y Channel Map (SNDW2PCMS4CM)
SoundWire PCM Stream y Channel Count (SNDW2PCMS5CHC)
SoundWire x PCM Stream y Channel Map (SNDW2PCMS5CM)
SoundWire PCM Stream y Channel Count (SNDW2PCMS6CHC)
SoundWire x PCM Stream y Channel Map (SNDW2PCMS6CM)
SoundWire PCM Stream y Channel Count (SNDW2PCMS7CHC)
SoundWire x PCM Stream y Channel Map (SNDW2PCMS7CM)
SoundWire PCM Stream y Channel Count (SNDW2PCMS8CHC)
SoundWire x PCM Stream y Channel Map (SNDW2PCMS8CM)
SoundWire PCM Stream y Channel Count (SNDW2PCMS9CHC)
SoundWire x PCM Stream y Channel Map (SNDW2PCMS9CM)
SoundWire PCM Stream y Channel Count (SNDW2PCMS10CHC)
SoundWire x PCM Stream y Channel Map (SNDW2PCMS10CM)
SoundWire PCM Stream y Channel Count (SNDW2PCMS11CHC)
SoundWire x PCM Stream y Channel Map (SNDW2PCMS11CM)
SoundWire PCM Stream y Channel Count (SNDW2PCMS12CHC)
SoundWire x PCM Stream y Channel Map (SNDW2PCMS12CM)
SoundWire PCM Stream y Channel Count (SNDW2PCMS13CHC)
SoundWire x PCM Stream y Channel Map (SNDW2PCMS13CM)
SoundWire PCM Stream y Channel Count (SNDW2PCMS14CHC)
SoundWire x PCM Stream y Channel Map (SNDW2PCMS14CM)
SoundWire PCM Stream y Channel Count (SNDW2PCMS15CHC)
SoundWire x PCM Stream y Channel Map (SNDW2PCMS15CM)
MCP Config (MCP_2_Config)
MCP Control (MCP_2_Control)
MCP SSPStat (MCP_2_SSPStat)
MCP FrameShape (MCP_2_FrameShape)
MCP FrameShapeInit (MCP_2_FrameShapeInit)
MCP ConfigUpdate (MCP_2_ConfigUpdate)
MCP SSPCtrl (MCP_2_B0_SSPCtrl)
MCP SSPCtrl (MCP_2_B1_SSPCtrl)
MCP ClockCtrl (MCP_2_B0_ClockCtrl)
MCP ClockCtrl (MCP_2_B1_ClockCtrl)
MCP Stat (MCP_2_Stat)
MCP IntStat (MCP_2_IntStat)
MCP IntMask (MCP_2_IntMask)
MCP PeripheryStat (MCP_2_PeripheryStat)
MCP PeripheryIntStat0 (MCP_2_PeripheryIntStat0)
MCP PeripheryIntStat1 (MCP_2_PeripheryIntStat1)
MCP PeripheryIntMask0 (MCP_2_PeripheryIntMask0)
MCP PeripheryIntMask1 (MCP_2_PeripheryIntMask1)
MCP PortIntStat (MCP_2_PortIntStat)
MCP PDIStat (MCP_2_PDIStat)
MCP FIFOLevel (MCP_2_FIFOLevel)
MCP FIFOStat (MCP_2_FIFOStat)
DP Config (DP_2_0_B0_Config)
DP ChannelEn (DP_2_0_B0_ChannelEn)
DP SampleCtrl (DP_2_0_B0_SampleCtrl)
DP OffsetCtrl (DP_2_0_B0_OffsetCtrl)
DP HCtrl (DP_2_0_B0_HCtrl)
DP AsyncCtrl (DP_2_0_B0_AsyncCtrl)
DP Config (DP_2_0_B1_Config)
DP ChannelEn (DP_2_0_B1_ChannelEn)
DP SampleCtrl (DP_2_0_B1_SampleCtrl)
DP OffsetCtrl (DP_2_0_B1_OffsetCtrl)
DP HCtrl (DP_2_0_B1_HCtrl)
DP AsyncCtrl (DP_2_0_B1_AsyncCtrl)
DP Port Ctrl (DP_2_0_Port_Ctrl)
DP Config (DP_2_1_B0_Config)
DP ChannelEn (DP_2_1_B0_ChannelEn)
DP SampleCtrl (DP_2_1_B0_SampleCtrl)
DP OffsetCtrl (DP_2_1_B0_OffsetCtrl)
DP HCtrl (DP_2_1_B0_HCtrl)
DP AsyncCtrl (DP_2_1_B0_AsyncCtrl)
DP Config (DP_2_1_B1_Config)
DP ChannelEn (DP_2_1_B1_ChannelEn)
DP SampleCtrl (DP_2_1_B1_SampleCtrl)
DP OffsetCtrl (DP_2_1_B1_OffsetCtrl)
DP HCtrl (DP_2_1_B1_HCtrl)
DP AsyncCtrl (DP_2_1_B1_AsyncCtrl)
DP Port Ctrl (DP_2_1_Port_Ctrl)
DP Config (DP_2_2_B0_Config)
DP ChannelEn (DP_2_2_B0_ChannelEn)
DP SampleCtrl (DP_2_2_B0_SampleCtrl)
DP OffsetCtrl (DP_2_2_B0_OffsetCtrl)
DP HCtrl (DP_2_2_B0_HCtrl)
DP AsyncCtrl (DP_2_2_B0_AsyncCtrl)
DP Config (DP_2_2_B1_Config)
DP ChannelEn (DP_2_2_B1_ChannelEn)
DP SampleCtrl (DP_2_2_B1_SampleCtrl)
DP OffsetCtrl (DP_2_2_B1_OffsetCtrl)
DP HCtrl (DP_2_2_B1_HCtrl)
DP AsyncCtrl (DP_2_2_B1_AsyncCtrl)
DP Port Ctrl (DP_2_2_Port_Ctrl)
DP Config (DP_2_3_B0_Config)
DP ChannelEn (DP_2_3_B0_ChannelEn)
DP SampleCtrl (DP_2_3_B0_SampleCtrl)
DP OffsetCtrl (DP_2_3_B0_OffsetCtrl)
DP HCtrl (DP_2_3_B0_HCtrl)
DP AsyncCtrl (DP_2_3_B0_AsyncCtrl)
DP Config (DP_2_3_B1_Config)
DP ChannelEn (DP_2_3_B1_ChannelEn)
DP SampleCtrl (DP_2_3_B1_SampleCtrl)
DP OffsetCtrl (DP_2_3_B1_OffsetCtrl)
DP HCtrl (DP_2_3_B1_HCtrl)
DP AsyncCtrl (DP_2_3_B1_AsyncCtrl)
DP Port Ctrl (DP_2_3_Port_Ctrl)
DP Config (DP_2_4_B0_Config)
DP ChannelEn (DP_2_4_B0_ChannelEn)
DP SampleCtrl (DP_2_4_B0_SampleCtrl)
DP OffsetCtrl (DP_2_4_B0_OffsetCtrl)
DP HCtrl (DP_2_4_B0_HCtrl)
DP AsyncCtrl (DP_2_4_B0_AsyncCtrl)
DP Config (DP_2_4_B1_Config)
DP ChannelEn (DP_2_4_B1_ChannelEn)
DP SampleCtrl (DP_2_4_B1_SampleCtrl)
DP OffsetCtrl (DP_2_4_B1_OffsetCtrl)
DP HCtrl (DP_2_4_B1_HCtrl)
DP AsyncCtrl (DP_2_4_B1_AsyncCtrl)
DP Port Ctrl (DP_2_4_Port_Ctrl)
DP Config (DP_2_5_B0_Config)
DP ChannelEn (DP_2_5_B0_ChannelEn)
DP SampleCtrl (DP_2_5_B0_SampleCtrl)
DP OffsetCtrl (DP_2_5_B0_OffsetCtrl)
DP HCtrl (DP_2_5_B0_HCtrl)
DP AsyncCtrl (DP_2_5_B0_AsyncCtrl)
DP Config (DP_2_5_B1_Config)
DP ChannelEn (DP_2_5_B1_ChannelEn)
DP SampleCtrl (DP_2_5_B1_SampleCtrl)
DP OffsetCtrl (DP_2_5_B1_OffsetCtrl)
DP HCtrl (DP_2_5_B1_HCtrl)
DP AsyncCtrl (DP_2_5_B1_AsyncCtrl)
DP Port Ctrl (DP_2_5_Port_Ctrl)
DP Config (DP_2_6_B0_Config)
DP ChannelEn (DP_2_6_B0_ChannelEn)
DP SampleCtrl (DP_2_6_B0_SampleCtrl)
DP OffsetCtrl (DP_2_6_B0_OffsetCtrl)
DP HCtrl (DP_2_6_B0_HCtrl)
DP AsyncCtrl (DP_2_6_B0_AsyncCtrl)
DP Config (DP_2_6_B1_Config)
DP ChannelEn (DP_2_6_B1_ChannelEn)
DP SampleCtrl (DP_2_6_B1_SampleCtrl)
DP OffsetCtrl (DP_2_6_B1_OffsetCtrl)
DP HCtrl (DP_2_6_B1_HCtrl)
DP AsyncCtrl (DP_2_6_B1_AsyncCtrl)
DP Port Ctrl (DP_2_6_Port_Ctrl)
DP Config (DP_2_7_B0_Config)
DP ChannelEn (DP_2_7_B0_ChannelEn)
DP SampleCtrl (DP_2_7_B0_SampleCtrl)
DP OffsetCtrl (DP_2_7_B0_OffsetCtrl)
DP HCtrl (DP_2_7_B0_HCtrl)
DP AsyncCtrl (DP_2_7_B0_AsyncCtrl)
DP Config (DP_2_7_B1_Config)
DP ChannelEn (DP_2_7_B1_ChannelEn)
DP SampleCtrl (DP_2_7_B1_SampleCtrl)
DP OffsetCtrl (DP_2_7_B1_OffsetCtrl)
DP HCtrl (DP_2_7_B1_HCtrl)
DP AsyncCtrl (DP_2_7_B1_AsyncCtrl)
DP Port Ctrl (DP_2_7_Port_Ctrl)
DP Config (DP_2_8_B0_Config)
DP ChannelEn (DP_2_8_B0_ChannelEn)
DP SampleCtrl (DP_2_8_B0_SampleCtrl)
DP OffsetCtrl (DP_2_8_B0_OffsetCtrl)
DP HCtrl (DP_2_8_B0_HCtrl)
DP AsyncCtrl (DP_2_8_B0_AsyncCtrl)
DP Config (DP_2_8_B1_Config)
DP ChannelEn (DP_2_8_B1_ChannelEn)
DP SampleCtrl (DP_2_8_B1_SampleCtrl)
DP OffsetCtrl (DP_2_8_B1_OffsetCtrl)
DP HCtrl (DP_2_8_B1_HCtrl)
DP AsyncCtrl (DP_2_8_B1_AsyncCtrl)
DP Port Ctrl (DP_2_8_Port_Ctrl)
DP Config (DP_2_9_B0_Config)
DP ChannelEn (DP_2_9_B0_ChannelEn)
DP SampleCtrl (DP_2_9_B0_SampleCtrl)
DP OffsetCtrl (DP_2_9_B0_OffsetCtrl)
DP HCtrl (DP_2_9_B0_HCtrl)
DP AsyncCtrl (DP_2_9_B0_AsyncCtrl)
DP Config (DP_2_9_B1_Config)
DP ChannelEn (DP_2_9_B1_ChannelEn)
DP SampleCtrl (DP_2_9_B1_SampleCtrl)
DP OffsetCtrl (DP_2_9_B1_OffsetCtrl)
DP HCtrl (DP_2_9_B1_HCtrl)
DP AsyncCtrl (DP_2_9_B1_AsyncCtrl)
DP Port Ctrl (DP_2_9_Port_Ctrl)
DP Config (DP_2_10_B0_Config)
DP ChannelEn (DP_2_10_B0_ChannelEn)
DP SampleCtrl (DP_2_10_B0_SampleCtrl)
DP OffsetCtrl (DP_2_10_B0_OffsetCtrl)
DP HCtrl (DP_2_10_B0_HCtrl)
DP AsyncCtrl (DP_2_10_B0_AsyncCtrl)
DP Config (DP_2_10_B1_Config)
DP ChannelEn (DP_2_10_B1_ChannelEn)
DP SampleCtrl (DP_2_10_B1_SampleCtrl)
DP OffsetCtrl (DP_2_10_B1_OffsetCtrl)
DP HCtrl (DP_2_10_B1_HCtrl)
DP AsyncCtrl (DP_2_10_B1_AsyncCtrl)
DP Port Ctrl (DP_2_10_Port_Ctrl)
DP Config (DP_2_11_B0_Config)
DP ChannelEn (DP_2_11_B0_ChannelEn)
DP SampleCtrl (DP_2_11_B0_SampleCtrl)
DP OffsetCtrl (DP_2_11_B0_OffsetCtrl)
DP HCtrl (DP_2_11_B0_HCtrl)
DP AsyncCtrl (DP_2_11_B0_AsyncCtrl)
DP Config (DP_2_11_B1_Config)
DP ChannelEn (DP_2_11_B1_ChannelEn)
DP SampleCtrl (DP_2_11_B1_SampleCtrl)
DP OffsetCtrl (DP_2_11_B1_OffsetCtrl)
DP HCtrl (DP_2_11_B1_HCtrl)
DP AsyncCtrl (DP_2_11_B1_AsyncCtrl)
DP Port Ctrl (DP_2_11_Port_Ctrl)
DP Config (DP_2_12_B0_Config)
DP ChannelEn (DP_2_12_B0_ChannelEn)
DP SampleCtrl (DP_2_12_B0_SampleCtrl)
DP OffsetCtrl (DP_2_12_B0_OffsetCtrl)
DP HCtrl (DP_2_12_B0_HCtrl)
DP AsyncCtrl (DP_2_12_B0_AsyncCtrl)
DP Config (DP_2_12_B1_Config)
DP ChannelEn (DP_2_12_B1_ChannelEn)
DP SampleCtrl (DP_2_12_B1_SampleCtrl)
DP OffsetCtrl (DP_2_12_B1_OffsetCtrl)
DP HCtrl (DP_2_12_B1_HCtrl)
DP AsyncCtrl (DP_2_12_B1_AsyncCtrl)
DP Port Ctrl (DP_2_12_Port_Ctrl)
DP Config (DP_2_13_B0_Config)
DP ChannelEn (DP_2_13_B0_ChannelEn)
DP SampleCtrl (DP_2_13_B0_SampleCtrl)
DP OffsetCtrl (DP_2_13_B0_OffsetCtrl)
DP HCtrl (DP_2_13_B0_HCtrl)
DP AsyncCtrl (DP_2_13_B0_AsyncCtrl)
DP Config (DP_2_13_B1_Config)
DP ChannelEn (DP_2_13_B1_ChannelEn)
DP SampleCtrl (DP_2_13_B1_SampleCtrl)
DP OffsetCtrl (DP_2_13_B1_OffsetCtrl)
DP HCtrl (DP_2_13_B1_HCtrl)
DP AsyncCtrl (DP_2_13_B1_AsyncCtrl)
DP Port Ctrl (DP_2_13_Port_Ctrl)
DP Config (DP_2_14_B0_Config)
DP ChannelEn (DP_2_14_B0_ChannelEn)
DP SampleCtrl (DP_2_14_B0_SampleCtrl)
DP OffsetCtrl (DP_2_14_B0_OffsetCtrl)
DP HCtrl (DP_2_14_B0_HCtrl)
DP AsyncCtrl (DP_2_14_B0_AsyncCtrl)
DP Config (DP_2_14_B1_Config)
DP ChannelEn (DP_2_14_B1_ChannelEn)
DP SampleCtrl (DP_2_14_B1_SampleCtrl)
DP OffsetCtrl (DP_2_14_B1_OffsetCtrl)
DP HCtrl (DP_2_14_B1_HCtrl)
DP AsyncCtrl (DP_2_14_B1_AsyncCtrl)
DP Port Ctrl (DP_2_14_Port_Ctrl)
PDI Config (PDI_2_0_Config)
PDI Config (PDI_2_1_Config)
PDI Config (PDI_2_2_Config)
PDI Config (PDI_2_3_Config)
PDI Config (PDI_2_4_Config)
PDI Config (PDI_2_5_Config)
PDI Config (PDI_2_6_Config)
PDI Config (PDI_2_7_Config)
PDI Config (PDI_2_8_Config)
PDI Config (PDI_2_9_Config)
PDI Config (PDI_2_10_Config)
PDI Config (PDI_2_11_Config)
PDI Config (PDI_2_12_Config)
PDI Config (PDI_2_13_Config)
PDI Config (PDI_2_14_Config)
PDI Config (PDI_2_15_Config)
IP MCP Config (IP_MCP_2_Config)
IP MCP Control (IP_MCP_2_Control)
IP MCP CmdCtrl (IP_MCP_2_CmdCtrl)
IP MCP PHYCtrl (IP_MCP_2_PHYCtrl)
IP MCP B0_ClockCtrl (IP_MCP_2_B0_ClockCtrl)
IP MCP Stat (IP_MCP_2_Stat)
IP MCP IntSet (IP_MCP_2_IntSet)
IP MCP Command (IP_MCP_2_Command)
SoundWire x Link Vendor Specific Control (SNDW2LVSCTL)
SoundWire x Wake Enable (SNDW2WAKEEN)
SoundWire x Wake Status (SNDW2WAKESTS)
SoundWire x I/O Control (SNDW2IOCTL)
SoundWire x AC Timing Control (SNDW2ACTMCTL)
SoundWire x Microphone Privacy Control & Status (SNDW2PVCCS)
SoundWire x Link Extended Capability (SNDW3LECAP)
SoundWire x PCM Stream Capabilities (SNDW3PCMSCAP)
SoundWire PCM Stream y Channel Count (SNDW3PCMS0CHC)
SoundWire x PCM Stream y Channel Map (SNDW3PCMS0CM)
SoundWire PCM Stream y Channel Count (SNDW3PCMS1CHC)
SoundWire x PCM Stream y Channel Map (SNDW3PCMS1CM)
SoundWire PCM Stream y Channel Count (SNDW3PCMS2CHC)
SoundWire x PCM Stream y Channel Map (SNDW3PCMS2CM)
SoundWire PCM Stream y Channel Count (SNDW3PCMS3CHC)
SoundWire x PCM Stream y Channel Map (SNDW3PCMS3CM)
SoundWire PCM Stream y Channel Count (SNDW3PCMS4CHC)
SoundWire x PCM Stream y Channel Map (SNDW3PCMS4CM)
SoundWire PCM Stream y Channel Count (SNDW3PCMS5CHC)
SoundWire x PCM Stream y Channel Map (SNDW3PCMS5CM)
SoundWire PCM Stream y Channel Count (SNDW3PCMS6CHC)
SoundWire x PCM Stream y Channel Map (SNDW3PCMS6CM)
SoundWire PCM Stream y Channel Count (SNDW3PCMS7CHC)
SoundWire x PCM Stream y Channel Map (SNDW3PCMS7CM)
SoundWire PCM Stream y Channel Count (SNDW3PCMS8CHC)
SoundWire x PCM Stream y Channel Map (SNDW3PCMS8CM)
SoundWire PCM Stream y Channel Count (SNDW3PCMS9CHC)
SoundWire x PCM Stream y Channel Map (SNDW3PCMS9CM)
SoundWire PCM Stream y Channel Count (SNDW3PCMS10CHC)
SoundWire x PCM Stream y Channel Map (SNDW3PCMS10CM)
SoundWire PCM Stream y Channel Count (SNDW3PCMS11CHC)
SoundWire x PCM Stream y Channel Map (SNDW3PCMS11CM)
SoundWire PCM Stream y Channel Count (SNDW3PCMS12CHC)
SoundWire x PCM Stream y Channel Map (SNDW3PCMS12CM)
SoundWire PCM Stream y Channel Count (SNDW3PCMS13CHC)
SoundWire x PCM Stream y Channel Map (SNDW3PCMS13CM)
SoundWire PCM Stream y Channel Count (SNDW3PCMS14CHC)
SoundWire x PCM Stream y Channel Map (SNDW3PCMS14CM)
SoundWire PCM Stream y Channel Count (SNDW3PCMS15CHC)
SoundWire x PCM Stream y Channel Map (SNDW3PCMS15CM)
MCP Config (MCP_3_Config)
MCP Control (MCP_3_Control)
MCP SSPStat (MCP_3_SSPStat)
MCP FrameShape (MCP_3_FrameShape)
MCP FrameShapeInit (MCP_3_FrameShapeInit)
MCP ConfigUpdate (MCP_3_ConfigUpdate)
MCP SSPCtrl (MCP_3_B0_SSPCtrl)
MCP SSPCtrl (MCP_3_B1_SSPCtrl)
MCP ClockCtrl (MCP_3_B0_ClockCtrl)
MCP ClockCtrl (MCP_3_B1_ClockCtrl)
MCP Stat (MCP_3_Stat)
MCP IntStat (MCP_3_IntStat)
MCP IntMask (MCP_3_IntMask)
MCP PeripheryStat (MCP_3_PeripheryStat)
MCP PeripheryIntStat0 (MCP_3_PeripheryIntStat0)
MCP PeripheryIntStat1 (MCP_3_PeripheryIntStat1)
MCP PeripheryIntMask0 (MCP_3_PeripheryIntMask0)
MCP PeripheryIntMask1 (MCP_3_PeripheryIntMask1)
MCP PortIntStat (MCP_3_PortIntStat)
MCP PDIStat (MCP_3_PDIStat)
MCP FIFOLevel (MCP_3_FIFOLevel)
MCP FIFOStat (MCP_3_FIFOStat)
DP Config (DP_3_0_B0_Config)
DP ChannelEn (DP_3_0_B0_ChannelEn)
DP SampleCtrl (DP_3_0_B0_SampleCtrl)
DP OffsetCtrl (DP_3_0_B0_OffsetCtrl)
DP HCtrl (DP_3_0_B0_HCtrl)
DP AsyncCtrl (DP_3_0_B0_AsyncCtrl)
DP Config (DP_3_0_B1_Config)
DP ChannelEn (DP_3_0_B1_ChannelEn)
DP SampleCtrl (DP_3_0_B1_SampleCtrl)
DP OffsetCtrl (DP_3_0_B1_OffsetCtrl)
DP HCtrl (DP_3_0_B1_HCtrl)
DP AsyncCtrl (DP_3_0_B1_AsyncCtrl)
DP Port Ctrl (DP_3_0_Port_Ctrl)
DP Config (DP_3_1_B0_Config)
DP ChannelEn (DP_3_1_B0_ChannelEn)
DP SampleCtrl (DP_3_1_B0_SampleCtrl)
DP OffsetCtrl (DP_3_1_B0_OffsetCtrl)
DP HCtrl (DP_3_1_B0_HCtrl)
DP AsyncCtrl (DP_3_1_B0_AsyncCtrl)
DP Config (DP_3_1_B1_Config)
DP ChannelEn (DP_3_1_B1_ChannelEn)
DP SampleCtrl (DP_3_1_B1_SampleCtrl)
DP OffsetCtrl (DP_3_1_B1_OffsetCtrl)
DP HCtrl (DP_3_1_B1_HCtrl)
DP AsyncCtrl (DP_3_1_B1_AsyncCtrl)
DP Port Ctrl (DP_3_1_Port_Ctrl)
DP Config (DP_3_2_B0_Config)
DP ChannelEn (DP_3_2_B0_ChannelEn)
DP SampleCtrl (DP_3_2_B0_SampleCtrl)
DP OffsetCtrl (DP_3_2_B0_OffsetCtrl)
DP HCtrl (DP_3_2_B0_HCtrl)
DP AsyncCtrl (DP_3_2_B0_AsyncCtrl)
DP Config (DP_3_2_B1_Config)
DP ChannelEn (DP_3_2_B1_ChannelEn)
DP SampleCtrl (DP_3_2_B1_SampleCtrl)
DP OffsetCtrl (DP_3_2_B1_OffsetCtrl)
DP HCtrl (DP_3_2_B1_HCtrl)
DP AsyncCtrl (DP_3_2_B1_AsyncCtrl)
DP Port Ctrl (DP_3_2_Port_Ctrl)
DP Config (DP_3_3_B0_Config)
DP ChannelEn (DP_3_3_B0_ChannelEn)
DP SampleCtrl (DP_3_3_B0_SampleCtrl)
DP OffsetCtrl (DP_3_3_B0_OffsetCtrl)
DP HCtrl (DP_3_3_B0_HCtrl)
DP AsyncCtrl (DP_3_3_B0_AsyncCtrl)
DP Config (DP_3_3_B1_Config)
DP ChannelEn (DP_3_3_B1_ChannelEn)
DP SampleCtrl (DP_3_3_B1_SampleCtrl)
DP OffsetCtrl (DP_3_3_B1_OffsetCtrl)
DP HCtrl (DP_3_3_B1_HCtrl)
DP AsyncCtrl (DP_3_3_B1_AsyncCtrl)
DP Port Ctrl (DP_3_3_Port_Ctrl)
DP Config (DP_3_4_B0_Config)
DP ChannelEn (DP_3_4_B0_ChannelEn)
DP SampleCtrl (DP_3_4_B0_SampleCtrl)
DP OffsetCtrl (DP_3_4_B0_OffsetCtrl)
DP HCtrl (DP_3_4_B0_HCtrl)
DP AsyncCtrl (DP_3_4_B0_AsyncCtrl)
DP Config (DP_3_4_B1_Config)
DP ChannelEn (DP_3_4_B1_ChannelEn)
DP SampleCtrl (DP_3_4_B1_SampleCtrl)
DP OffsetCtrl (DP_3_4_B1_OffsetCtrl)
DP HCtrl (DP_3_4_B1_HCtrl)
DP AsyncCtrl (DP_3_4_B1_AsyncCtrl)
DP Port Ctrl (DP_3_4_Port_Ctrl)
DP Config (DP_3_5_B0_Config)
DP ChannelEn (DP_3_5_B0_ChannelEn)
DP SampleCtrl (DP_3_5_B0_SampleCtrl)
DP OffsetCtrl (DP_3_5_B0_OffsetCtrl)
DP HCtrl (DP_3_5_B0_HCtrl)
DP AsyncCtrl (DP_3_5_B0_AsyncCtrl)
DP Config (DP_3_5_B1_Config)
DP ChannelEn (DP_3_5_B1_ChannelEn)
DP SampleCtrl (DP_3_5_B1_SampleCtrl)
DP OffsetCtrl (DP_3_5_B1_OffsetCtrl)
DP HCtrl (DP_3_5_B1_HCtrl)
DP AsyncCtrl (DP_3_5_B1_AsyncCtrl)
DP Port Ctrl (DP_3_5_Port_Ctrl)
DP Config (DP_3_6_B0_Config)
DP ChannelEn (DP_3_6_B0_ChannelEn)
DP SampleCtrl (DP_3_6_B0_SampleCtrl)
DP OffsetCtrl (DP_3_6_B0_OffsetCtrl)
DP HCtrl (DP_3_6_B0_HCtrl)
DP AsyncCtrl (DP_3_6_B0_AsyncCtrl)
DP Config (DP_3_6_B1_Config)
DP ChannelEn (DP_3_6_B1_ChannelEn)
DP SampleCtrl (DP_3_6_B1_SampleCtrl)
DP OffsetCtrl (DP_3_6_B1_OffsetCtrl)
DP HCtrl (DP_3_6_B1_HCtrl)
DP AsyncCtrl (DP_3_6_B1_AsyncCtrl)
DP Port Ctrl (DP_3_6_Port_Ctrl)
DP Config (DP_3_7_B0_Config)
DP ChannelEn (DP_3_7_B0_ChannelEn)
DP SampleCtrl (DP_3_7_B0_SampleCtrl)
DP OffsetCtrl (DP_3_7_B0_OffsetCtrl)
DP HCtrl (DP_3_7_B0_HCtrl)
DP AsyncCtrl (DP_3_7_B0_AsyncCtrl)
DP Config (DP_3_7_B1_Config)
DP ChannelEn (DP_3_7_B1_ChannelEn)
DP SampleCtrl (DP_3_7_B1_SampleCtrl)
DP OffsetCtrl (DP_3_7_B1_OffsetCtrl)
DP HCtrl (DP_3_7_B1_HCtrl)
DP AsyncCtrl (DP_3_7_B1_AsyncCtrl)
DP Port Ctrl (DP_3_7_Port_Ctrl)
DP Config (DP_3_8_B0_Config)
DP ChannelEn (DP_3_8_B0_ChannelEn)
DP SampleCtrl (DP_3_8_B0_SampleCtrl)
DP OffsetCtrl (DP_3_8_B0_OffsetCtrl)
DP HCtrl (DP_3_8_B0_HCtrl)
DP AsyncCtrl (DP_3_8_B0_AsyncCtrl)
DP Config (DP_3_8_B1_Config)
DP ChannelEn (DP_3_8_B1_ChannelEn)
DP SampleCtrl (DP_3_8_B1_SampleCtrl)
DP OffsetCtrl (DP_3_8_B1_OffsetCtrl)
DP HCtrl (DP_3_8_B1_HCtrl)
DP AsyncCtrl (DP_3_8_B1_AsyncCtrl)
DP Port Ctrl (DP_3_8_Port_Ctrl)
DP Config (DP_3_9_B0_Config)
DP ChannelEn (DP_3_9_B0_ChannelEn)
DP SampleCtrl (DP_3_9_B0_SampleCtrl)
DP OffsetCtrl (DP_3_9_B0_OffsetCtrl)
DP HCtrl (DP_3_9_B0_HCtrl)
DP AsyncCtrl (DP_3_9_B0_AsyncCtrl)
DP Config (DP_3_9_B1_Config)
DP ChannelEn (DP_3_9_B1_ChannelEn)
DP SampleCtrl (DP_3_9_B1_SampleCtrl)
DP OffsetCtrl (DP_3_9_B1_OffsetCtrl)
DP HCtrl (DP_3_9_B1_HCtrl)
DP AsyncCtrl (DP_3_9_B1_AsyncCtrl)
DP Port Ctrl (DP_3_9_Port_Ctrl)
DP Config (DP_3_10_B0_Config)
DP ChannelEn (DP_3_10_B0_ChannelEn)
DP SampleCtrl (DP_3_10_B0_SampleCtrl)
DP OffsetCtrl (DP_3_10_B0_OffsetCtrl)
DP HCtrl (DP_3_10_B0_HCtrl)
DP AsyncCtrl (DP_3_10_B0_AsyncCtrl)
DP Config (DP_3_10_B1_Config)
DP ChannelEn (DP_3_10_B1_ChannelEn)
DP SampleCtrl (DP_3_10_B1_SampleCtrl)
DP OffsetCtrl (DP_3_10_B1_OffsetCtrl)
DP HCtrl (DP_3_10_B1_HCtrl)
DP AsyncCtrl (DP_3_10_B1_AsyncCtrl)
DP Port Ctrl (DP_3_10_Port_Ctrl)
DP Config (DP_3_11_B0_Config)
DP ChannelEn (DP_3_11_B0_ChannelEn)
DP SampleCtrl (DP_3_11_B0_SampleCtrl)
DP OffsetCtrl (DP_3_11_B0_OffsetCtrl)
DP HCtrl (DP_3_11_B0_HCtrl)
DP AsyncCtrl (DP_3_11_B0_AsyncCtrl)
DP Config (DP_3_11_B1_Config)
DP ChannelEn (DP_3_11_B1_ChannelEn)
DP SampleCtrl (DP_3_11_B1_SampleCtrl)
DP OffsetCtrl (DP_3_11_B1_OffsetCtrl)
DP HCtrl (DP_3_11_B1_HCtrl)
DP AsyncCtrl (DP_3_11_B1_AsyncCtrl)
DP Port Ctrl (DP_3_11_Port_Ctrl)
DP Config (DP_3_12_B0_Config)
DP ChannelEn (DP_3_12_B0_ChannelEn)
DP SampleCtrl (DP_3_12_B0_SampleCtrl)
DP OffsetCtrl (DP_3_12_B0_OffsetCtrl)
DP HCtrl (DP_3_12_B0_HCtrl)
DP AsyncCtrl (DP_3_12_B0_AsyncCtrl)
DP Config (DP_3_12_B1_Config)
DP ChannelEn (DP_3_12_B1_ChannelEn)
DP SampleCtrl (DP_3_12_B1_SampleCtrl)
DP OffsetCtrl (DP_3_12_B1_OffsetCtrl)
DP HCtrl (DP_3_12_B1_HCtrl)
DP AsyncCtrl (DP_3_12_B1_AsyncCtrl)
DP Port Ctrl (DP_3_12_Port_Ctrl)
DP Config (DP_3_13_B0_Config)
DP ChannelEn (DP_3_13_B0_ChannelEn)
DP SampleCtrl (DP_3_13_B0_SampleCtrl)
DP OffsetCtrl (DP_3_13_B0_OffsetCtrl)
DP HCtrl (DP_3_13_B0_HCtrl)
DP AsyncCtrl (DP_3_13_B0_AsyncCtrl)
DP Config (DP_3_13_B1_Config)
DP ChannelEn (DP_3_13_B1_ChannelEn)
DP SampleCtrl (DP_3_13_B1_SampleCtrl)
DP OffsetCtrl (DP_3_13_B1_OffsetCtrl)
DP HCtrl (DP_3_13_B1_HCtrl)
DP AsyncCtrl (DP_3_13_B1_AsyncCtrl)
DP Port Ctrl (DP_3_13_Port_Ctrl)
DP Config (DP_3_14_B0_Config)
DP ChannelEn (DP_3_14_B0_ChannelEn)
DP SampleCtrl (DP_3_14_B0_SampleCtrl)
DP OffsetCtrl (DP_3_14_B0_OffsetCtrl)
DP HCtrl (DP_3_14_B0_HCtrl)
DP AsyncCtrl (DP_3_14_B0_AsyncCtrl)
DP Config (DP_3_14_B1_Config)
DP ChannelEn (DP_3_14_B1_ChannelEn)
DP SampleCtrl (DP_3_14_B1_SampleCtrl)
DP OffsetCtrl (DP_3_14_B1_OffsetCtrl)
DP HCtrl (DP_3_14_B1_HCtrl)
DP AsyncCtrl (DP_3_14_B1_AsyncCtrl)
DP Port Ctrl (DP_3_14_Port_Ctrl)
PDI Config (PDI_3_0_Config)
PDI Config (PDI_3_1_Config)
PDI Config (PDI_3_2_Config)
PDI Config (PDI_3_3_Config)
PDI Config (PDI_3_4_Config)
PDI Config (PDI_3_5_Config)
PDI Config (PDI_3_6_Config)
PDI Config (PDI_3_7_Config)
PDI Config (PDI_3_8_Config)
PDI Config (PDI_3_9_Config)
PDI Config (PDI_3_10_Config)
PDI Config (PDI_3_11_Config)
PDI Config (PDI_3_12_Config)
PDI Config (PDI_3_13_Config)
PDI Config (PDI_3_14_Config)
PDI Config (PDI_3_15_Config)
IP MCP Config (IP_MCP_3_Config)
IP MCP Control (IP_MCP_3_Control)
IP MCP CmdCtrl (IP_MCP_3_CmdCtrl)
IP MCP PHYCtrl (IP_MCP_3_PHYCtrl)
IP MCP B0_ClockCtrl (IP_MCP_3_B0_ClockCtrl)
IP MCP Stat (IP_MCP_3_Stat)
IP MCP IntSet (IP_MCP_3_IntSet)
IP MCP Command (IP_MCP_3_Command)
SoundWire x Link Vendor Specific Control (SNDW3LVSCTL)
SoundWire x Wake Enable (SNDW3WAKEEN)
SoundWire x Wake Status (SNDW3WAKESTS)
SoundWire x I/O Control (SNDW3IOCTL)
SoundWire x AC Timing Control (SNDW3ACTMCTL)
SoundWire x Microphone Privacy Control & Status (SNDW3PVCCS)
SoundWire x Link Extended Capability (SNDW4LECAP)
SoundWire x PCM Stream Capabilities (SNDW4PCMSCAP)
SoundWire PCM Stream y Channel Count (SNDW4PCMS0CHC)
SoundWire x PCM Stream y Channel Map (SNDW4PCMS0CM)
SoundWire PCM Stream y Channel Count (SNDW4PCMS1CHC)
SoundWire x PCM Stream y Channel Map (SNDW4PCMS1CM)
SoundWire PCM Stream y Channel Count (SNDW4PCMS2CHC)
SoundWire x PCM Stream y Channel Map (SNDW4PCMS2CM)
SoundWire PCM Stream y Channel Count (SNDW4PCMS3CHC)
SoundWire x PCM Stream y Channel Map (SNDW4PCMS3CM)
SoundWire PCM Stream y Channel Count (SNDW4PCMS4CHC)
SoundWire x PCM Stream y Channel Map (SNDW4PCMS4CM)
SoundWire PCM Stream y Channel Count (SNDW4PCMS5CHC)
SoundWire x PCM Stream y Channel Map (SNDW4PCMS5CM)
SoundWire PCM Stream y Channel Count (SNDW4PCMS6CHC)
SoundWire x PCM Stream y Channel Map (SNDW4PCMS6CM)
SoundWire PCM Stream y Channel Count (SNDW4PCMS7CHC)
SoundWire x PCM Stream y Channel Map (SNDW4PCMS7CM)
SoundWire PCM Stream y Channel Count (SNDW4PCMS8CHC)
SoundWire x PCM Stream y Channel Map (SNDW4PCMS8CM)
SoundWire PCM Stream y Channel Count (SNDW4PCMS9CHC)
SoundWire x PCM Stream y Channel Map (SNDW4PCMS9CM)
SoundWire PCM Stream y Channel Count (SNDW4PCMS10CHC)
SoundWire x PCM Stream y Channel Map (SNDW4PCMS10CM)
SoundWire PCM Stream y Channel Count (SNDW4PCMS11CHC)
SoundWire x PCM Stream y Channel Map (SNDW4PCMS11CM)
SoundWire PCM Stream y Channel Count (SNDW4PCMS12CHC)
SoundWire x PCM Stream y Channel Map (SNDW4PCMS12CM)
SoundWire PCM Stream y Channel Count (SNDW4PCMS13CHC)
SoundWire x PCM Stream y Channel Map (SNDW4PCMS13CM)
SoundWire PCM Stream y Channel Count (SNDW4PCMS14CHC)
SoundWire x PCM Stream y Channel Map (SNDW4PCMS14CM)
SoundWire PCM Stream y Channel Count (SNDW4PCMS15CHC)
SoundWire x PCM Stream y Channel Map (SNDW4PCMS15CM)
MCP Config (MCP_4_Config)
MCP Control (MCP_4_Control)
MCP SSPStat (MCP_4_SSPStat)
MCP FrameShape (MCP_4_FrameShape)
MCP FrameShapeInit (MCP_4_FrameShapeInit)
MCP ConfigUpdate (MCP_4_ConfigUpdate)
MCP SSPCtrl (MCP_4_B0_SSPCtrl)
MCP SSPCtrl (MCP_4_B1_SSPCtrl)
MCP ClockCtrl (MCP_4_B0_ClockCtrl)
MCP ClockCtrl (MCP_4_B1_ClockCtrl)
MCP Stat (MCP_4_Stat)
MCP IntStat (MCP_4_IntStat)
MCP IntMask (MCP_4_IntMask)
MCP PeripheryStat (MCP_4_PeripheryStat)
MCP PeripheryIntStat0 (MCP_4_PeripheryIntStat0)
MCP PeripheryIntStat1 (MCP_4_PeripheryIntStat1)
MCP PeripheryIntMask0 (MCP_4_PeripheryIntMask0)
MCP PeripheryIntMask1 (MCP_4_PeripheryIntMask1)
MCP PortIntStat (MCP_4_PortIntStat)
MCP PDIStat (MCP_4_PDIStat)
MCP FIFOLevel (MCP_4_FIFOLevel)
MCP FIFOStat (MCP_4_FIFOStat)
DP Config (DP_4_0_B0_Config)
DP ChannelEn (DP_4_0_B0_ChannelEn)
DP SampleCtrl (DP_4_0_B0_SampleCtrl)
DP OffsetCtrl (DP_4_0_B0_OffsetCtrl)
DP HCtrl (DP_4_0_B0_HCtrl)
DP AsyncCtrl (DP_4_0_B0_AsyncCtrl)
DP Config (DP_4_0_B1_Config)
DP ChannelEn (DP_4_0_B1_ChannelEn)
DP SampleCtrl (DP_4_0_B1_SampleCtrl)
DP OffsetCtrl (DP_4_0_B1_OffsetCtrl)
DP HCtrl (DP_4_0_B1_HCtrl)
DP AsyncCtrl (DP_4_0_B1_AsyncCtrl)
DP Port Ctrl (DP_4_0_Port_Ctrl)
DP Config (DP_4_1_B0_Config)
DP ChannelEn (DP_4_1_B0_ChannelEn)
DP SampleCtrl (DP_4_1_B0_SampleCtrl)
DP OffsetCtrl (DP_4_1_B0_OffsetCtrl)
DP HCtrl (DP_4_1_B0_HCtrl)
DP AsyncCtrl (DP_4_1_B0_AsyncCtrl)
DP Config (DP_4_1_B1_Config)
DP ChannelEn (DP_4_1_B1_ChannelEn)
DP SampleCtrl (DP_4_1_B1_SampleCtrl)
DP OffsetCtrl (DP_4_1_B1_OffsetCtrl)
DP HCtrl (DP_4_1_B1_HCtrl)
DP AsyncCtrl (DP_4_1_B1_AsyncCtrl)
DP Port Ctrl (DP_4_1_Port_Ctrl)
DP Config (DP_4_2_B0_Config)
DP ChannelEn (DP_4_2_B0_ChannelEn)
DP SampleCtrl (DP_4_2_B0_SampleCtrl)
DP OffsetCtrl (DP_4_2_B0_OffsetCtrl)
DP HCtrl (DP_4_2_B0_HCtrl)
DP AsyncCtrl (DP_4_2_B0_AsyncCtrl)
DP Config (DP_4_2_B1_Config)
DP ChannelEn (DP_4_2_B1_ChannelEn)
DP SampleCtrl (DP_4_2_B1_SampleCtrl)
DP OffsetCtrl (DP_4_2_B1_OffsetCtrl)
DP HCtrl (DP_4_2_B1_HCtrl)
DP AsyncCtrl (DP_4_2_B1_AsyncCtrl)
DP Port Ctrl (DP_4_2_Port_Ctrl)
DP Config (DP_4_3_B0_Config)
DP ChannelEn (DP_4_3_B0_ChannelEn)
DP SampleCtrl (DP_4_3_B0_SampleCtrl)
DP OffsetCtrl (DP_4_3_B0_OffsetCtrl)
DP HCtrl (DP_4_3_B0_HCtrl)
DP AsyncCtrl (DP_4_3_B0_AsyncCtrl)
DP Config (DP_4_3_B1_Config)
DP ChannelEn (DP_4_3_B1_ChannelEn)
DP SampleCtrl (DP_4_3_B1_SampleCtrl)
DP OffsetCtrl (DP_4_3_B1_OffsetCtrl)
DP HCtrl (DP_4_3_B1_HCtrl)
DP AsyncCtrl (DP_4_3_B1_AsyncCtrl)
DP Port Ctrl (DP_4_3_Port_Ctrl)
DP Config (DP_4_4_B0_Config)
DP ChannelEn (DP_4_4_B0_ChannelEn)
DP SampleCtrl (DP_4_4_B0_SampleCtrl)
DP OffsetCtrl (DP_4_4_B0_OffsetCtrl)
DP HCtrl (DP_4_4_B0_HCtrl)
DP AsyncCtrl (DP_4_4_B0_AsyncCtrl)
DP Config (DP_4_4_B1_Config)
DP ChannelEn (DP_4_4_B1_ChannelEn)
DP SampleCtrl (DP_4_4_B1_SampleCtrl)
DP OffsetCtrl (DP_4_4_B1_OffsetCtrl)
DP HCtrl (DP_4_4_B1_HCtrl)
DP AsyncCtrl (DP_4_4_B1_AsyncCtrl)
DP Port Ctrl (DP_4_4_Port_Ctrl)
DP Config (DP_4_5_B0_Config)
DP ChannelEn (DP_4_5_B0_ChannelEn)
DP SampleCtrl (DP_4_5_B0_SampleCtrl)
DP OffsetCtrl (DP_4_5_B0_OffsetCtrl)
DP HCtrl (DP_4_5_B0_HCtrl)
DP AsyncCtrl (DP_4_5_B0_AsyncCtrl)
DP Config (DP_4_5_B1_Config)
DP ChannelEn (DP_4_5_B1_ChannelEn)
DP SampleCtrl (DP_4_5_B1_SampleCtrl)
DP OffsetCtrl (DP_4_5_B1_OffsetCtrl)
DP HCtrl (DP_4_5_B1_HCtrl)
DP AsyncCtrl (DP_4_5_B1_AsyncCtrl)
DP Port Ctrl (DP_4_5_Port_Ctrl)
DP Config (DP_4_6_B0_Config)
DP ChannelEn (DP_4_6_B0_ChannelEn)
DP SampleCtrl (DP_4_6_B0_SampleCtrl)
DP OffsetCtrl (DP_4_6_B0_OffsetCtrl)
DP HCtrl (DP_4_6_B0_HCtrl)
DP AsyncCtrl (DP_4_6_B0_AsyncCtrl)
DP Config (DP_4_6_B1_Config)
DP ChannelEn (DP_4_6_B1_ChannelEn)
DP SampleCtrl (DP_4_6_B1_SampleCtrl)
DP OffsetCtrl (DP_4_6_B1_OffsetCtrl)
DP HCtrl (DP_4_6_B1_HCtrl)
DP AsyncCtrl (DP_4_6_B1_AsyncCtrl)
DP Port Ctrl (DP_4_6_Port_Ctrl)
DP Config (DP_4_7_B0_Config)
DP ChannelEn (DP_4_7_B0_ChannelEn)
DP SampleCtrl (DP_4_7_B0_SampleCtrl)
DP OffsetCtrl (DP_4_7_B0_OffsetCtrl)
DP HCtrl (DP_4_7_B0_HCtrl)
DP AsyncCtrl (DP_4_7_B0_AsyncCtrl)
DP Config (DP_4_7_B1_Config)
DP ChannelEn (DP_4_7_B1_ChannelEn)
DP SampleCtrl (DP_4_7_B1_SampleCtrl)
DP OffsetCtrl (DP_4_7_B1_OffsetCtrl)
DP HCtrl (DP_4_7_B1_HCtrl)
DP AsyncCtrl (DP_4_7_B1_AsyncCtrl)
DP Port Ctrl (DP_4_7_Port_Ctrl)
DP Config (DP_4_8_B0_Config)
DP ChannelEn (DP_4_8_B0_ChannelEn)
DP SampleCtrl (DP_4_8_B0_SampleCtrl)
DP OffsetCtrl (DP_4_8_B0_OffsetCtrl)
DP HCtrl (DP_4_8_B0_HCtrl)
DP AsyncCtrl (DP_4_8_B0_AsyncCtrl)
DP Config (DP_4_8_B1_Config)
DP ChannelEn (DP_4_8_B1_ChannelEn)
DP SampleCtrl (DP_4_8_B1_SampleCtrl)
DP OffsetCtrl (DP_4_8_B1_OffsetCtrl)
DP HCtrl (DP_4_8_B1_HCtrl)
DP AsyncCtrl (DP_4_8_B1_AsyncCtrl)
DP Port Ctrl (DP_4_8_Port_Ctrl)
DP Config (DP_4_9_B0_Config)
DP ChannelEn (DP_4_9_B0_ChannelEn)
DP SampleCtrl (DP_4_9_B0_SampleCtrl)
DP OffsetCtrl (DP_4_9_B0_OffsetCtrl)
DP HCtrl (DP_4_9_B0_HCtrl)
DP AsyncCtrl (DP_4_9_B0_AsyncCtrl)
DP Config (DP_4_9_B1_Config)
DP ChannelEn (DP_4_9_B1_ChannelEn)
DP SampleCtrl (DP_4_9_B1_SampleCtrl)
DP OffsetCtrl (DP_4_9_B1_OffsetCtrl)
DP HCtrl (DP_4_9_B1_HCtrl)
DP AsyncCtrl (DP_4_9_B1_AsyncCtrl)
DP Port Ctrl (DP_4_9_Port_Ctrl)
DP Config (DP_4_10_B0_Config)
DP ChannelEn (DP_4_10_B0_ChannelEn)
DP SampleCtrl (DP_4_10_B0_SampleCtrl)
DP OffsetCtrl (DP_4_10_B0_OffsetCtrl)
DP HCtrl (DP_4_10_B0_HCtrl)
DP AsyncCtrl (DP_4_10_B0_AsyncCtrl)
DP Config (DP_4_10_B1_Config)
DP ChannelEn (DP_4_10_B1_ChannelEn)
DP SampleCtrl (DP_4_10_B1_SampleCtrl)
DP OffsetCtrl (DP_4_10_B1_OffsetCtrl)
DP HCtrl (DP_4_10_B1_HCtrl)
DP AsyncCtrl (DP_4_10_B1_AsyncCtrl)
DP Port Ctrl (DP_4_10_Port_Ctrl)
DP Config (DP_4_11_B0_Config)
DP ChannelEn (DP_4_11_B0_ChannelEn)
DP SampleCtrl (DP_4_11_B0_SampleCtrl)
DP OffsetCtrl (DP_4_11_B0_OffsetCtrl)
DP HCtrl (DP_4_11_B0_HCtrl)
DP AsyncCtrl (DP_4_11_B0_AsyncCtrl)
DP Config (DP_4_11_B1_Config)
DP ChannelEn (DP_4_11_B1_ChannelEn)
DP SampleCtrl (DP_4_11_B1_SampleCtrl)
DP OffsetCtrl (DP_4_11_B1_OffsetCtrl)
DP HCtrl (DP_4_11_B1_HCtrl)
DP AsyncCtrl (DP_4_11_B1_AsyncCtrl)
DP Port Ctrl (DP_4_11_Port_Ctrl)
DP Config (DP_4_12_B0_Config)
DP ChannelEn (DP_4_12_B0_ChannelEn)
DP SampleCtrl (DP_4_12_B0_SampleCtrl)
DP OffsetCtrl (DP_4_12_B0_OffsetCtrl)
DP HCtrl (DP_4_12_B0_HCtrl)
DP AsyncCtrl (DP_4_12_B0_AsyncCtrl)
DP Config (DP_4_12_B1_Config)
DP ChannelEn (DP_4_12_B1_ChannelEn)
DP SampleCtrl (DP_4_12_B1_SampleCtrl)
DP OffsetCtrl (DP_4_12_B1_OffsetCtrl)
DP HCtrl (DP_4_12_B1_HCtrl)
DP AsyncCtrl (DP_4_12_B1_AsyncCtrl)
DP Port Ctrl (DP_4_12_Port_Ctrl)
DP Config (DP_4_13_B0_Config)
DP ChannelEn (DP_4_13_B0_ChannelEn)
DP SampleCtrl (DP_4_13_B0_SampleCtrl)
DP OffsetCtrl (DP_4_13_B0_OffsetCtrl)
DP HCtrl (DP_4_13_B0_HCtrl)
DP AsyncCtrl (DP_4_13_B0_AsyncCtrl)
DP Config (DP_4_13_B1_Config)
DP ChannelEn (DP_4_13_B1_ChannelEn)
DP SampleCtrl (DP_4_13_B1_SampleCtrl)
DP OffsetCtrl (DP_4_13_B1_OffsetCtrl)
DP HCtrl (DP_4_13_B1_HCtrl)
DP AsyncCtrl (DP_4_13_B1_AsyncCtrl)
DP Port Ctrl (DP_4_13_Port_Ctrl)
DP Config (DP_4_14_B0_Config)
DP ChannelEn (DP_4_14_B0_ChannelEn)
DP SampleCtrl (DP_4_14_B0_SampleCtrl)
DP OffsetCtrl (DP_4_14_B0_OffsetCtrl)
DP HCtrl (DP_4_14_B0_HCtrl)
DP AsyncCtrl (DP_4_14_B0_AsyncCtrl)
DP Config (DP_4_14_B1_Config)
DP ChannelEn (DP_4_14_B1_ChannelEn)
DP SampleCtrl (DP_4_14_B1_SampleCtrl)
DP OffsetCtrl (DP_4_14_B1_OffsetCtrl)
DP HCtrl (DP_4_14_B1_HCtrl)
DP AsyncCtrl (DP_4_14_B1_AsyncCtrl)
DP Port Ctrl (DP_4_14_Port_Ctrl)
PDI Config (PDI_4_0_Config)
PDI Config (PDI_4_1_Config)
PDI Config (PDI_4_2_Config)
PDI Config (PDI_4_3_Config)
PDI Config (PDI_4_4_Config)
PDI Config (PDI_4_5_Config)
PDI Config (PDI_4_6_Config)
PDI Config (PDI_4_7_Config)
PDI Config (PDI_4_8_Config)
PDI Config (PDI_4_9_Config)
PDI Config (PDI_4_10_Config)
PDI Config (PDI_4_11_Config)
PDI Config (PDI_4_12_Config)
PDI Config (PDI_4_13_Config)
PDI Config (PDI_4_14_Config)
PDI Config (PDI_4_15_Config)
IP MCP Config (IP_MCP_4_Config)
IP MCP Control (IP_MCP_4_Control)
IP MCP CmdCtrl (IP_MCP_4_CmdCtrl)
IP MCP PHYCtrl (IP_MCP_4_PHYCtrl)
IP MCP B0_ClockCtrl (IP_MCP_4_B0_ClockCtrl)
IP MCP Stat (IP_MCP_4_Stat)
IP MCP IntSet (IP_MCP_4_IntSet)
IP MCP Command (IP_MCP_4_Command)
SoundWire x Link Vendor Specific Control (SNDW4LVSCTL)
SoundWire x Wake Enable (SNDW4WAKEEN)
SoundWire x Wake Status (SNDW4WAKESTS)
SoundWire x I/O Control (SNDW4IOCTL)
SoundWire x AC Timing Control (SNDW4ACTMCTL)
SoundWire x Microphone Privacy Control & Status (SNDW4PVCCS)
Audio PCI Configuration
Audio PCI Configuration Vendor Identification (VID) Device Identification (DID) Device Command (CMD) Device Status (STS) Revision Identification (RID) Programming Interface (PI) Sub Class Code (SCC) Base Class Code (BCC) Cache Line Size (CLS) Latency Timer (LT) Header Type (HTYPE) Built-in Self Test (BIST) Intel HD Audio Lower Base Address (HDALBA) Intel HD Audio Upper Base Address (HDAUBA) Shadowed PCI Configuration Lower Base Address (SPCLBA) Shadowed PCI Configuration Upper Base Address (SPCUBA) DSP Subsystem Lower Base Address (DSPLBA) DSP Subsystem Upper Base Address (DSPUBA) Subsystem Vendor Identifier (SVID) Subsystem Identifier (SID) Capabilities Pointer (CAPPTR) Interrupt Line (INTLN) Interrupt Pin (INTPN) Power Management Identifiers (PID) Power Management Capabilities (PC) Power Management Control & Status (PCS) MSI Identifiers (MID) MSI Message Control (MMC) MSI Message Lower Address (MMLA) MSI Message Upper Address (MMUA) MSI Message Data (MMD) PCI Express Identifiers (PXID) PCI Express Capabilities (PXC) Device Capabilities (DEVCAP) Device Control (DEVC) Device Status (DEVS) Vendor Specific Capability Identifiers (VSCID) Vendor Specific Extended Capability Identifiers (VSECID) Device Idle Pointer (DEVIDLEPTR) Device Idle Power On Latency (DEVIDLEPOL) Power Control Enable (PCE)
Vendor Identification (VID)
Device Identification (DID)
Device Command (CMD)
Device Status (STS)
Revision Identification (RID)
Programming Interface (PI)
Sub Class Code (SCC)
Base Class Code (BCC)
Cache Line Size (CLS)
Latency Timer (LT)
Header Type (HTYPE)
Built-in Self Test (BIST)
Intel HD Audio Lower Base Address (HDALBA)
Intel HD Audio Upper Base Address (HDAUBA)
Shadowed PCI Configuration Lower Base Address (SPCLBA)
Shadowed PCI Configuration Upper Base Address (SPCUBA)
DSP Subsystem Lower Base Address (DSPLBA)
DSP Subsystem Upper Base Address (DSPUBA)
Subsystem Vendor Identifier (SVID)
Subsystem Identifier (SID)
Capabilities Pointer (CAPPTR)
Interrupt Line (INTLN)
Interrupt Pin (INTPN)
Power Management Identifiers (PID)
Power Management Capabilities (PC)
Power Management Control & Status (PCS)
MSI Identifiers (MID)
MSI Message Control (MMC)
MSI Message Lower Address (MMLA)
MSI Message Upper Address (MMUA)
MSI Message Data (MMD)
PCI Express Identifiers (PXID)
PCI Express Capabilities (PXC)
Device Capabilities (DEVCAP)
Device Control (DEVC)
Device Status (DEVS)
Vendor Specific Capability Identifiers (VSCID)
Vendor Specific Extended Capability Identifiers (VSECID)
Device Idle Pointer (DEVIDLEPTR)
Device Idle Power On Latency (DEVIDLEPOL)
Power Control Enable (PCE)
CNVi Bluetooth* PCI Configuration
CNVi Bluetooth* PCI Configuration Vendor Device Identification (VEN_DEV_ID) Command and Status (PCI_COM_STAT) PCI CLASS CODE (PCI_CLASS_CODE) PCI BUS COM (PCI_BUS_COM) BAR0 (BAR0) BAR1 (BAR1) SUBSYS Identification (SUBSYS_ID) ROM BAR (ROM_BAR) Capabilities Pointer (CAP_PTR) Interrupt (INTERRUPT) PCI Express Capabilities (GIO_CAP) Device Capability 1 (GIO_DEV_CAP) Device Control 1 (GIO_DEV) Device Capability 2 (GIO_DEV_CAP_2) Device Control 2 (GIO_DEV_2) MSIX Capability (MSIX_CAP_HEAD) MSIX TABLE OFFSET (MSIX_TABLE_OFFSET) MSIX PBA OFFSET (MSIX_PBA_OFFSET) Power Management Capabilities (PMC) Power Management Status and Control (PMCSR) MSI Message Control (MSI_MSG_CTRL) MSI LOW Address (MSI_LOW_ADD) MSI HIGH Address (MSI_HIGH_ADD) MSI Data (MSI_DATA) LTR Extended Capability (LTR_EXTND_CAP_HEAD) LTR Maximum NOSNOOP Latency (LTR_MAX_SNOOP_NOSNOOP_LAT)
Vendor Device Identification (VEN_DEV_ID)
Command and Status (PCI_COM_STAT)
PCI CLASS CODE (PCI_CLASS_CODE)
PCI BUS COM (PCI_BUS_COM)
BAR0 (BAR0)
BAR1 (BAR1)
SUBSYS Identification (SUBSYS_ID)
ROM BAR (ROM_BAR)
Capabilities Pointer (CAP_PTR)
Interrupt (INTERRUPT)
PCI Express Capabilities (GIO_CAP)
Device Capability 1 (GIO_DEV_CAP)
Device Control 1 (GIO_DEV)
Device Capability 2 (GIO_DEV_CAP_2)
Device Control 2 (GIO_DEV_2)
MSIX Capability (MSIX_CAP_HEAD)
MSIX TABLE OFFSET (MSIX_TABLE_OFFSET)
MSIX PBA OFFSET (MSIX_PBA_OFFSET)
Power Management Capabilities (PMC)
Power Management Status and Control (PMCSR)
MSI Message Control (MSI_MSG_CTRL)
MSI LOW Address (MSI_LOW_ADD)
MSI HIGH Address (MSI_HIGH_ADD)
MSI Data (MSI_DATA)
LTR Extended Capability (LTR_EXTND_CAP_HEAD)
LTR Maximum NOSNOOP Latency (LTR_MAX_SNOOP_NOSNOOP_LAT)
CNVi WiFi* PCI Configuration
CNVi WiFi* PCI Configuration Vendor Device Identification (VEN_DEV_ID) PCI Command and Status (PCI_COM_STAT) PCI CLASS CODE (PCI_CLASS_CODE) PCI BUS COM (PCI_BUS_COM) BAR0 (BAR0) BAR1 (BAR1) SUBSYS Identification (SUBSYS_ID) ROM BAR (ROM_BAR) Capabilities Pointer (CAP_PTR) Interrupt (INTERRUPT) PCI Express Capabilities (GIO_CAP) Device Capability 1 (GIO_DEV_CAP) Device Control 1 (GIO_DEV) Device Capability 2 (GIO_DEV_CAP_2) Device Control 2 (GIO_DEV_2) MSIX Capability HEAD (MSIX_CAP_HEAD) MSIX TABLE OFFSET (MSIX_TABLE_OFFSET) MSIX PBA OFFSET (MSIX_PBA_OFFSET) Power Management Capabilities (PMC) Power Management Status and Control (PMCSR) MSI Message Control (MSI_MSG_CTRL) MSI LOW Address (MSI_LOW_ADD) MSI HIGH Address (MSI_HIGH_ADD) MSI Data (MSI_DATA) LTR Extended Capability (LTR_EXTND_CAP_HEAD) LTR Maximum NOSNOOP Latency (LTR_MAX_SNOOP_NOSNOOP_LAT) HEALTHY External Capability (HEALTHY_EXT_CAP_REG) HEALTHY STATUS (HEALTHY_STATUS)
Vendor Device Identification (VEN_DEV_ID)
PCI Command and Status (PCI_COM_STAT)
PCI CLASS CODE (PCI_CLASS_CODE)
PCI BUS COM (PCI_BUS_COM)
BAR0 (BAR0)
BAR1 (BAR1)
SUBSYS Identification (SUBSYS_ID)
ROM BAR (ROM_BAR)
Capabilities Pointer (CAP_PTR)
Interrupt (INTERRUPT)
PCI Express Capabilities (GIO_CAP)
Device Capability 1 (GIO_DEV_CAP)
Device Control 1 (GIO_DEV)
Device Capability 2 (GIO_DEV_CAP_2)
Device Control 2 (GIO_DEV_2)
MSIX Capability HEAD (MSIX_CAP_HEAD)
MSIX TABLE OFFSET (MSIX_TABLE_OFFSET)
MSIX PBA OFFSET (MSIX_PBA_OFFSET)
Power Management Capabilities (PMC)
Power Management Status and Control (PMCSR)
MSI Message Control (MSI_MSG_CTRL)
MSI LOW Address (MSI_LOW_ADD)
MSI HIGH Address (MSI_HIGH_ADD)
MSI Data (MSI_DATA)
LTR Extended Capability (LTR_EXTND_CAP_HEAD)
LTR Maximum NOSNOOP Latency (LTR_MAX_SNOOP_NOSNOOP_LAT)
HEALTHY External Capability (HEALTHY_EXT_CAP_REG)
HEALTHY STATUS (HEALTHY_STATUS)
eSPI PCI Configuration (D31:F0)
eSPI PCI Configuration (D31:F0) Device and Vendor Identifiers (ESPI_DID_VID) Device Status and Command (ESPI_STS_CMD) Class Code and Revision ID (ESPI_CC_RID) Peripheral Channel Header Type and Primary Latency (ESPI_PCHT_PCPLT) Sub System Identifiers (ESPI_SS) Capability List Pointer (ESPI_CAPP) I/O Decode Ranges and I/O Enables (ESPI_IOD_IOE) eSPI Generic IO Range 1 (ESPI_LGIR1) eSPI Generic IO Range 2 (ESPI_LGIR2) eSPI Generic IO Range 3 (ESPI_LGIR3) eSPI Generic IO Range 4 (ESPI_LGIR4) USB Legacy Keyboard/Mouse Control (ESPI_ULKMC) eSPI Generic Memory Range (ESPI_LGMR) eSPI CS1 IO Routing Enables (ESPI_CS1IORE) eSPI CS1 Generic IO Range 1 (ESPI_CS1GIR1) eSPI CS1 Generic Memory Range 1 (ESPI_CS1GMR1) BIOS Decode Enable (ESPI_BDE) BIOS Control (ESPI_BC) eSPI IO Routing Enables for ESPI CS2 (ESPI_IORE_EXT[2]) eSPI Generic IO Range 1 for ESPI CS2 (ESPI_GIR1_EXT[2]) eSPI Generic Memory Range 1 for ESPI CS2 (ESPI_GMR1_EXT[2]) eSPI IO Routing Enables for ESPI CS3 (ESPI_IORE_EXT[3]) eSPI Generic IO Range 1 for ESPI CS3 (ESPI_GIR1_EXT[3]) eSPI Generic Memory Range 1 for ESPI CS3 (ESPI_GMR1_EXT[3])
Device and Vendor Identifiers (ESPI_DID_VID)
Device Status and Command (ESPI_STS_CMD)
Class Code and Revision ID (ESPI_CC_RID)
Peripheral Channel Header Type and Primary Latency (ESPI_PCHT_PCPLT)
Sub System Identifiers (ESPI_SS)
Capability List Pointer (ESPI_CAPP)
I/O Decode Ranges and I/O Enables (ESPI_IOD_IOE)
eSPI Generic IO Range 1 (ESPI_LGIR1)
eSPI Generic IO Range 2 (ESPI_LGIR2)
eSPI Generic IO Range 3 (ESPI_LGIR3)
eSPI Generic IO Range 4 (ESPI_LGIR4)
USB Legacy Keyboard/Mouse Control (ESPI_ULKMC)
eSPI Generic Memory Range (ESPI_LGMR)
eSPI CS1 IO Routing Enables (ESPI_CS1IORE)
eSPI CS1 Generic IO Range 1 (ESPI_CS1GIR1)
eSPI CS1 Generic Memory Range 1 (ESPI_CS1GMR1)
BIOS Decode Enable (ESPI_BDE)
BIOS Control (ESPI_BC)
eSPI IO Routing Enables for ESPI CS2 (ESPI_IORE_EXT[2])
eSPI Generic IO Range 1 for ESPI CS2 (ESPI_GIR1_EXT[2])
eSPI Generic Memory Range 1 for ESPI CS2 (ESPI_GMR1_EXT[2])
eSPI IO Routing Enables for ESPI CS3 (ESPI_IORE_EXT[3])
eSPI Generic IO Range 1 for ESPI CS3 (ESPI_GIR1_EXT[3])
eSPI Generic Memory Range 1 for ESPI CS3 (ESPI_GMR1_EXT[3])
eSPI PCR
eSPI PCR eSPI Device Configuration Register And Link Control (SLV_CFG_REG_CTL) eSPI Device Configuration Register Data (SLV_CFG_REG_DATA) Peripheral Channel Error for Device 0 (PCERR_SLV0) Peripheral Channel Error for Device 1 (PCERR_SLV1) Virtual Wire Channel Error for Device 0 (VWERR_SLV0) Virtual Wire Channel Error for Device 1 (VWERR_SLV1) Flash Access Channel Error for Device 0 (FCERR_SLV0) Link Error for Device 0 (LNKERR_SLV0) Link Error for Device 1 (LNKERR_SLV1) Peripheral Channel Error for Device 2 (PCERR_SLV_EXT[2]) Virtual Wire Channel Error for Device 2 (VWERR_SLV_EXT[2]) Link Error for Device 2 (LNKERR_SLV_EXT[2]) Peripheral Channel Error for Device 3 (PCERR_SLV_EXT[3]) Virtual Wire Channel Error for Device 3 (VWERR_SLV_EXT[3]) Link Error for Device 3 (LNKERR_SLV_EXT[3])
eSPI Device Configuration Register And Link Control (SLV_CFG_REG_CTL)
eSPI Device Configuration Register Data (SLV_CFG_REG_DATA)
Peripheral Channel Error for Device 0 (PCERR_SLV0)
Peripheral Channel Error for Device 1 (PCERR_SLV1)
Virtual Wire Channel Error for Device 0 (VWERR_SLV0)
Virtual Wire Channel Error for Device 1 (VWERR_SLV1)
Flash Access Channel Error for Device 0 (FCERR_SLV0)
Link Error for Device 0 (LNKERR_SLV0)
Link Error for Device 1 (LNKERR_SLV1)
Peripheral Channel Error for Device 2 (PCERR_SLV_EXT[2])
Virtual Wire Channel Error for Device 2 (VWERR_SLV_EXT[2])
Link Error for Device 2 (LNKERR_SLV_EXT[2])
Peripheral Channel Error for Device 3 (PCERR_SLV_EXT[3])
Virtual Wire Channel Error for Device 3 (VWERR_SLV_EXT[3])
Link Error for Device 3 (LNKERR_SLV_EXT[3])
GPIO Community 0
GPIO Community 0 Family Base Address (FAMBAR) Pad Base Address (PADBAR) Miscellaneous Configuration (MISCCFG) Pad Ownership (PAD_OWN_xxgpp_v_0) Pad Ownership (PAD_OWN_xxgpp_v_1) Pad Ownership (PAD_OWN_xxgpp_v_2) Pad Ownership (PAD_OWN_xxgpp_v_3) Pad Ownership (PAD_OWN_xxgpp_v_4) Pad Ownership (PAD_OWN_xxgpp_v_5) Pad Ownership (PAD_OWN_xxgpp_v_6) Pad Ownership (PAD_OWN_xxgpp_v_7) Pad Ownership (PAD_OWN_xxgpp_v_8) Pad Ownership (PAD_OWN_xxgpp_v_9) Pad Ownership (PAD_OWN_xxgpp_v_10) Pad Ownership (PAD_OWN_xxgpp_v_11) Pad Ownership (PAD_OWN_xxgpp_v_12) Pad Ownership (PAD_OWN_xxgpp_v_13) Pad Ownership (PAD_OWN_xxgpp_v_14) Pad Ownership (PAD_OWN_xxgpp_v_15) Pad Ownership (PAD_OWN_xxgpp_v_16) Pad Ownership (PAD_OWN_xxgpp_v_17) Pad Ownership (PAD_OWN_xxgpp_c_0) Pad Ownership (PAD_OWN_xxgpp_c_1) Pad Ownership (PAD_OWN_xxgpp_c_2) Pad Ownership (PAD_OWN_xxgpp_c_3) Pad Ownership (PAD_OWN_xxgpp_c_4) Pad Ownership (PAD_OWN_xxgpp_c_5) Pad Ownership (PAD_OWN_xxgpp_c_6) Pad Ownership (PAD_OWN_xxgpp_c_7) Pad Ownership (PAD_OWN_xxgpp_c_8) Pad Ownership (PAD_OWN_xxgpp_c_9) Pad Ownership (PAD_OWN_xxgpp_c_10) Pad Ownership (PAD_OWN_xxgpp_c_11) Pad Ownership (PAD_OWN_xxgpp_c_12) Pad Ownership (PAD_OWN_xxgpp_c_13) Pad Ownership (PAD_OWN_xxgpp_c_14) Pad Ownership (PAD_OWN_xxgpp_c_15) Pad Ownership (PAD_OWN_xxgpp_c_16) Pad Ownership (PAD_OWN_xxgpp_c_17) Pad Ownership (PAD_OWN_xxgpp_c_18) Pad Ownership (PAD_OWN_xxgpp_c_19) Pad Ownership (PAD_OWN_xxgpp_c_20) Pad Ownership (PAD_OWN_xxgpp_c_21) Pad Ownership (PAD_OWN_xxgpp_c_22) Pad Ownership (PAD_OWN_xxgpp_c_23) Pad Configuration Lock (PADCFGLOCK_GPP_V_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_V_0) Pad Configuration Lock (PADCFGLOCK_GPP_C_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_C_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_V_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_C_0) GPI Interrupt Status (GPI_IS_GPP_V_0) GPI Interrupt Status (GPI_IS_GPP_C_0) GPI Interrupt Enable (GPI_IE_GPP_V_0) GPI Interrupt Enable (GPI_IE_GPP_C_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_V_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_V_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_0) SMI Status (GPI_SMI_STS_GPP_C_0) SMI Enable (GPI_SMI_EN_GPP_C_0) NMI Status (GPI_NMI_STS_GPP_C_0) NMI Enable (GPI_NMI_EN_GPP_C_0) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_0) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_0) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_1) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_1) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_2) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_2) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_3) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_3) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_4) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_4) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_5) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_5) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_6) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_6) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_7) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_7) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_8) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_8) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_9) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_9) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_10) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_10) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_11) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_11) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_12) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_12) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_13) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_13) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_14) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_14) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_15) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_15) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_16) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_16) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_17) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_17) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_0) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_0) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_1) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_1) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_2) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_2) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_3) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_3) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_4) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_4) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_5) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_5) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_6) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_6) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_7) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_7) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_8) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_8) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_9) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_9) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_10) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_10) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_11) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_11) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_12) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_12) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_13) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_13) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_14) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_14) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_15) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_15) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_16) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_16) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_17) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_17) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_18) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_18) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_19) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_19) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_20) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_20) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_21) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_21) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_22) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_22) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_23) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_23)
Family Base Address (FAMBAR)
Pad Base Address (PADBAR)
Miscellaneous Configuration (MISCCFG)
Pad Ownership (PAD_OWN_xxgpp_v_0)
Pad Ownership (PAD_OWN_xxgpp_v_1)
Pad Ownership (PAD_OWN_xxgpp_v_2)
Pad Ownership (PAD_OWN_xxgpp_v_3)
Pad Ownership (PAD_OWN_xxgpp_v_4)
Pad Ownership (PAD_OWN_xxgpp_v_5)
Pad Ownership (PAD_OWN_xxgpp_v_6)
Pad Ownership (PAD_OWN_xxgpp_v_7)
Pad Ownership (PAD_OWN_xxgpp_v_8)
Pad Ownership (PAD_OWN_xxgpp_v_9)
Pad Ownership (PAD_OWN_xxgpp_v_10)
Pad Ownership (PAD_OWN_xxgpp_v_11)
Pad Ownership (PAD_OWN_xxgpp_v_12)
Pad Ownership (PAD_OWN_xxgpp_v_13)
Pad Ownership (PAD_OWN_xxgpp_v_14)
Pad Ownership (PAD_OWN_xxgpp_v_15)
Pad Ownership (PAD_OWN_xxgpp_v_16)
Pad Ownership (PAD_OWN_xxgpp_v_17)
Pad Ownership (PAD_OWN_xxgpp_c_0)
Pad Ownership (PAD_OWN_xxgpp_c_1)
Pad Ownership (PAD_OWN_xxgpp_c_2)
Pad Ownership (PAD_OWN_xxgpp_c_3)
Pad Ownership (PAD_OWN_xxgpp_c_4)
Pad Ownership (PAD_OWN_xxgpp_c_5)
Pad Ownership (PAD_OWN_xxgpp_c_6)
Pad Ownership (PAD_OWN_xxgpp_c_7)
Pad Ownership (PAD_OWN_xxgpp_c_8)
Pad Ownership (PAD_OWN_xxgpp_c_9)
Pad Ownership (PAD_OWN_xxgpp_c_10)
Pad Ownership (PAD_OWN_xxgpp_c_11)
Pad Ownership (PAD_OWN_xxgpp_c_12)
Pad Ownership (PAD_OWN_xxgpp_c_13)
Pad Ownership (PAD_OWN_xxgpp_c_14)
Pad Ownership (PAD_OWN_xxgpp_c_15)
Pad Ownership (PAD_OWN_xxgpp_c_16)
Pad Ownership (PAD_OWN_xxgpp_c_17)
Pad Ownership (PAD_OWN_xxgpp_c_18)
Pad Ownership (PAD_OWN_xxgpp_c_19)
Pad Ownership (PAD_OWN_xxgpp_c_20)
Pad Ownership (PAD_OWN_xxgpp_c_21)
Pad Ownership (PAD_OWN_xxgpp_c_22)
Pad Ownership (PAD_OWN_xxgpp_c_23)
Pad Configuration Lock (PADCFGLOCK_GPP_V_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_V_0)
Pad Configuration Lock (PADCFGLOCK_GPP_C_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_C_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_V_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_C_0)
GPI Interrupt Status (GPI_IS_GPP_V_0)
GPI Interrupt Status (GPI_IS_GPP_C_0)
GPI Interrupt Enable (GPI_IE_GPP_V_0)
GPI Interrupt Enable (GPI_IE_GPP_C_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_V_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_V_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_0)
SMI Status (GPI_SMI_STS_GPP_C_0)
SMI Enable (GPI_SMI_EN_GPP_C_0)
NMI Status (GPI_NMI_STS_GPP_C_0)
NMI Enable (GPI_NMI_EN_GPP_C_0)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_0)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_0)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_1)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_1)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_2)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_2)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_3)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_3)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_4)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_4)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_5)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_5)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_6)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_6)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_7)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_7)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_8)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_8)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_9)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_9)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_10)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_10)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_11)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_11)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_12)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_12)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_13)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_13)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_14)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_14)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_15)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_15)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_16)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_16)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_v_17)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_v_17)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_0)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_0)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_1)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_1)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_2)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_2)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_3)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_3)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_4)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_4)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_5)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_5)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_6)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_6)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_7)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_7)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_8)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_8)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_9)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_9)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_10)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_10)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_11)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_11)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_12)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_12)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_13)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_13)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_14)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_14)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_15)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_15)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_16)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_16)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_17)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_17)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_18)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_18)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_19)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_19)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_20)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_20)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_21)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_21)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_22)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_22)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_c_23)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_c_23)
GPIO Community 1
GPIO Community 1 Family Base Address (FAMBAR) Pad Base Address (PADBAR) Miscellaneous Configuration (MISCCFG) Pad Ownership (PAD_OWN_xxgpp_f_0) Pad Ownership (PAD_OWN_xxgpp_f_1) Pad Ownership (PAD_OWN_xxgpp_f_2) Pad Ownership (PAD_OWN_xxgpp_f_3) Pad Ownership (PAD_OWN_xxgpp_f_4) Pad Ownership (PAD_OWN_xxgpp_f_5) Pad Ownership (PAD_OWN_xxgpp_f_6) Pad Ownership (PAD_OWN_xxgpp_f_7) Pad Ownership (PAD_OWN_xxgpp_f_8) Pad Ownership (PAD_OWN_xxgpp_f_9) Pad Ownership (PAD_OWN_xxgpp_f_10) Pad Ownership (PAD_OWN_xxgpp_f_11) Pad Ownership (PAD_OWN_xxgpp_f_12) Pad Ownership (PAD_OWN_xxgpp_f_13) Pad Ownership (PAD_OWN_xxgpp_f_14) Pad Ownership (PAD_OWN_xxgpp_f_15) Pad Ownership (PAD_OWN_xxgpp_f_16) Pad Ownership (PAD_OWN_xxgpp_f_17) Pad Ownership (PAD_OWN_xxgpp_f_18) Pad Ownership (PAD_OWN_xxgpp_f_19) Pad Ownership (PAD_OWN_xxgpp_f_20) Pad Ownership (PAD_OWN_xxgpp_f_21) Pad Ownership (PAD_OWN_xxgpp_f_22) Pad Ownership (PAD_OWN_xxgpp_f_23) Pad Ownership (PAD_OWN_xxgpp_e_1) Pad Ownership (PAD_OWN_xxgpp_e_2) Pad Ownership (PAD_OWN_xxgpp_e_3) Pad Ownership (PAD_OWN_xxgpp_e_5) Pad Ownership (PAD_OWN_xxgpp_e_6) Pad Ownership (PAD_OWN_xxgpp_e_7) Pad Ownership (PAD_OWN_xxgpp_e_8) Pad Ownership (PAD_OWN_xxgpp_e_9) Pad Ownership (PAD_OWN_xxgpp_e_10) Pad Ownership (PAD_OWN_xxgpp_e_11) Pad Ownership (PAD_OWN_xxgpp_e_12) Pad Ownership (PAD_OWN_xxgpp_e_13) Pad Ownership (PAD_OWN_xxgpp_e_14) Pad Ownership (PAD_OWN_xxgpp_e_15) Pad Ownership (PAD_OWN_xxgpp_e_16) Pad Ownership (PAD_OWN_xxgpp_e_17) Pad Ownership (PAD_OWN_xxgpp_e_18) Pad Ownership (PAD_OWN_xxgpp_e_19) Pad Ownership (PAD_OWN_xxgpp_e_20) Pad Ownership (PAD_OWN_xxgpp_e_21) Pad Ownership (PAD_OWN_xxgpp_e_22) Pad Configuration Lock (PADCFGLOCK_GPP_F_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_F_0) Pad Configuration Lock (PADCFGLOCK_GPP_E_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_E_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_F_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_E_0) GPI Interrupt Status (GPI_IS_GPP_F_0) GPI Interrupt Status (GPI_IS_GPP_E_0) GPI Interrupt Enable (GPI_IE_GPP_F_0) GPI Interrupt Enable (GPI_IE_GPP_E_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_E_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_E_0) SMI Status (GPI_SMI_STS_GPP_E_0) SMI Enable (GPI_SMI_EN_GPP_E_0) NMI Status (GPI_NMI_STS_GPP_E_0) NMI Enable (GPI_NMI_EN_GPP_E_0) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_0) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_0) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_1) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_1) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_2) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_2) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_3) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_3) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_4) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_4) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_5) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_5) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_6) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_6) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_7) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_7) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_8) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_8) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_9) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_9) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_10) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_10) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_11) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_11) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_12) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_12) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_13) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_13) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_14) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_14) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_15) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_15) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_16) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_16) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_17) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_17) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_18) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_18) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_19) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_19) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_20) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_20) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_21) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_21) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_22) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_22) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_23) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_23) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_1) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_1) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_2) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_2) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_3) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_3) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_5) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_5) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_6) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_6) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_7) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_7) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_8) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_8) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_9) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_9) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_10) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_10) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_11) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_11) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_12) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_12) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_13) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_13) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_14) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_14) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_15) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_15) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_16) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_16) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_17) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_17) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_18) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_18) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_19) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_19) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_20) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_20) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_21) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_21) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_22) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_22)
Family Base Address (FAMBAR)
Pad Base Address (PADBAR)
Miscellaneous Configuration (MISCCFG)
Pad Ownership (PAD_OWN_xxgpp_f_0)
Pad Ownership (PAD_OWN_xxgpp_f_1)
Pad Ownership (PAD_OWN_xxgpp_f_2)
Pad Ownership (PAD_OWN_xxgpp_f_3)
Pad Ownership (PAD_OWN_xxgpp_f_4)
Pad Ownership (PAD_OWN_xxgpp_f_5)
Pad Ownership (PAD_OWN_xxgpp_f_6)
Pad Ownership (PAD_OWN_xxgpp_f_7)
Pad Ownership (PAD_OWN_xxgpp_f_8)
Pad Ownership (PAD_OWN_xxgpp_f_9)
Pad Ownership (PAD_OWN_xxgpp_f_10)
Pad Ownership (PAD_OWN_xxgpp_f_11)
Pad Ownership (PAD_OWN_xxgpp_f_12)
Pad Ownership (PAD_OWN_xxgpp_f_13)
Pad Ownership (PAD_OWN_xxgpp_f_14)
Pad Ownership (PAD_OWN_xxgpp_f_15)
Pad Ownership (PAD_OWN_xxgpp_f_16)
Pad Ownership (PAD_OWN_xxgpp_f_17)
Pad Ownership (PAD_OWN_xxgpp_f_18)
Pad Ownership (PAD_OWN_xxgpp_f_19)
Pad Ownership (PAD_OWN_xxgpp_f_20)
Pad Ownership (PAD_OWN_xxgpp_f_21)
Pad Ownership (PAD_OWN_xxgpp_f_22)
Pad Ownership (PAD_OWN_xxgpp_f_23)
Pad Ownership (PAD_OWN_xxgpp_e_1)
Pad Ownership (PAD_OWN_xxgpp_e_2)
Pad Ownership (PAD_OWN_xxgpp_e_3)
Pad Ownership (PAD_OWN_xxgpp_e_5)
Pad Ownership (PAD_OWN_xxgpp_e_6)
Pad Ownership (PAD_OWN_xxgpp_e_7)
Pad Ownership (PAD_OWN_xxgpp_e_8)
Pad Ownership (PAD_OWN_xxgpp_e_9)
Pad Ownership (PAD_OWN_xxgpp_e_10)
Pad Ownership (PAD_OWN_xxgpp_e_11)
Pad Ownership (PAD_OWN_xxgpp_e_12)
Pad Ownership (PAD_OWN_xxgpp_e_13)
Pad Ownership (PAD_OWN_xxgpp_e_14)
Pad Ownership (PAD_OWN_xxgpp_e_15)
Pad Ownership (PAD_OWN_xxgpp_e_16)
Pad Ownership (PAD_OWN_xxgpp_e_17)
Pad Ownership (PAD_OWN_xxgpp_e_18)
Pad Ownership (PAD_OWN_xxgpp_e_19)
Pad Ownership (PAD_OWN_xxgpp_e_20)
Pad Ownership (PAD_OWN_xxgpp_e_21)
Pad Ownership (PAD_OWN_xxgpp_e_22)
Pad Configuration Lock (PADCFGLOCK_GPP_F_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_F_0)
Pad Configuration Lock (PADCFGLOCK_GPP_E_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_E_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_F_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_E_0)
GPI Interrupt Status (GPI_IS_GPP_F_0)
GPI Interrupt Status (GPI_IS_GPP_E_0)
GPI Interrupt Enable (GPI_IE_GPP_F_0)
GPI Interrupt Enable (GPI_IE_GPP_E_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_E_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_E_0)
SMI Status (GPI_SMI_STS_GPP_E_0)
SMI Enable (GPI_SMI_EN_GPP_E_0)
NMI Status (GPI_NMI_STS_GPP_E_0)
NMI Enable (GPI_NMI_EN_GPP_E_0)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_0)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_0)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_1)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_1)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_2)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_2)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_3)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_3)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_4)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_4)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_5)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_5)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_6)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_6)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_7)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_7)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_8)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_8)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_9)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_9)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_10)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_10)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_11)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_11)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_12)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_12)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_13)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_13)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_14)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_14)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_15)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_15)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_16)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_16)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_17)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_17)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_18)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_18)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_19)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_19)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_20)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_20)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_21)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_21)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_22)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_22)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_f_23)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_f_23)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_1)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_1)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_2)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_2)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_3)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_3)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_5)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_5)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_6)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_6)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_7)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_7)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_8)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_8)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_9)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_9)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_10)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_10)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_11)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_11)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_12)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_12)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_13)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_13)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_14)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_14)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_15)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_15)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_16)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_16)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_17)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_17)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_18)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_18)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_19)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_19)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_20)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_20)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_21)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_21)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_e_22)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_e_22)
GPIO Community 3
GPIO Community 3 Family Base Address (FAMBAR) Miscellaneous Configuration (MISCCFG) Pad Ownership (PAD_OWN_xxgpp_h_0) Pad Ownership (PAD_OWN_xxgpp_h_1) Pad Ownership (PAD_OWN_xxgpp_h_2) Pad Ownership (PAD_OWN_xxgpp_h_3) Pad Ownership (PAD_OWN_xxgpp_h_4) Pad Ownership (PAD_OWN_xxgpp_h_5) Pad Ownership (PAD_OWN_xxgpp_h_6) Pad Ownership (PAD_OWN_xxgpp_h_7) Pad Ownership (PAD_OWN_xxgpp_h_8) Pad Ownership (PAD_OWN_xxgpp_h_9) Pad Ownership (PAD_OWN_xxgpp_h_10) Pad Ownership (PAD_OWN_xxgpp_h_11) Pad Ownership (PAD_OWN_xxgpp_h_12) Pad Ownership (PAD_OWN_xxgpp_h_13) Pad Ownership (PAD_OWN_xxgpp_h_14) Pad Ownership (PAD_OWN_xxgpp_h_15) Pad Ownership (PAD_OWN_xxgpp_h_16) Pad Ownership (PAD_OWN_xxgpp_h_17) Pad Ownership (PAD_OWN_xxgpp_h_18) Pad Ownership (PAD_OWN_xxgpp_h_19) Pad Ownership (PAD_OWN_xxgpp_h_20) Pad Ownership (PAD_OWN_xxgpp_h_21) Pad Ownership (PAD_OWN_xxgpp_h_22) Pad Ownership (PAD_OWN_xxgpp_h_23) Pad Ownership (PAD_OWN_xxgpp_h_24) Pad Ownership (PAD_OWN_xxgpp_a_0) Pad Ownership (PAD_OWN_xxgpp_a_1) Pad Ownership (PAD_OWN_xxgpp_a_2) Pad Ownership (PAD_OWN_xxgpp_a_3) Pad Ownership (PAD_OWN_xxgpp_a_4) Pad Ownership (PAD_OWN_xxgpp_a_5) Pad Ownership (PAD_OWN_xxgpp_a_6) Pad Ownership (PAD_OWN_xxgpp_a_7) Pad Ownership (PAD_OWN_xxgpp_a_8) Pad Ownership (PAD_OWN_xxgpp_a_9) Pad Ownership (PAD_OWN_xxgpp_a_10) Pad Ownership (PAD_OWN_xxgpp_a_11) Pad Ownership (PAD_OWN_xxgpp_a_12) Pad Ownership (PAD_OWN_xxgpp_a_13) Pad Ownership (PAD_OWN_xxgpp_a_14) Pad Ownership (PAD_OWN_xxgpp_a_15) Pad Ownership (PAD_OWN_xxgpp_a_16) Pad Ownership (PAD_OWN_xxgpp_a_17) Pad Ownership (PAD_OWN_vGPIO_TS0) Pad Ownership (PAD_OWN_vGPIO_TS1) Pad Ownership (PAD_OWN_vGPIO_THC0) Pad Ownership (PAD_OWN_vGPIO_THC1) Pad Ownership (PAD_OWN_vGPIO_THC2) Pad Ownership (PAD_OWN_vGPIO_THC3) Pad Configuration Lock (PADCFGLOCK_GPP_H_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_H_0) Pad Configuration Lock (PADCFGLOCK_GPP_A_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_A_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_H_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_A_0) Host Software Pad Ownership (HOSTSW_OWN_vGPIO_3_0) GPI Interrupt Status (GPI_IS_GPP_H_0) GPI Interrupt Status (GPI_IS_GPP_A_0) GPI Interrupt Status (GPI_IS_vGPIO_3_0) GPI Interrupt Enable (GPI_IE_GPP_H_0) GPI Interrupt Enable (GPI_IE_GPP_A_0) GPI Interrupt Enable (GPI_IE_vGPIO_3_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_H_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_0) GPI General Purpose Events Status (GPI_GPE_STS_vGPIO_3_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_H_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_0) GPI General Purpose Events Enable (GPI_GPE_EN_vGPIO_3_0) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_0) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_0) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_1) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_1) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_2) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_2) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_3) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_3) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_4) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_4) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_5) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_5) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_6) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_6) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_7) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_7) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_8) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_8) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_9) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_9) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_10) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_10) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_11) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_11) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_12) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_12) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_13) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_13) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_14) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_14) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_15) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_15) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_16) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_16) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_17) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_17) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_18) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_18) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_19) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_19) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_20) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_20) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_21) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_21) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_22) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_22) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_23) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_23) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_24) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_24) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_0) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_0) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_1) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_1) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_2) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_2) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_3) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_3) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_4) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_4) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_5) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_5) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_6) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_6) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_7) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_7) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_8) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_8) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_9) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_9) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_10) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_10) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_11) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_11) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_12) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_12) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_13) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_13) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_14) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_14) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_15) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_15) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_16) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_16) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_17) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_17) Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_TS0) Pad Configuration DW1 (PAD_CFG_DW1_vGPIO_TS0) Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_TS1) Pad Configuration DW1 (PAD_CFG_DW1_vGPIO_TS1) Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_THC0) Pad Configuration DW1 (PAD_CFG_DW1_vGPIO_THC0) Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_THC1) Pad Configuration DW1 (PAD_CFG_DW1_vGPIO_THC1) Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_THC2) Pad Configuration DW1 (PAD_CFG_DW1_vGPIO_THC2) Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_THC3) Pad Configuration DW1 (PAD_CFG_DW1_vGPIO_THC3)
Family Base Address (FAMBAR)
Miscellaneous Configuration (MISCCFG)
Pad Ownership (PAD_OWN_xxgpp_h_0)
Pad Ownership (PAD_OWN_xxgpp_h_1)
Pad Ownership (PAD_OWN_xxgpp_h_2)
Pad Ownership (PAD_OWN_xxgpp_h_3)
Pad Ownership (PAD_OWN_xxgpp_h_4)
Pad Ownership (PAD_OWN_xxgpp_h_5)
Pad Ownership (PAD_OWN_xxgpp_h_6)
Pad Ownership (PAD_OWN_xxgpp_h_7)
Pad Ownership (PAD_OWN_xxgpp_h_8)
Pad Ownership (PAD_OWN_xxgpp_h_9)
Pad Ownership (PAD_OWN_xxgpp_h_10)
Pad Ownership (PAD_OWN_xxgpp_h_11)
Pad Ownership (PAD_OWN_xxgpp_h_12)
Pad Ownership (PAD_OWN_xxgpp_h_13)
Pad Ownership (PAD_OWN_xxgpp_h_14)
Pad Ownership (PAD_OWN_xxgpp_h_15)
Pad Ownership (PAD_OWN_xxgpp_h_16)
Pad Ownership (PAD_OWN_xxgpp_h_17)
Pad Ownership (PAD_OWN_xxgpp_h_18)
Pad Ownership (PAD_OWN_xxgpp_h_19)
Pad Ownership (PAD_OWN_xxgpp_h_20)
Pad Ownership (PAD_OWN_xxgpp_h_21)
Pad Ownership (PAD_OWN_xxgpp_h_22)
Pad Ownership (PAD_OWN_xxgpp_h_23)
Pad Ownership (PAD_OWN_xxgpp_h_24)
Pad Ownership (PAD_OWN_xxgpp_a_0)
Pad Ownership (PAD_OWN_xxgpp_a_1)
Pad Ownership (PAD_OWN_xxgpp_a_2)
Pad Ownership (PAD_OWN_xxgpp_a_3)
Pad Ownership (PAD_OWN_xxgpp_a_4)
Pad Ownership (PAD_OWN_xxgpp_a_5)
Pad Ownership (PAD_OWN_xxgpp_a_6)
Pad Ownership (PAD_OWN_xxgpp_a_7)
Pad Ownership (PAD_OWN_xxgpp_a_8)
Pad Ownership (PAD_OWN_xxgpp_a_9)
Pad Ownership (PAD_OWN_xxgpp_a_10)
Pad Ownership (PAD_OWN_xxgpp_a_11)
Pad Ownership (PAD_OWN_xxgpp_a_12)
Pad Ownership (PAD_OWN_xxgpp_a_13)
Pad Ownership (PAD_OWN_xxgpp_a_14)
Pad Ownership (PAD_OWN_xxgpp_a_15)
Pad Ownership (PAD_OWN_xxgpp_a_16)
Pad Ownership (PAD_OWN_xxgpp_a_17)
Pad Ownership (PAD_OWN_vGPIO_TS0)
Pad Ownership (PAD_OWN_vGPIO_TS1)
Pad Ownership (PAD_OWN_vGPIO_THC0)
Pad Ownership (PAD_OWN_vGPIO_THC1)
Pad Ownership (PAD_OWN_vGPIO_THC2)
Pad Ownership (PAD_OWN_vGPIO_THC3)
Pad Configuration Lock (PADCFGLOCK_GPP_H_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_H_0)
Pad Configuration Lock (PADCFGLOCK_GPP_A_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_A_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_H_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_A_0)
Host Software Pad Ownership (HOSTSW_OWN_vGPIO_3_0)
GPI Interrupt Status (GPI_IS_GPP_H_0)
GPI Interrupt Status (GPI_IS_GPP_A_0)
GPI Interrupt Status (GPI_IS_vGPIO_3_0)
GPI Interrupt Enable (GPI_IE_GPP_H_0)
GPI Interrupt Enable (GPI_IE_GPP_A_0)
GPI Interrupt Enable (GPI_IE_vGPIO_3_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_H_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_0)
GPI General Purpose Events Status (GPI_GPE_STS_vGPIO_3_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_H_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_0)
GPI General Purpose Events Enable (GPI_GPE_EN_vGPIO_3_0)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_0)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_0)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_1)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_1)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_2)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_2)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_3)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_3)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_4)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_4)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_5)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_5)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_6)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_6)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_7)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_7)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_8)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_8)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_9)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_9)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_10)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_10)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_11)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_11)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_12)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_12)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_13)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_13)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_14)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_14)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_15)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_15)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_16)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_16)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_17)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_17)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_18)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_18)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_19)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_19)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_20)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_20)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_21)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_21)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_22)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_22)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_23)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_23)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_h_24)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_h_24)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_0)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_0)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_1)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_1)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_2)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_2)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_3)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_3)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_4)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_4)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_5)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_5)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_6)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_6)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_7)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_7)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_8)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_8)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_9)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_9)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_10)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_10)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_11)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_11)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_12)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_12)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_13)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_13)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_14)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_14)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_15)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_15)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_16)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_16)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_a_17)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_a_17)
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_TS0)
Pad Configuration DW1 (PAD_CFG_DW1_vGPIO_TS0)
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_TS1)
Pad Configuration DW1 (PAD_CFG_DW1_vGPIO_TS1)
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_THC0)
Pad Configuration DW1 (PAD_CFG_DW1_vGPIO_THC0)
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_THC1)
Pad Configuration DW1 (PAD_CFG_DW1_vGPIO_THC1)
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_THC2)
Pad Configuration DW1 (PAD_CFG_DW1_vGPIO_THC2)
Pad Configuration DW0 (PAD_CFG_DW0_vGPIO_THC3)
Pad Configuration DW1 (PAD_CFG_DW1_vGPIO_THC3)
GPIO Community 4
GPIO Community 4 Family Base Address (FAMBAR) Pad Base Address (PADBAR) Miscellaneous Configuration (MISCCFG) Pad Ownership (PAD_OWN_xxgpp_s_0) Pad Ownership (PAD_OWN_xxgpp_s_1) Pad Ownership (PAD_OWN_xxgpp_s_2) Pad Ownership (PAD_OWN_xxgpp_s_3) Pad Ownership (PAD_OWN_xxgpp_s_4) Pad Ownership (PAD_OWN_xxgpp_s_5) Pad Ownership (PAD_OWN_xxgpp_s_6) Pad Ownership (PAD_OWN_xxgpp_s_7) Pad Configuration Lock (PADCFGLOCK_GPP_S_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_S_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_S_0) GPI Interrupt Status (GPI_IS_GPP_S_0) GPI Interrupt Enable (GPI_IE_GPP_S_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_S_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_S_0) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_s_0) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_s_0) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_s_1) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_s_1) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_s_2) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_s_2) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_s_3) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_s_3) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_s_4) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_s_4) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_s_5) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_s_5) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_s_6) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_s_6) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_s_7) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_s_7)
Family Base Address (FAMBAR)
Pad Base Address (PADBAR)
Miscellaneous Configuration (MISCCFG)
Pad Ownership (PAD_OWN_xxgpp_s_0)
Pad Ownership (PAD_OWN_xxgpp_s_1)
Pad Ownership (PAD_OWN_xxgpp_s_2)
Pad Ownership (PAD_OWN_xxgpp_s_3)
Pad Ownership (PAD_OWN_xxgpp_s_4)
Pad Ownership (PAD_OWN_xxgpp_s_5)
Pad Ownership (PAD_OWN_xxgpp_s_6)
Pad Ownership (PAD_OWN_xxgpp_s_7)
Pad Configuration Lock (PADCFGLOCK_GPP_S_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_S_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_S_0)
GPI Interrupt Status (GPI_IS_GPP_S_0)
GPI Interrupt Enable (GPI_IE_GPP_S_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_S_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_S_0)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_s_0)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_s_0)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_s_1)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_s_1)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_s_2)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_s_2)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_s_3)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_s_3)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_s_4)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_s_4)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_s_5)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_s_5)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_s_6)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_s_6)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_s_7)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_s_7)
GPIO Community 5
GPIO Community 5 Family Base Address (FAMBAR) Pad Base Address (PADBAR) Miscellaneous Configuration (MISCCFG) Pad Ownership (PAD_OWN_xxgpp_b_0) Pad Ownership (PAD_OWN_xxgpp_b_1) Pad Ownership (PAD_OWN_xxgpp_b_2) Pad Ownership (PAD_OWN_xxgpp_b_3) Pad Ownership (PAD_OWN_xxgpp_b_4) Pad Ownership (PAD_OWN_xxgpp_b_5) Pad Ownership (PAD_OWN_xxgpp_b_6) Pad Ownership (PAD_OWN_xxgpp_b_7) Pad Ownership (PAD_OWN_xxgpp_b_8) Pad Ownership (PAD_OWN_xxgpp_b_9) Pad Ownership (PAD_OWN_xxgpp_b_10) Pad Ownership (PAD_OWN_xxgpp_b_11) Pad Ownership (PAD_OWN_xxgpp_b_12) Pad Ownership (PAD_OWN_xxgpp_b_13) Pad Ownership (PAD_OWN_xxgpp_b_14) Pad Ownership (PAD_OWN_xxgpp_b_15) Pad Ownership (PAD_OWN_xxgpp_b_16) Pad Ownership (PAD_OWN_xxgpp_b_17) Pad Ownership (PAD_OWN_xxgpp_b_18) Pad Ownership (PAD_OWN_xxgpp_b_19) Pad Ownership (PAD_OWN_xxgpp_b_20) Pad Ownership (PAD_OWN_xxgpp_b_21) Pad Ownership (PAD_OWN_xxgpp_b_22) Pad Ownership (PAD_OWN_xxgpp_b_23) Pad Ownership (PAD_OWN_xxgpp_b_24) Pad Ownership (PAD_OWN_xxgpp_b_25) Pad Ownership (PAD_OWN_xxgpp_d_0) Pad Ownership (PAD_OWN_xxgpp_d_1) Pad Ownership (PAD_OWN_xxgpp_d_2) Pad Ownership (PAD_OWN_xxgpp_d_3) Pad Ownership (PAD_OWN_xxgpp_d_4) Pad Ownership (PAD_OWN_xxgpp_d_5) Pad Ownership (PAD_OWN_xxgpp_d_6) Pad Ownership (PAD_OWN_xxgpp_d_7) Pad Ownership (PAD_OWN_xxgpp_d_8) Pad Ownership (PAD_OWN_xxgpp_d_9) Pad Ownership (PAD_OWN_xxgpp_d_10) Pad Ownership (PAD_OWN_xxgpp_d_11) Pad Ownership (PAD_OWN_xxgpp_d_12) Pad Ownership (PAD_OWN_xxgpp_d_13) Pad Ownership (PAD_OWN_xxgpp_d_14) Pad Ownership (PAD_OWN_xxgpp_d_15) Pad Ownership (PAD_OWN_xxgpp_d_16) Pad Ownership (PAD_OWN_xxgpp_d_17) Pad Ownership (PAD_OWN_xxgpp_d_18) Pad Ownership (PAD_OWN_xxgpp_d_19) Pad Ownership (PAD_OWN_xxgpp_d_20) Pad Ownership (PAD_OWN_xxgpp_d_21) Pad Ownership (PAD_OWN_xxgpp_d_22) Pad Ownership (PAD_OWN_xxgpp_d_23) Pad Ownership (PAD_OWN_xxgpp_d_24) Pad Ownership (PAD_OWN_xxgpp_d_25) Pad Configuration Lock (PADCFGLOCK_GPP_B_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_B_0) Pad Configuration Lock (PADCFGLOCK_GPP_D_0) Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_D_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_B_0) Host Software Pad Ownership (HOSTSW_OWN_GPP_D_0) GPI Interrupt Status (GPI_IS_GPP_B_0) GPI Interrupt Status (GPI_IS_GPP_D_0) GPI Interrupt Enable (GPI_IE_GPP_B_0) GPI Interrupt Enable (GPI_IE_GPP_D_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_D_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_B_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_D_0) SMI Status (GPI_SMI_STS_GPP_B_0) SMI Status (GPI_SMI_STS_GPP_D_0) SMI Enable (GPI_SMI_EN_GPP_B_0) SMI Enable (GPI_SMI_EN_GPP_D_0) NMI Status (GPI_NMI_STS_GPP_B_0) NMI Status (GPI_NMI_STS_GPP_D_0) NMI Enable (GPI_NMI_EN_GPP_B_0) NMI Enable (GPI_NMI_EN_GPP_D_0) PWM Control (PWMC) GPIO Serial Blink Enable (GP_SER_BLINK) GPIO Serial Blink Command/Status (GP_SER_CMDSTS) GPIO Serial Blink Data (GP_SER_DATA) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_0) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_0) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_1) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_1) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_2) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_2) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_3) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_3) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_4) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_4) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_5) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_5) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_6) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_6) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_7) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_7) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_8) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_8) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_9) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_9) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_10) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_10) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_11) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_11) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_12) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_12) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_13) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_13) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_14) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_14) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_15) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_15) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_16) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_16) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_17) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_17) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_18) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_18) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_19) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_19) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_20) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_20) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_21) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_21) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_22) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_22) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_23) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_23) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_24) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_24) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_25) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_25) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_0) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_0) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_1) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_1) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_2) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_2) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_3) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_3) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_4) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_4) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_5) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_5) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_6) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_6) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_7) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_7) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_8) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_8) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_9) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_9) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_10) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_10) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_11) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_11) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_12) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_12) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_13) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_13) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_14) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_14) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_15) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_15) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_16) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_16) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_17) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_17) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_18) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_18) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_19) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_19) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_20) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_20) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_21) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_21) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_22) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_22) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_23) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_23) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_24) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_24) Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_25) Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_25)
Family Base Address (FAMBAR)
Pad Base Address (PADBAR)
Miscellaneous Configuration (MISCCFG)
Pad Ownership (PAD_OWN_xxgpp_b_0)
Pad Ownership (PAD_OWN_xxgpp_b_1)
Pad Ownership (PAD_OWN_xxgpp_b_2)
Pad Ownership (PAD_OWN_xxgpp_b_3)
Pad Ownership (PAD_OWN_xxgpp_b_4)
Pad Ownership (PAD_OWN_xxgpp_b_5)
Pad Ownership (PAD_OWN_xxgpp_b_6)
Pad Ownership (PAD_OWN_xxgpp_b_7)
Pad Ownership (PAD_OWN_xxgpp_b_8)
Pad Ownership (PAD_OWN_xxgpp_b_9)
Pad Ownership (PAD_OWN_xxgpp_b_10)
Pad Ownership (PAD_OWN_xxgpp_b_11)
Pad Ownership (PAD_OWN_xxgpp_b_12)
Pad Ownership (PAD_OWN_xxgpp_b_13)
Pad Ownership (PAD_OWN_xxgpp_b_14)
Pad Ownership (PAD_OWN_xxgpp_b_15)
Pad Ownership (PAD_OWN_xxgpp_b_16)
Pad Ownership (PAD_OWN_xxgpp_b_17)
Pad Ownership (PAD_OWN_xxgpp_b_18)
Pad Ownership (PAD_OWN_xxgpp_b_19)
Pad Ownership (PAD_OWN_xxgpp_b_20)
Pad Ownership (PAD_OWN_xxgpp_b_21)
Pad Ownership (PAD_OWN_xxgpp_b_22)
Pad Ownership (PAD_OWN_xxgpp_b_23)
Pad Ownership (PAD_OWN_xxgpp_b_24)
Pad Ownership (PAD_OWN_xxgpp_b_25)
Pad Ownership (PAD_OWN_xxgpp_d_0)
Pad Ownership (PAD_OWN_xxgpp_d_1)
Pad Ownership (PAD_OWN_xxgpp_d_2)
Pad Ownership (PAD_OWN_xxgpp_d_3)
Pad Ownership (PAD_OWN_xxgpp_d_4)
Pad Ownership (PAD_OWN_xxgpp_d_5)
Pad Ownership (PAD_OWN_xxgpp_d_6)
Pad Ownership (PAD_OWN_xxgpp_d_7)
Pad Ownership (PAD_OWN_xxgpp_d_8)
Pad Ownership (PAD_OWN_xxgpp_d_9)
Pad Ownership (PAD_OWN_xxgpp_d_10)
Pad Ownership (PAD_OWN_xxgpp_d_11)
Pad Ownership (PAD_OWN_xxgpp_d_12)
Pad Ownership (PAD_OWN_xxgpp_d_13)
Pad Ownership (PAD_OWN_xxgpp_d_14)
Pad Ownership (PAD_OWN_xxgpp_d_15)
Pad Ownership (PAD_OWN_xxgpp_d_16)
Pad Ownership (PAD_OWN_xxgpp_d_17)
Pad Ownership (PAD_OWN_xxgpp_d_18)
Pad Ownership (PAD_OWN_xxgpp_d_19)
Pad Ownership (PAD_OWN_xxgpp_d_20)
Pad Ownership (PAD_OWN_xxgpp_d_21)
Pad Ownership (PAD_OWN_xxgpp_d_22)
Pad Ownership (PAD_OWN_xxgpp_d_23)
Pad Ownership (PAD_OWN_xxgpp_d_24)
Pad Ownership (PAD_OWN_xxgpp_d_25)
Pad Configuration Lock (PADCFGLOCK_GPP_B_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_B_0)
Pad Configuration Lock (PADCFGLOCK_GPP_D_0)
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_D_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_B_0)
Host Software Pad Ownership (HOSTSW_OWN_GPP_D_0)
GPI Interrupt Status (GPI_IS_GPP_B_0)
GPI Interrupt Status (GPI_IS_GPP_D_0)
GPI Interrupt Enable (GPI_IE_GPP_B_0)
GPI Interrupt Enable (GPI_IE_GPP_D_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_0)
GPI General Purpose Events Status (GPI_GPE_STS_GPP_D_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_B_0)
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_D_0)
SMI Status (GPI_SMI_STS_GPP_B_0)
SMI Status (GPI_SMI_STS_GPP_D_0)
SMI Enable (GPI_SMI_EN_GPP_B_0)
SMI Enable (GPI_SMI_EN_GPP_D_0)
NMI Status (GPI_NMI_STS_GPP_B_0)
NMI Status (GPI_NMI_STS_GPP_D_0)
NMI Enable (GPI_NMI_EN_GPP_B_0)
NMI Enable (GPI_NMI_EN_GPP_D_0)
PWM Control (PWMC)
GPIO Serial Blink Enable (GP_SER_BLINK)
GPIO Serial Blink Command/Status (GP_SER_CMDSTS)
GPIO Serial Blink Data (GP_SER_DATA)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_0)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_0)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_1)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_1)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_2)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_2)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_3)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_3)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_4)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_4)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_5)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_5)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_6)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_6)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_7)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_7)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_8)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_8)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_9)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_9)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_10)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_10)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_11)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_11)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_12)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_12)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_13)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_13)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_14)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_14)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_15)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_15)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_16)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_16)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_17)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_17)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_18)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_18)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_19)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_19)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_20)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_20)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_21)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_21)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_22)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_22)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_23)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_23)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_24)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_24)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_b_25)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_b_25)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_0)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_0)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_1)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_1)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_2)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_2)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_3)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_3)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_4)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_4)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_5)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_5)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_6)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_6)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_7)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_7)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_8)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_8)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_9)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_9)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_10)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_10)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_11)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_11)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_12)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_12)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_13)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_13)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_14)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_14)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_15)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_15)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_16)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_16)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_17)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_17)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_18)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_18)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_19)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_19)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_20)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_20)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_21)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_21)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_22)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_22)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_23)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_23)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_24)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_24)
Pad Configuration DW0 (PAD_CFG_DW0_xxgpp_d_25)
Pad Configuration DW1 (PAD_CFG_DW1_xxgpp_d_25)
GSPI Additional MMIO
GSPI Additional MMIO REG CLOCKS (CLOCKS) REG RESETS (RESETS) REG ACTIVELTR_VALUE (ACTIVELTR_VALUE) REG IDLELTR_VALUE (IDLELTR_VALUE) REG TX_BIT_COUNT (TX_BIT_COUNT) REG RX_BIT_COUNT (RX_BIT_COUNT) REG SSP_REG (SSP_REG) REG SPI_CS_CONTROL (SPI_CS_CONTROL) REG SW_SCRATCH_0 (SW_SCRATCH_0) REG SW_SCRATCH_1 (SW_SCRATCH_1) REG SW_SCRATCH_2 (SW_SCRATCH_2) REG SW_SCRATCH_3 (SW_SCRATCH_3) REG CLOCK_GATE (CLOCK_GATE) REG REMAP_ADDR_LO (REMAP_ADDR_LO) REG REMAP_ADDR_HI (REMAP_ADDR_HI) REG DEVIDLE_CONTROL (DEVIDLE_CONTROL) REG DEL_RX_CLK (DEL_RX_CLK) REG CAPABLITIES (CAPABLITIES)
REG CLOCKS (CLOCKS)
REG RESETS (RESETS)
REG ACTIVELTR_VALUE (ACTIVELTR_VALUE)
REG IDLELTR_VALUE (IDLELTR_VALUE)
REG TX_BIT_COUNT (TX_BIT_COUNT)
REG RX_BIT_COUNT (RX_BIT_COUNT)
REG SSP_REG (SSP_REG)
REG SPI_CS_CONTROL (SPI_CS_CONTROL)
REG SW_SCRATCH_0 (SW_SCRATCH_0)
REG SW_SCRATCH_1 (SW_SCRATCH_1)
REG SW_SCRATCH_2 (SW_SCRATCH_2)
REG SW_SCRATCH_3 (SW_SCRATCH_3)
REG CLOCK_GATE (CLOCK_GATE)
REG REMAP_ADDR_LO (REMAP_ADDR_LO)
REG REMAP_ADDR_HI (REMAP_ADDR_HI)
REG DEVIDLE_CONTROL (DEVIDLE_CONTROL)
REG DEL_RX_CLK (DEL_RX_CLK)
REG CAPABLITIES (CAPABLITIES)
GSPI DMA Controller
GSPI DMA Controller REG SAR_LO0 (SAR_LO0) REG SAR_HI0 (SAR_HI0) REG DAR_LO0 (DAR_LO0) REG DAR_HI0 (DAR_HI0) REG LLP_LO0 (LLP_LO0) REG LLP_HI0 (LLP_HI0) REG CTL_LO0 (CTL_LO0) REG CTL_HI0 (CTL_HI0) REG SSTAT0 (SSTAT0) REG DSTAT0 (DSTAT0) REG SSTATAR_LO0 (SSTATAR_LO0) REG SSTATAR_HI0 (SSTATAR_HI0) REG DSTATAR_LO0 (DSTATAR_LO0) REG DSTATAR_HI0 (DSTATAR_HI0) REG CFG_LO0 (CFG_LO0) REG CFG_HI0 (CFG_HI0) REG SGR0 (SGR0) REG DSR0 (DSR0) REG SAR_LO1 (SAR_LO1) REG SAR_HI1 (SAR_HI1) REG DAR_LO1 (DAR_LO1) REG DAR_HI1 (DAR_HI1) REG LLP_LO1 (LLP_LO1) REG LLP_HI1 (LLP_HI1) REG CTL_LO1 (CTL_LO1) REG CTL_HI1 (CTL_HI1) REG SSTAT1 (SSTAT1) REG DSTAT1 (DSTAT1) REG SSTATAR_LO1 (SSTATAR_LO1) REG SSTATAR_HI1 (SSTATAR_HI1) REG DSTATAR_LO1 (DSTATAR_LO1) REG DSTATAR_HI1 (DSTATAR_HI1) REG CFG_LO1 (CFG_LO1) REG CFG_HI1 (CFG_HI1) REG SGR1 (SGR1) REG DSR1 (DSR1) REG RawTfr (RawTfr) REG RawBlock (RawBlock) REG RawSrcTran (RawSrcTran) REG RawDstTran (RawDstTran) REG RawErr (RawErr) REG StatusTfr (StatusTfr) REG StatusBlock (StatusBlock) REG StatusSrcTran (StatusSrcTran) REG StatusDstTran (StatusDstTran) REG StatusErr (StatusErr) REG MaskTfr (MaskTfr) REG MaskBlock (MaskBlock) REG MaskSrcTran (MaskSrcTran) REG MaskDstTran (MaskDstTran) REG MaskErr (MaskErr) REG ClearTfr (ClearTfr) REG ClearBlock (ClearBlock) REG ClearSrcTran (ClearSrcTran) REG ClearDstTran (ClearDstTran) REG ClearErr (ClearErr) REG StatusInt (StatusInt) REG DmaCfgReg (DmaCfgReg) REG ChEnReg (ChEnReg) REG GLOBAL_CFG (GLOBAL_CFG)
REG SAR_LO0 (SAR_LO0)
REG SAR_HI0 (SAR_HI0)
REG DAR_LO0 (DAR_LO0)
REG DAR_HI0 (DAR_HI0)
REG LLP_LO0 (LLP_LO0)
REG LLP_HI0 (LLP_HI0)
REG CTL_LO0 (CTL_LO0)
REG CTL_HI0 (CTL_HI0)
REG SSTAT0 (SSTAT0)
REG DSTAT0 (DSTAT0)
REG SSTATAR_LO0 (SSTATAR_LO0)
REG SSTATAR_HI0 (SSTATAR_HI0)
REG DSTATAR_LO0 (DSTATAR_LO0)
REG DSTATAR_HI0 (DSTATAR_HI0)
REG CFG_LO0 (CFG_LO0)
REG CFG_HI0 (CFG_HI0)
REG SGR0 (SGR0)
REG DSR0 (DSR0)
REG SAR_LO1 (SAR_LO1)
REG SAR_HI1 (SAR_HI1)
REG DAR_LO1 (DAR_LO1)
REG DAR_HI1 (DAR_HI1)
REG LLP_LO1 (LLP_LO1)
REG LLP_HI1 (LLP_HI1)
REG CTL_LO1 (CTL_LO1)
REG CTL_HI1 (CTL_HI1)
REG SSTAT1 (SSTAT1)
REG DSTAT1 (DSTAT1)
REG SSTATAR_LO1 (SSTATAR_LO1)
REG SSTATAR_HI1 (SSTATAR_HI1)
REG DSTATAR_LO1 (DSTATAR_LO1)
REG DSTATAR_HI1 (DSTATAR_HI1)
REG CFG_LO1 (CFG_LO1)
REG CFG_HI1 (CFG_HI1)
REG SGR1 (SGR1)
REG DSR1 (DSR1)
REG RawTfr (RawTfr)
REG RawBlock (RawBlock)
REG RawSrcTran (RawSrcTran)
REG RawDstTran (RawDstTran)
REG RawErr (RawErr)
REG StatusTfr (StatusTfr)
REG StatusBlock (StatusBlock)
REG StatusSrcTran (StatusSrcTran)
REG StatusDstTran (StatusDstTran)
REG StatusErr (StatusErr)
REG MaskTfr (MaskTfr)
REG MaskBlock (MaskBlock)
REG MaskSrcTran (MaskSrcTran)
REG MaskDstTran (MaskDstTran)
REG MaskErr (MaskErr)
REG ClearTfr (ClearTfr)
REG ClearBlock (ClearBlock)
REG ClearSrcTran (ClearSrcTran)
REG ClearDstTran (ClearDstTran)
REG ClearErr (ClearErr)
REG StatusInt (StatusInt)
REG DmaCfgReg (DmaCfgReg)
REG ChEnReg (ChEnReg)
REG GLOBAL_CFG (GLOBAL_CFG)
GSPI PCI Configuration (D30:F2/3, D18:F6)
GSPI PCI Configuration (D30:F2/3, D18:F6) Device Id And Vendor Id Register (DEVVENDID) Status And Command (STATUSCOMMAND) Revision Id And Class Code (REVCLASSCODE) Cache Line Latency Header And Bist (CLLATHEADERBIST) Base Address Register (BAR) Base Address Register High (BAR_HIGH) Base Address Register1 (BAR1) Base Address Register1 High (BAR1_HIGH) Subsystem Vendor And Subsystem Id (SUBSYSTEMID) Expansion Rom Base Address (EXPANSION_ROM_BASEADDR) Capabilities Pointer (CAPABILITYPTR) Interrupt Register (INTERRUPTREG) Power Management Capability Id (POWERCAPID) Power Management Control And Status Register (PMECTRLSTATUS) Pci Device Idle Vendor Capability Register (PCIDEVIDLE_CAP_RECORD) Vendor Specific Extended Capability Register (DEVID_VEND_SPECIFIC_REG) Software Ltr Update Mmio Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG) Device Idle Pointer Register (DEVICE_IDLE_POINTER_REG) D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG) General Purpose Read Write Register1 (GEN_PCI_REGRW1) General Purpose Read Write Register2 (GEN_PCI_REGRW2) General Purpose Read Write Register3 (GEN_PCI_REGRW3) General Purpose Read Write Register4 (GEN_PCI_REGRW4) General Purpose Input Register (GEN_INPUT_REG)
Device Id And Vendor Id Register (DEVVENDID)
Status And Command (STATUSCOMMAND)
Revision Id And Class Code (REVCLASSCODE)
Cache Line Latency Header And Bist (CLLATHEADERBIST)
Base Address Register (BAR)
Base Address Register High (BAR_HIGH)
Base Address Register1 (BAR1)
Base Address Register1 High (BAR1_HIGH)
Subsystem Vendor And Subsystem Id (SUBSYSTEMID)
Expansion Rom Base Address (EXPANSION_ROM_BASEADDR)
Capabilities Pointer (CAPABILITYPTR)
Interrupt Register (INTERRUPTREG)
Power Management Capability Id (POWERCAPID)
Power Management Control And Status Register (PMECTRLSTATUS)
Pci Device Idle Vendor Capability Register (PCIDEVIDLE_CAP_RECORD)
Vendor Specific Extended Capability Register (DEVID_VEND_SPECIFIC_REG)
Software Ltr Update Mmio Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device Idle Pointer Register (DEVICE_IDLE_POINTER_REG)
D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG)
General Purpose Read Write Register1 (GEN_PCI_REGRW1)
General Purpose Read Write Register2 (GEN_PCI_REGRW2)
General Purpose Read Write Register3 (GEN_PCI_REGRW3)
General Purpose Read Write Register4 (GEN_PCI_REGRW4)
General Purpose Input Register (GEN_INPUT_REG)
GSPI0 MMIO
GSPI0 MMIO REG SSCR0 (SSCR0) REG SSCR1 (SSCR1) REG SSSR (SSSR) REG SSITR (SSITR) REG SSDR (SSDR) REG SSTO (SSTO) REG SITF (SITF) REG SIRF (SIRF)
REG SSCR0 (SSCR0)
REG SSCR1 (SSCR1)
REG SSSR (SSSR)
REG SSITR (SSITR)
REG SSDR (SSDR)
REG SSTO (SSTO)
REG SITF (SITF)
REG SIRF (SIRF)
High Precision Event Timer (HPET) MMIO
High Precision Event Timer (HPET) MMIO General Capabilities and ID Register (GEN_CAP_ID) General Config Register (GEN_CFG) General Interrupt Status Register (GEN_INT_STS) Main Counter Value (MAIN_CNTR) Timer 0 Config and Capabilities (TMR0_CNF_CAP) Timer 0 Comparator Value (TMR0_CMP_VAL) Timer 0 FSB Interrupt Rout Register (TMR0_FSB_INT_ROUT) Timer 1 Config and Capabilities (TMR1_CNF_CAP) Timer 1 Comparator Value (TMR1_CMP_VAL) Timer 1 FSB Interrupt Rout Register (TMR1_FSB_INT_ROUT) Timer 2 Config and Capabilities (TMR2_CNF_CAP) Timer 2 Comparator Value (TMR2_CMP_VAL) Timer 2 FSB Interrupt Rout Register (TMR2_FSB_INT_ROUT) Timer 3 Config and Capabilities (TMR3_CNF_CAP) Timer 3 Comparator Value (TMR3_CMP_VAL) Timer 3 FSB Interrupt Rout Register (TMR3_FSB_INT_ROUT) Timer 4 Config and Capabilities (TMR4_CNF_CAP) Timer 4 Comparator Value (TMR4_CMP_VAL) Timer 4 FSB Interrupt Rout Register (TMR4_FSB_INT_ROUT) Timer 5 Config and Capabilities (TMR5_CNF_CAP) Timer 5 Comparator Value (TMR5_CMP_VAL) Timer 5 FSB Interrupt Rout Register (TMR5_FSB_INT_ROUT) Timer 6 Config and Capabilities (TMR6_CNF_CAP) Timer 6 Comparator Value (TMR6_CMP_VAL) Timer 6 FSB Interrupt Rout Register (TMR6_FSB_INT_ROUT) Timer 7 Config and Capabilities (TMR7_CNF_CAP) Timer 7 Comparator Value (TMR7_CMP_VAL) Timer 7 FSB Interrupt Rout Register (TMR7_FSB_INT_ROUT)
General Capabilities and ID Register (GEN_CAP_ID)
General Config Register (GEN_CFG)
General Interrupt Status Register (GEN_INT_STS)
Main Counter Value (MAIN_CNTR)
Timer 0 Config and Capabilities (TMR0_CNF_CAP)
Timer 0 Comparator Value (TMR0_CMP_VAL)
Timer 0 FSB Interrupt Rout Register (TMR0_FSB_INT_ROUT)
Timer 1 Config and Capabilities (TMR1_CNF_CAP)
Timer 1 Comparator Value (TMR1_CMP_VAL)
Timer 1 FSB Interrupt Rout Register (TMR1_FSB_INT_ROUT)
Timer 2 Config and Capabilities (TMR2_CNF_CAP)
Timer 2 Comparator Value (TMR2_CMP_VAL)
Timer 2 FSB Interrupt Rout Register (TMR2_FSB_INT_ROUT)
Timer 3 Config and Capabilities (TMR3_CNF_CAP)
Timer 3 Comparator Value (TMR3_CMP_VAL)
Timer 3 FSB Interrupt Rout Register (TMR3_FSB_INT_ROUT)
Timer 4 Config and Capabilities (TMR4_CNF_CAP)
Timer 4 Comparator Value (TMR4_CMP_VAL)
Timer 4 FSB Interrupt Rout Register (TMR4_FSB_INT_ROUT)
Timer 5 Config and Capabilities (TMR5_CNF_CAP)
Timer 5 Comparator Value (TMR5_CMP_VAL)
Timer 5 FSB Interrupt Rout Register (TMR5_FSB_INT_ROUT)
Timer 6 Config and Capabilities (TMR6_CNF_CAP)
Timer 6 Comparator Value (TMR6_CMP_VAL)
Timer 6 FSB Interrupt Rout Register (TMR6_FSB_INT_ROUT)
Timer 7 Config and Capabilities (TMR7_CNF_CAP)
Timer 7 Comparator Value (TMR7_CMP_VAL)
Timer 7 FSB Interrupt Rout Register (TMR7_FSB_INT_ROUT)
I/O Trap
I/O Trap PSTH Control Register (PSTHCTL) Trap Status Register (TRPSTS) Trapped Cycle Register (TRPCYC1) Trapped Write Data Register (TRPWRDATA1) I/O Trap Registers 1 (IOTRP1_1) I/O Trap Registers 1 (IOTRP1_2) I/O Trap Registers 2 (IOTRP2_1) I/O Trap Registers 2 (IOTRP2_2) I/O Trap Registers 3 (IOTRP3_1) I/O Trap Registers 3 (IOTRP3_2) I/O Trap Registers 4 (IOTRP4_1) I/O Trap Registers 4 (IOTRP4_2)
PSTH Control Register (PSTHCTL)
Trap Status Register (TRPSTS)
Trapped Cycle Register (TRPCYC1)
Trapped Write Data Register (TRPWRDATA1)
I/O Trap Registers 1 (IOTRP1_1)
I/O Trap Registers 1 (IOTRP1_2)
I/O Trap Registers 2 (IOTRP2_1)
I/O Trap Registers 2 (IOTRP2_2)
I/O Trap Registers 3 (IOTRP3_1)
I/O Trap Registers 3 (IOTRP3_2)
I/O Trap Registers 4 (IOTRP4_1)
I/O Trap Registers 4 (IOTRP4_2)
I2C Additional MMIO
I2C Additional MMIO (RESETS) General (GENERAL) Active LTR Value (ACTIVELTR_VALUE) Idle LTR Value (IDLELTR_VALUE) TX ACK Counts (TX_ACK_COUNT) (RX_BYTE_COUNT) Interrupt Status for Tx Complete (TX_COMPLETE_INTR_STAT) Tx Complete Interrupt Clear (TX_COMPLETE_INTR_CLR) SW scratch register 0 (SW_SCRATCH_0) SW scratch register 1 (SW_SCRATCH_1) SW scratch register 2 (SW_SCRATCH_2) SW scratch register 3 (SW_SCRATCH_3) Clock Gate (CLOCK_GATE) Remap Address Low (REMAP_ADDR_LO) Remap Address High (REMAP_ADDR_HI) Device Idle Control (DEVIDLE_CONTROL) Capabilities (CAPABLITIES)
(RESETS)
General (GENERAL)
Active LTR Value (ACTIVELTR_VALUE)
Idle LTR Value (IDLELTR_VALUE)
TX ACK Counts (TX_ACK_COUNT)
(RX_BYTE_COUNT)
Interrupt Status for Tx Complete (TX_COMPLETE_INTR_STAT)
Tx Complete Interrupt Clear (TX_COMPLETE_INTR_CLR)
SW scratch register 0 (SW_SCRATCH_0)
SW scratch register 1 (SW_SCRATCH_1)
SW scratch register 2 (SW_SCRATCH_2)
SW scratch register 3 (SW_SCRATCH_3)
Clock Gate (CLOCK_GATE)
Remap Address Low (REMAP_ADDR_LO)
Remap Address High (REMAP_ADDR_HI)
Device Idle Control (DEVIDLE_CONTROL)
Capabilities (CAPABLITIES)
I2C DMA Controller
I2C DMA Controller REG SAR_LO0 (SAR_LO0) REG SAR_HI0 (SAR_HI0) REG DAR_LO0 (DAR_LO0) REG DAR_HI0 (DAR_HI0) REG LLP_LO0 (LLP_LO0) REG LLP_HI0 (LLP_HI0) REG CTL_LO0 (CTL_LO0) REG CTL_HI0 (CTL_HI0) REG SSTAT0 (SSTAT0) REG DSTAT0 (DSTAT0) REG SSTATAR_LO0 (SSTATAR_LO0) REG SSTATAR_HI0 (SSTATAR_HI0) REG DSTATAR_LO0 (DSTATAR_LO0) REG DSTATAR_HI0 (DSTATAR_HI0) REG CFG_LO0 (CFG_LO0) REG CFG_HI0 (CFG_HI0) REG SGR0 (SGR0) REG DSR0 (DSR0) REG SAR_LO1 (SAR_LO1) REG SAR_HI1 (SAR_HI1) REG DAR_LO1 (DAR_LO1) REG DAR_HI1 (DAR_HI1) REG LLP_LO1 (LLP_LO1) REG LLP_HI1 (LLP_HI1) REG CTL_LO1 (CTL_LO1) REG CTL_HI1 (CTL_HI1) REG SSTAT1 (SSTAT1) REG DSTAT1 (DSTAT1) REG SSTATAR_LO1 (SSTATAR_LO1) REG SSTATAR_HI1 (SSTATAR_HI1) REG DSTATAR_LO1 (DSTATAR_LO1) REG DSTATAR_HI1 (DSTATAR_HI1) REG CFG_LO1 (CFG_LO1) REG CFG_HI1 (CFG_HI1) REG SGR1 (SGR1) REG DSR1 (DSR1) REG RawTfr (RawTfr) REG RawBlock (RawBlock) REG RawSrcTran (RawSrcTran) REG RawDstTran (RawDstTran) REG RawErr (RawErr) REG StatusTfr (StatusTfr) REG StatusBlock (StatusBlock) REG StatusSrcTran (StatusSrcTran) REG StatusDstTran (StatusDstTran) REG StatusErr (StatusErr) REG MaskTfr (MaskTfr) REG MaskBlock (MaskBlock) REG MaskSrcTran (MaskSrcTran) REG MaskDstTran (MaskDstTran) REG MaskErr (MaskErr) REG ClearTfr (ClearTfr) REG ClearBlock (ClearBlock) REG ClearSrcTran (ClearSrcTran) REG ClearDstTran (ClearDstTran) REG ClearErr (ClearErr) REG StatusInt (StatusInt) REG DmaCfgReg (DmaCfgReg) REG ChEnReg (ChEnReg) REG GLOBAL_CFG (GLOBAL_CFG)
REG SAR_LO0 (SAR_LO0)
REG SAR_HI0 (SAR_HI0)
REG DAR_LO0 (DAR_LO0)
REG DAR_HI0 (DAR_HI0)
REG LLP_LO0 (LLP_LO0)
REG LLP_HI0 (LLP_HI0)
REG CTL_LO0 (CTL_LO0)
REG CTL_HI0 (CTL_HI0)
REG SSTAT0 (SSTAT0)
REG DSTAT0 (DSTAT0)
REG SSTATAR_LO0 (SSTATAR_LO0)
REG SSTATAR_HI0 (SSTATAR_HI0)
REG DSTATAR_LO0 (DSTATAR_LO0)
REG DSTATAR_HI0 (DSTATAR_HI0)
REG CFG_LO0 (CFG_LO0)
REG CFG_HI0 (CFG_HI0)
REG SGR0 (SGR0)
REG DSR0 (DSR0)
REG SAR_LO1 (SAR_LO1)
REG SAR_HI1 (SAR_HI1)
REG DAR_LO1 (DAR_LO1)
REG DAR_HI1 (DAR_HI1)
REG LLP_LO1 (LLP_LO1)
REG LLP_HI1 (LLP_HI1)
REG CTL_LO1 (CTL_LO1)
REG CTL_HI1 (CTL_HI1)
REG SSTAT1 (SSTAT1)
REG DSTAT1 (DSTAT1)
REG SSTATAR_LO1 (SSTATAR_LO1)
REG SSTATAR_HI1 (SSTATAR_HI1)
REG DSTATAR_LO1 (DSTATAR_LO1)
REG DSTATAR_HI1 (DSTATAR_HI1)
REG CFG_LO1 (CFG_LO1)
REG CFG_HI1 (CFG_HI1)
REG SGR1 (SGR1)
REG DSR1 (DSR1)
REG RawTfr (RawTfr)
REG RawBlock (RawBlock)
REG RawSrcTran (RawSrcTran)
REG RawDstTran (RawDstTran)
REG RawErr (RawErr)
REG StatusTfr (StatusTfr)
REG StatusBlock (StatusBlock)
REG StatusSrcTran (StatusSrcTran)
REG StatusDstTran (StatusDstTran)
REG StatusErr (StatusErr)
REG MaskTfr (MaskTfr)
REG MaskBlock (MaskBlock)
REG MaskSrcTran (MaskSrcTran)
REG MaskDstTran (MaskDstTran)
REG MaskErr (MaskErr)
REG ClearTfr (ClearTfr)
REG ClearBlock (ClearBlock)
REG ClearSrcTran (ClearSrcTran)
REG ClearDstTran (ClearDstTran)
REG ClearErr (ClearErr)
REG StatusInt (StatusInt)
REG DmaCfgReg (DmaCfgReg)
REG ChEnReg (ChEnReg)
REG GLOBAL_CFG (GLOBAL_CFG)
I2C MMIO
I2C MMIO REG IC_CON (IC_CON) REG IC_TAR (IC_TAR) REG IC_SAR (IC_SAR) REG IC_HS_MADDR (IC_HS_MADDR) REG IC_DATA_CMD (IC_DATA_CMD) REG IC_SS_SCL_HCNT (IC_SS_SCL_HCNT) REG IC_SS_SCL_LCNT (IC_SS_SCL_LCNT) REG IC_FS_SCL_HCNT (IC_FS_SCL_HCNT) REG IC_FS_SCL_LCNT (IC_FS_SCL_LCNT) REG IC_HS_SCL_HCNT (IC_HS_SCL_HCNT) REG IC_HS_SCL_LCNT (IC_HS_SCL_LCNT) REG IC_INTR_STAT (IC_INTR_STAT) REG IC_INTR_MASK (IC_INTR_MASK) REG IC_RAW_INTR_STAT (IC_RAW_INTR_STAT) REG IC_RX_TL (IC_RX_TL) REG IC_TX_TL (IC_TX_TL) REG IC_CLR_INTR (IC_CLR_INTR) REG IC_CLR_RX_UNDER (IC_CLR_RX_UNDER) REG IC_CLR_RX_OVER (IC_CLR_RX_OVER) REG IC_CLR_TX_OVER (IC_CLR_TX_OVER) REG IC_CLR_RD_REQ (IC_CLR_RD_REQ) REG IC_CLR_TX_ABRT (IC_CLR_TX_ABRT) REG IC_CLR_RX_DONE (IC_CLR_RX_DONE) REG IC_CLR_ACTIVITY (IC_CLR_ACTIVITY) REG IC_CLR_STOP_DET (IC_CLR_STOP_DET) REG IC_CLR_START_DET (IC_CLR_START_DET) REG IC_CLR_GEN_CALL (IC_CLR_GEN_CALL) REG IC_ENABLE (IC_ENABLE) REG IC_STATUS (IC_STATUS) REG IC_TXFLR (IC_TXFLR) REG IC_RXFLR (IC_RXFLR) REG IC_SDA_HOLD (IC_SDA_HOLD) REG IC_TX_ABRT_SOURCE (IC_TX_ABRT_SOURCE) REG IC_SLV_DATA_NACK_ONLY (IC_SLV_DATA_NACK_ONLY) REG IC_DMA_CR (IC_DMA_CR) REG IC_DMA_TDLR (IC_DMA_TDLR) REG IC_DMA_RDLR (IC_DMA_RDLR) REG IC_SDA_SETUP (IC_SDA_SETUP) REG IC_ACK_GENERAL_CALL (IC_ACK_GENERAL_CALL) REG IC_ENABLE_STATUS (IC_ENABLE_STATUS) REG IC_FS_SPKLEN (IC_FS_SPKLEN) REG IC_HS_SPKLEN (IC_HS_SPKLEN) REG IC_COMP_PARAM_1 (IC_COMP_PARAM_1) REG IC_COMP_VERSION (IC_COMP_VERSION) REG IC_COMP_TYPE (IC_COMP_TYPE)
REG IC_CON (IC_CON)
REG IC_TAR (IC_TAR)
REG IC_SAR (IC_SAR)
REG IC_HS_MADDR (IC_HS_MADDR)
REG IC_DATA_CMD (IC_DATA_CMD)
REG IC_SS_SCL_HCNT (IC_SS_SCL_HCNT)
REG IC_SS_SCL_LCNT (IC_SS_SCL_LCNT)
REG IC_FS_SCL_HCNT (IC_FS_SCL_HCNT)
REG IC_FS_SCL_LCNT (IC_FS_SCL_LCNT)
REG IC_HS_SCL_HCNT (IC_HS_SCL_HCNT)
REG IC_HS_SCL_LCNT (IC_HS_SCL_LCNT)
REG IC_INTR_STAT (IC_INTR_STAT)
REG IC_INTR_MASK (IC_INTR_MASK)
REG IC_RAW_INTR_STAT (IC_RAW_INTR_STAT)
REG IC_RX_TL (IC_RX_TL)
REG IC_TX_TL (IC_TX_TL)
REG IC_CLR_INTR (IC_CLR_INTR)
REG IC_CLR_RX_UNDER (IC_CLR_RX_UNDER)
REG IC_CLR_RX_OVER (IC_CLR_RX_OVER)
REG IC_CLR_TX_OVER (IC_CLR_TX_OVER)
REG IC_CLR_RD_REQ (IC_CLR_RD_REQ)
REG IC_CLR_TX_ABRT (IC_CLR_TX_ABRT)
REG IC_CLR_RX_DONE (IC_CLR_RX_DONE)
REG IC_CLR_ACTIVITY (IC_CLR_ACTIVITY)
REG IC_CLR_STOP_DET (IC_CLR_STOP_DET)
REG IC_CLR_START_DET (IC_CLR_START_DET)
REG IC_CLR_GEN_CALL (IC_CLR_GEN_CALL)
REG IC_ENABLE (IC_ENABLE)
REG IC_STATUS (IC_STATUS)
REG IC_TXFLR (IC_TXFLR)
REG IC_RXFLR (IC_RXFLR)
REG IC_SDA_HOLD (IC_SDA_HOLD)
REG IC_TX_ABRT_SOURCE (IC_TX_ABRT_SOURCE)
REG IC_SLV_DATA_NACK_ONLY (IC_SLV_DATA_NACK_ONLY)
REG IC_DMA_CR (IC_DMA_CR)
REG IC_DMA_TDLR (IC_DMA_TDLR)
REG IC_DMA_RDLR (IC_DMA_RDLR)
REG IC_SDA_SETUP (IC_SDA_SETUP)
REG IC_ACK_GENERAL_CALL (IC_ACK_GENERAL_CALL)
REG IC_ENABLE_STATUS (IC_ENABLE_STATUS)
REG IC_FS_SPKLEN (IC_FS_SPKLEN)
REG IC_HS_SPKLEN (IC_HS_SPKLEN)
REG IC_COMP_PARAM_1 (IC_COMP_PARAM_1)
REG IC_COMP_VERSION (IC_COMP_VERSION)
REG IC_COMP_TYPE (IC_COMP_TYPE)
I2C PCI Configuration (D21:F0/1/2/3; D25:F0/1)
I2C PCI Configuration (D21:F0/1/2/3; D25:F0/1) Device Id And Vendor Id Register (DEVVENDID) Status And Command (STATUSCOMMAND) Revision Id And Class Code (REVCLASSCODE) Cache Line Latency Header And Bist (CLLATHEADERBIST) Base Address Register (BAR) Base Address Register High (BAR_HIGH) Base Address Register1 (BAR1) Base Address Register1 High (BAR1_HIGH) Subsystem Vendor And Subsystem Id (SUBSYSTEMID) Expansion Rom Base Address (EXPANSION_ROM_BASEADDR) Capabilities Pointer (CAPABILITYPTR) Interrupt Register (INTERRUPTREG) Power Management Capability Id (POWERCAPID) Power Management Control And Status Register (PMECTRLSTATUS) Pci Device Idle Vendor Capability Register (PCIDEVIDLE_CAP_RECORD) Vendor Specific Extended Capability Register (DEVID_VEND_SPECIFIC_REG) Software Ltr Update Mmio Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG) Device Idle Pointer Register (DEVICE_IDLE_POINTER_REG) D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG) General Purpose Read Write Register1 (GEN_PCI_REGRW1) General Purpose Read Write Register2 (GEN_PCI_REGRW2) General Purpose Read Write Register3 (GEN_PCI_REGRW3) General Purpose Read Write Register4 (GEN_PCI_REGRW4) General Purpose Input Register (GEN_INPUT_REG)
Device Id And Vendor Id Register (DEVVENDID)
Status And Command (STATUSCOMMAND)
Revision Id And Class Code (REVCLASSCODE)
Cache Line Latency Header And Bist (CLLATHEADERBIST)
Base Address Register (BAR)
Base Address Register High (BAR_HIGH)
Base Address Register1 (BAR1)
Base Address Register1 High (BAR1_HIGH)
Subsystem Vendor And Subsystem Id (SUBSYSTEMID)
Expansion Rom Base Address (EXPANSION_ROM_BASEADDR)
Capabilities Pointer (CAPABILITYPTR)
Interrupt Register (INTERRUPTREG)
Power Management Capability Id (POWERCAPID)
Power Management Control And Status Register (PMECTRLSTATUS)
Pci Device Idle Vendor Capability Register (PCIDEVIDLE_CAP_RECORD)
Vendor Specific Extended Capability Register (DEVID_VEND_SPECIFIC_REG)
Software Ltr Update Mmio Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device Idle Pointer Register (DEVICE_IDLE_POINTER_REG)
D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG)
General Purpose Read Write Register1 (GEN_PCI_REGRW1)
General Purpose Read Write Register2 (GEN_PCI_REGRW2)
General Purpose Read Write Register3 (GEN_PCI_REGRW3)
General Purpose Read Write Register4 (GEN_PCI_REGRW4)
General Purpose Input Register (GEN_INPUT_REG)
I3C Additional MMIO
I3C Additional MMIO REG SAR_LO0 (SAR_LO0) REG SAR_HI0 (SAR_HI0) REG DAR_LO0 (DAR_LO0) REG DAR_HI0 (DAR_HI0) REG LLP_LO0 (LLP_LO0) REG LLP_HI0 (LLP_HI0) REG CTL_LO0 (CTL_LO0) REG CTL_HI0 (CTL_HI0) REG SSTAT0 (SSTAT0) REG DSTAT0 (DSTAT0) REG SSTATAR_LO0 (SSTATAR_LO0) REG SSTATAR_HI0 (SSTATAR_HI0) REG DSTATAR_LO0 (DSTATAR_LO0) REG DSTATAR_HI0 (DSTATAR_HI0) REG CFG_LO0 (CFG_LO0) REG CFG_HI0 (CFG_HI0) REG SGR0 (SGR0) REG DSR0 (DSR0) REG SAR_LO1 (SAR_LO1) REG SAR_HI1 (SAR_HI1) REG DAR_LO1 (DAR_LO1) REG DAR_HI1 (DAR_HI1) REG LLP_LO1 (LLP_LO1) REG LLP_HI1 (LLP_HI1) REG CTL_LO1 (CTL_LO1) REG CTL_HI1 (CTL_HI1) REG SSTAT1 (SSTAT1) REG DSTAT1 (DSTAT1) REG SSTATAR_LO1 (SSTATAR_LO1) REG SSTATAR_HI1 (SSTATAR_HI1) REG DSTATAR_LO1 (DSTATAR_LO1) REG DSTATAR_HI1 (DSTATAR_HI1) REG CFG_LO1 (CFG_LO1) REG CFG_HI1 (CFG_HI1) REG SGR1 (SGR1) REG DSR1 (DSR1) REG RawTfr (RawTfr) REG RawBlock (RawBlock) REG RawSrcTran (RawSrcTran) REG RawDstTran (RawDstTran) REG RawErr (RawErr) REG StatusTfr (StatusTfr) REG StatusBlock (StatusBlock) REG StatusSrcTran (StatusSrcTran) REG StatusDstTran (StatusDstTran) REG StatusErr (StatusErr) REG MaskTfr (MaskTfr) REG MaskBlock (MaskBlock) REG MaskSrcTran (MaskSrcTran) REG MaskDstTran (MaskDstTran) REG MaskErr (MaskErr) REG ClearTfr (ClearTfr) REG ClearBlock (ClearBlock) REG ClearSrcTran (ClearSrcTran) REG ClearDstTran (ClearDstTran) REG ClearErr (ClearErr) REG StatusInt (StatusInt) REG DmaCfgReg (DmaCfgReg) REG ChEnReg (ChEnReg) REG Reserved0_CPL (Reserved0_CPL) REG Reserved0_CPH (Reserved0_CPH) REG Reserved1_CPL (Reserved1_CPL) REG Reserved1_CPH (Reserved1_CPH) REG Reserved0_FPL (Reserved0_FPL) REG Reserved0_FPH (Reserved0_FPH) REG Reserved1_FPL (Reserved1_FPL) REG Reserved1_FPH (Reserved1_FPH) REG GLOBAL_CFG (GLOBAL_CFG)
REG SAR_LO0 (SAR_LO0)
REG SAR_HI0 (SAR_HI0)
REG DAR_LO0 (DAR_LO0)
REG DAR_HI0 (DAR_HI0)
REG LLP_LO0 (LLP_LO0)
REG LLP_HI0 (LLP_HI0)
REG CTL_LO0 (CTL_LO0)
REG CTL_HI0 (CTL_HI0)
REG SSTAT0 (SSTAT0)
REG DSTAT0 (DSTAT0)
REG SSTATAR_LO0 (SSTATAR_LO0)
REG SSTATAR_HI0 (SSTATAR_HI0)
REG DSTATAR_LO0 (DSTATAR_LO0)
REG DSTATAR_HI0 (DSTATAR_HI0)
REG CFG_LO0 (CFG_LO0)
REG CFG_HI0 (CFG_HI0)
REG SGR0 (SGR0)
REG DSR0 (DSR0)
REG SAR_LO1 (SAR_LO1)
REG SAR_HI1 (SAR_HI1)
REG DAR_LO1 (DAR_LO1)
REG DAR_HI1 (DAR_HI1)
REG LLP_LO1 (LLP_LO1)
REG LLP_HI1 (LLP_HI1)
REG CTL_LO1 (CTL_LO1)
REG CTL_HI1 (CTL_HI1)
REG SSTAT1 (SSTAT1)
REG DSTAT1 (DSTAT1)
REG SSTATAR_LO1 (SSTATAR_LO1)
REG SSTATAR_HI1 (SSTATAR_HI1)
REG DSTATAR_LO1 (DSTATAR_LO1)
REG DSTATAR_HI1 (DSTATAR_HI1)
REG CFG_LO1 (CFG_LO1)
REG CFG_HI1 (CFG_HI1)
REG SGR1 (SGR1)
REG DSR1 (DSR1)
REG RawTfr (RawTfr)
REG RawBlock (RawBlock)
REG RawSrcTran (RawSrcTran)
REG RawDstTran (RawDstTran)
REG RawErr (RawErr)
REG StatusTfr (StatusTfr)
REG StatusBlock (StatusBlock)
REG StatusSrcTran (StatusSrcTran)
REG StatusDstTran (StatusDstTran)
REG StatusErr (StatusErr)
REG MaskTfr (MaskTfr)
REG MaskBlock (MaskBlock)
REG MaskSrcTran (MaskSrcTran)
REG MaskDstTran (MaskDstTran)
REG MaskErr (MaskErr)
REG ClearTfr (ClearTfr)
REG ClearBlock (ClearBlock)
REG ClearSrcTran (ClearSrcTran)
REG ClearDstTran (ClearDstTran)
REG ClearErr (ClearErr)
REG StatusInt (StatusInt)
REG DmaCfgReg (DmaCfgReg)
REG ChEnReg (ChEnReg)
REG Reserved0_CPL (Reserved0_CPL)
REG Reserved0_CPH (Reserved0_CPH)
REG Reserved1_CPL (Reserved1_CPL)
REG Reserved1_CPH (Reserved1_CPH)
REG Reserved0_FPL (Reserved0_FPL)
REG Reserved0_FPH (Reserved0_FPH)
REG Reserved1_FPL (Reserved1_FPL)
REG Reserved1_FPH (Reserved1_FPH)
REG GLOBAL_CFG (GLOBAL_CFG)
I3C Additional MMIO
I3C Additional MMIO REG MULT_BUS_INST_EXT_CAP (MULT_BUS_INST_EXT_CAP) REG MULT_BUS_INST_CNT (MULT_BUS_INST_CNT) REG MULT_BUS_INST_OFFSET (MULT_BUS_INST_OFFSET) REG VND_SPEC_EXT_CAP_2 (VND_SPEC_EXT_CAP_2) REG RESETS (RESETS) REG GENERAL (GENERAL) REG ACTIVELTR (ACTIVELTR) REG IDLELTR (IDLELTR) REG SW_SCRATCH_0 (SW_SCRATCH_0) REG CLOCK_GATE (CLOCK_GATE) REG DEVIDLE_CONTROL (DEVIDLE_CONTROL) REG I3C_Threshold (I3C_Threshold) REG Ext_CAP_End (Ext_CAP_End)
REG MULT_BUS_INST_EXT_CAP (MULT_BUS_INST_EXT_CAP)
REG MULT_BUS_INST_CNT (MULT_BUS_INST_CNT)
REG MULT_BUS_INST_OFFSET (MULT_BUS_INST_OFFSET)
REG VND_SPEC_EXT_CAP_2 (VND_SPEC_EXT_CAP_2)
REG RESETS (RESETS)
REG GENERAL (GENERAL)
REG ACTIVELTR (ACTIVELTR)
REG IDLELTR (IDLELTR)
REG SW_SCRATCH_0 (SW_SCRATCH_0)
REG CLOCK_GATE (CLOCK_GATE)
REG DEVIDLE_CONTROL (DEVIDLE_CONTROL)
REG I3C_Threshold (I3C_Threshold)
REG Ext_CAP_End (Ext_CAP_End)
I3C DMA Controller
I3C DMA Controller REG CR_SETUP_0 (CR_SETUP_0) REG IBI_SETUP_0 (IBI_SETUP_0) REG CHUNK_CONTROL_0 (CHUNK_CONTROL_0) REG RH_INTR_STATUS_0 (RH_INTR_STATUS_0) REG RH_INTR_STATUS_ENABLE_0 (RH_INTR_STATUS_ENABLE_0) REG RH_INTR_SIGNAL_ENABLE_0 (RH_INTR_SIGNAL_ENABLE_0) REG RH_INTR_FORCE_0 (RH_INTR_FORCE_0) REG RH_STATUS_0 (RH_STATUS_0) REG RH_CONTROL_0 (RH_CONTROL_0) REG RH_OPERATION1_0 (RH_OPERATION1_0) REG RH_OPERATION2_0 (RH_OPERATION2_0) REG RH_CMD_RING_BASE_LO_0 (RH_CMD_RING_BASE_LO_0) REG RH_CMD_RING_BASE_HI_0 (RH_CMD_RING_BASE_HI_0) REG RH_RESP_RING_BASE_LO_0 (RH_RESP_RING_BASE_LO_0) REG RH_RESP_RING_BASE_HI_0 (RH_RESP_RING_BASE_HI_0) REG RH_IBI_STATUS_RING_BASE_LO_0 (RH_IBI_STATUS_RING_BASE_LO_0) REG RH_IBI_STATUS_RING_BASE_HI_0 (RH_IBI_STATUS_RING_BASE_HI_0) REG RH_IBI_DATA_RING_BASE_LO_0 (RH_IBI_DATA_RING_BASE_LO_0) REG RH_IBI_DATA_RING_BASE_HI_0 (RH_IBI_DATA_RING_BASE_HI_0) REG RHS_CONTROL_0 (RHS_CONTROL_0) REG RH0_OFFSET_0 (RH0_OFFSET_0) REG RH1_OFFSET_0 (RH1_OFFSET_0) REG RH2_OFFSET_0 (RH2_OFFSET_0) REG RH3_OFFSET_0 (RH3_OFFSET_0) REG RH4_OFFSET_0 (RH4_OFFSET_0) REG RH5_OFFSET_0 (RH5_OFFSET_0) REG RH6_OFFSET_0 (RH6_OFFSET_0) REG RH7_OFFSET_0 (RH7_OFFSET_0) REG CR_SETUP_2 (CR_SETUP_2) REG IBI_SETUP_2 (IBI_SETUP_2) REG CHUNK_CONTROL_2 (CHUNK_CONTROL_2) REG RH_INTR_STATUS_2 (RH_INTR_STATUS_2) REG RH_INTR_STATUS_ENABLE_2 (RH_INTR_STATUS_ENABLE_2) REG RH_INTR_SIGNAL_ENABLE_2 (RH_INTR_SIGNAL_ENABLE_2) REG RH_INTR_FORCE_2 (RH_INTR_FORCE_2) REG RH_STATUS_2 (RH_STATUS_2) REG RH_CONTROL_2 (RH_CONTROL_2) REG RH_OPERATION1_2 (RH_OPERATION1_2) REG RH_OPERATION2_2 (RH_OPERATION2_2) REG RH_CMD_RING_BASE_LO_2 (RH_CMD_RING_BASE_LO_2) REG RH_CMD_RING_BASE_HI_2 (RH_CMD_RING_BASE_HI_2) REG RH_RESP_RING_BASE_LO_2 (RH_RESP_RING_BASE_LO_2) REG RH_RESP_RING_BASE_HI_2 (RH_RESP_RING_BASE_HI_2) REG RH_IBI_STATUS_RING_BASE_LO_2 (RH_IBI_STATUS_RING_BASE_LO_2) REG RH_IBI_STATUS_RING_BASE_HI_2 (RH_IBI_STATUS_RING_BASE_HI_2) REG RH_IBI_DATA_RING_BASE_LO_2 (RH_IBI_DATA_RING_BASE_LO_2) REG RH_IBI_DATA_RING_BASE_HI_2 (RH_IBI_DATA_RING_BASE_HI_2) REG RHS_CONTROL_1 (RHS_CONTROL_1) REG RH0_OFFSET_1 (RH0_OFFSET_1) REG RH1_OFFSET_1 (RH1_OFFSET_1) REG RH2_OFFSET_1 (RH2_OFFSET_1) REG RH3_OFFSET_1 (RH3_OFFSET_1) REG RH4_OFFSET_1 (RH4_OFFSET_1) REG RH5_OFFSET_1 (RH5_OFFSET_1) REG RH6_OFFSET_1 (RH6_OFFSET_1) REG RH7_OFFSET_1 (RH7_OFFSET_1) REG CR_SETUP_1 (CR_SETUP_1) REG IBI_SETUP_1 (IBI_SETUP_1) REG CHUNK_CONTROL_1 (CHUNK_CONTROL_1) REG RH_INTR_STATUS_1 (RH_INTR_STATUS_1) REG RH_INTR_STATUS_ENABLE_1 (RH_INTR_STATUS_ENABLE_1) REG RH_INTR_SIGNAL_ENABLE_1 (RH_INTR_SIGNAL_ENABLE_1) REG RH_INTR_FORCE_1 (RH_INTR_FORCE_1) REG RH_STATUS_1 (RH_STATUS_1) REG RH_CONTROL_1 (RH_CONTROL_1) REG RH_OPERATION1_1 (RH_OPERATION1_1) REG RH_OPERATION2_1 (RH_OPERATION2_1) REG RH_CMD_RING_BASE_LO_1 (RH_CMD_RING_BASE_LO_1) REG RH_CMD_RING_BASE_HI_1 (RH_CMD_RING_BASE_HI_1) REG RH_RESP_RING_BASE_LO_1 (RH_RESP_RING_BASE_LO_1) REG RH_RESP_RING_BASE_HI_1 (RH_RESP_RING_BASE_HI_1) REG RH_IBI_STATUS_RING_BASE_LO_1 (RH_IBI_STATUS_RING_BASE_LO_1) REG RH_IBI_STATUS_RING_BASE_HI_1 (RH_IBI_STATUS_RING_BASE_HI_1) REG RH_IBI_DATA_RING_BASE_LO_1 (RH_IBI_DATA_RING_BASE_LO_1) REG RH_IBI_DATA_RING_BASE_HI_1 (RH_IBI_DATA_RING_BASE_HI_1) REG CR_SETUP_3 (CR_SETUP_3) REG IBI_SETUP_3 (IBI_SETUP_3) REG CHUNK_CONTROL_3 (CHUNK_CONTROL_3) REG RH_INTR_STATUS_3 (RH_INTR_STATUS_3) REG RH_INTR_STATUS_ENABLE_3 (RH_INTR_STATUS_ENABLE_3) REG RH_INTR_SIGNAL_ENABLE_3 (RH_INTR_SIGNAL_ENABLE_3) REG RH_INTR_FORCE_3 (RH_INTR_FORCE_3) REG RH_STATUS_3 (RH_STATUS_3) REG RH_CONTROL_3 (RH_CONTROL_3) REG RH_OPERATION1_3 (RH_OPERATION1_3) REG RH_OPERATION2_3 (RH_OPERATION2_3) REG RH_CMD_RING_BASE_LO_3 (RH_CMD_RING_BASE_LO_3) REG RH_CMD_RING_BASE_HI_3 (RH_CMD_RING_BASE_HI_3) REG RH_RESP_RING_BASE_LO_3 (RH_RESP_RING_BASE_LO_3) REG RH_RESP_RING_BASE_HI_3 (RH_RESP_RING_BASE_HI_3) REG RH_IBI_STATUS_RING_BASE_LO_3 (RH_IBI_STATUS_RING_BASE_LO_3) REG RH_IBI_STATUS_RING_BASE_HI_3 (RH_IBI_STATUS_RING_BASE_HI_3) REG RH_IBI_DATA_RING_BASE_LO_3 (RH_IBI_DATA_RING_BASE_LO_3) REG RH_IBI_DATA_RING_BASE_HI_3 (RH_IBI_DATA_RING_BASE_HI_3)
REG CR_SETUP_0 (CR_SETUP_0)
REG IBI_SETUP_0 (IBI_SETUP_0)
REG CHUNK_CONTROL_0 (CHUNK_CONTROL_0)
REG RH_INTR_STATUS_0 (RH_INTR_STATUS_0)
REG RH_INTR_STATUS_ENABLE_0 (RH_INTR_STATUS_ENABLE_0)
REG RH_INTR_SIGNAL_ENABLE_0 (RH_INTR_SIGNAL_ENABLE_0)
REG RH_INTR_FORCE_0 (RH_INTR_FORCE_0)
REG RH_STATUS_0 (RH_STATUS_0)
REG RH_CONTROL_0 (RH_CONTROL_0)
REG RH_OPERATION1_0 (RH_OPERATION1_0)
REG RH_OPERATION2_0 (RH_OPERATION2_0)
REG RH_CMD_RING_BASE_LO_0 (RH_CMD_RING_BASE_LO_0)
REG RH_CMD_RING_BASE_HI_0 (RH_CMD_RING_BASE_HI_0)
REG RH_RESP_RING_BASE_LO_0 (RH_RESP_RING_BASE_LO_0)
REG RH_RESP_RING_BASE_HI_0 (RH_RESP_RING_BASE_HI_0)
REG RH_IBI_STATUS_RING_BASE_LO_0 (RH_IBI_STATUS_RING_BASE_LO_0)
REG RH_IBI_STATUS_RING_BASE_HI_0 (RH_IBI_STATUS_RING_BASE_HI_0)
REG RH_IBI_DATA_RING_BASE_LO_0 (RH_IBI_DATA_RING_BASE_LO_0)
REG RH_IBI_DATA_RING_BASE_HI_0 (RH_IBI_DATA_RING_BASE_HI_0)
REG RHS_CONTROL_0 (RHS_CONTROL_0)
REG RH0_OFFSET_0 (RH0_OFFSET_0)
REG RH1_OFFSET_0 (RH1_OFFSET_0)
REG RH2_OFFSET_0 (RH2_OFFSET_0)
REG RH3_OFFSET_0 (RH3_OFFSET_0)
REG RH4_OFFSET_0 (RH4_OFFSET_0)
REG RH5_OFFSET_0 (RH5_OFFSET_0)
REG RH6_OFFSET_0 (RH6_OFFSET_0)
REG RH7_OFFSET_0 (RH7_OFFSET_0)
REG CR_SETUP_2 (CR_SETUP_2)
REG IBI_SETUP_2 (IBI_SETUP_2)
REG CHUNK_CONTROL_2 (CHUNK_CONTROL_2)
REG RH_INTR_STATUS_2 (RH_INTR_STATUS_2)
REG RH_INTR_STATUS_ENABLE_2 (RH_INTR_STATUS_ENABLE_2)
REG RH_INTR_SIGNAL_ENABLE_2 (RH_INTR_SIGNAL_ENABLE_2)
REG RH_INTR_FORCE_2 (RH_INTR_FORCE_2)
REG RH_STATUS_2 (RH_STATUS_2)
REG RH_CONTROL_2 (RH_CONTROL_2)
REG RH_OPERATION1_2 (RH_OPERATION1_2)
REG RH_OPERATION2_2 (RH_OPERATION2_2)
REG RH_CMD_RING_BASE_LO_2 (RH_CMD_RING_BASE_LO_2)
REG RH_CMD_RING_BASE_HI_2 (RH_CMD_RING_BASE_HI_2)
REG RH_RESP_RING_BASE_LO_2 (RH_RESP_RING_BASE_LO_2)
REG RH_RESP_RING_BASE_HI_2 (RH_RESP_RING_BASE_HI_2)
REG RH_IBI_STATUS_RING_BASE_LO_2 (RH_IBI_STATUS_RING_BASE_LO_2)
REG RH_IBI_STATUS_RING_BASE_HI_2 (RH_IBI_STATUS_RING_BASE_HI_2)
REG RH_IBI_DATA_RING_BASE_LO_2 (RH_IBI_DATA_RING_BASE_LO_2)
REG RH_IBI_DATA_RING_BASE_HI_2 (RH_IBI_DATA_RING_BASE_HI_2)
REG RHS_CONTROL_1 (RHS_CONTROL_1)
REG RH0_OFFSET_1 (RH0_OFFSET_1)
REG RH1_OFFSET_1 (RH1_OFFSET_1)
REG RH2_OFFSET_1 (RH2_OFFSET_1)
REG RH3_OFFSET_1 (RH3_OFFSET_1)
REG RH4_OFFSET_1 (RH4_OFFSET_1)
REG RH5_OFFSET_1 (RH5_OFFSET_1)
REG RH6_OFFSET_1 (RH6_OFFSET_1)
REG RH7_OFFSET_1 (RH7_OFFSET_1)
REG CR_SETUP_1 (CR_SETUP_1)
REG IBI_SETUP_1 (IBI_SETUP_1)
REG CHUNK_CONTROL_1 (CHUNK_CONTROL_1)
REG RH_INTR_STATUS_1 (RH_INTR_STATUS_1)
REG RH_INTR_STATUS_ENABLE_1 (RH_INTR_STATUS_ENABLE_1)
REG RH_INTR_SIGNAL_ENABLE_1 (RH_INTR_SIGNAL_ENABLE_1)
REG RH_INTR_FORCE_1 (RH_INTR_FORCE_1)
REG RH_STATUS_1 (RH_STATUS_1)
REG RH_CONTROL_1 (RH_CONTROL_1)
REG RH_OPERATION1_1 (RH_OPERATION1_1)
REG RH_OPERATION2_1 (RH_OPERATION2_1)
REG RH_CMD_RING_BASE_LO_1 (RH_CMD_RING_BASE_LO_1)
REG RH_CMD_RING_BASE_HI_1 (RH_CMD_RING_BASE_HI_1)
REG RH_RESP_RING_BASE_LO_1 (RH_RESP_RING_BASE_LO_1)
REG RH_RESP_RING_BASE_HI_1 (RH_RESP_RING_BASE_HI_1)
REG RH_IBI_STATUS_RING_BASE_LO_1 (RH_IBI_STATUS_RING_BASE_LO_1)
REG RH_IBI_STATUS_RING_BASE_HI_1 (RH_IBI_STATUS_RING_BASE_HI_1)
REG RH_IBI_DATA_RING_BASE_LO_1 (RH_IBI_DATA_RING_BASE_LO_1)
REG RH_IBI_DATA_RING_BASE_HI_1 (RH_IBI_DATA_RING_BASE_HI_1)
REG CR_SETUP_3 (CR_SETUP_3)
REG IBI_SETUP_3 (IBI_SETUP_3)
REG CHUNK_CONTROL_3 (CHUNK_CONTROL_3)
REG RH_INTR_STATUS_3 (RH_INTR_STATUS_3)
REG RH_INTR_STATUS_ENABLE_3 (RH_INTR_STATUS_ENABLE_3)
REG RH_INTR_SIGNAL_ENABLE_3 (RH_INTR_SIGNAL_ENABLE_3)
REG RH_INTR_FORCE_3 (RH_INTR_FORCE_3)
REG RH_STATUS_3 (RH_STATUS_3)
REG RH_CONTROL_3 (RH_CONTROL_3)
REG RH_OPERATION1_3 (RH_OPERATION1_3)
REG RH_OPERATION2_3 (RH_OPERATION2_3)
REG RH_CMD_RING_BASE_LO_3 (RH_CMD_RING_BASE_LO_3)
REG RH_CMD_RING_BASE_HI_3 (RH_CMD_RING_BASE_HI_3)
REG RH_RESP_RING_BASE_LO_3 (RH_RESP_RING_BASE_LO_3)
REG RH_RESP_RING_BASE_HI_3 (RH_RESP_RING_BASE_HI_3)
REG RH_IBI_STATUS_RING_BASE_LO_3 (RH_IBI_STATUS_RING_BASE_LO_3)
REG RH_IBI_STATUS_RING_BASE_HI_3 (RH_IBI_STATUS_RING_BASE_HI_3)
REG RH_IBI_DATA_RING_BASE_LO_3 (RH_IBI_DATA_RING_BASE_LO_3)
REG RH_IBI_DATA_RING_BASE_HI_3 (RH_IBI_DATA_RING_BASE_HI_3)
I3C MMIO
I3C MMIO HCI Version register (DWC_mipi_i3c_HCI_block.HCI_VERSION) HC_CONTROL (DWC_mipi_i3c_HCI_block.HC_CONTROL) Master Device Address Register (DWC_mipi_i3c_HCI_block.MASTER_DEVICE_ADDR) HC Capabilities Register (DWC_mipi_i3c_HCI_block.HC_CAPABILITIES) Reset Control Register (DWC_mipi_i3c_HCI_block.RESET_CONTROL) Present State Register (DWC_mipi_i3c_HCI_block.PRESENT_STATE) Interrupt Status Register (DWC_mipi_i3c_HCI_block.INTR_STATUS) Interrupt Status Enable Register (DWC_mipi_i3c_HCI_block.INTR_STATUS_ENABLE) Interrupt Signal Enable Register (DWC_mipi_i3c_HCI_block.INTR_SIGNAL_ENABLE) Interrupt Force Enable Register (DWC_mipi_i3c_HCI_block.INTR_FORCE) Device Characteristics Table Pointer (DWC_mipi_i3c_HCI_block.DCT_SECTION_OFFSET) Ring Headers Section Offset Register (DWC_mipi_i3c_HCI_block.RING_HEADERS_SECTION_OFFSET) PIO Section Offset Register (DWC_mipi_i3c_HCI_block.PIO_SECTION_OFFSET) Extended Capabilities Section Offset Register (DWC_mipi_i3c_HCI_block.EXTCAPS_SECTION_OFFSET) IBI Queue Control Register (DWC_mipi_i3c_HCI_block.IBI_NOTIFY_CTRL) Device Context Address Low Register (DWC_mipi_i3c_HCI_block.DEV_CTX_BASE_LO) Device Context Address High Register (DWC_mipi_i3c_HCI_block.DEV_CTX_BASE_HI) Device Address Table Location 1 of Device1 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE1_LOC1) Device Address Table Location 2 of Device1 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE1_LOC2) Device Address Table Location 1 of Device2 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE2_LOC1) Device Address Table Location 2 of Device2 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE2_LOC2) Device Address Table Location 1 of Device3 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE3_LOC1) Device Address Table Location 2 of Device3 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE3_LOC2) Device Address Table Location 1 of Device4 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE4_LOC1) Device Address Table Location 2 of Device4 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE4_LOC2) Device Address Table Location 1 of Device5 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE5_LOC1) Device Address Table Location 2 of Device5 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE5_LOC2) Device Address Table Location 1 of Device6 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE6_LOC1) Device Address Table Location 2 of Device6 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE6_LOC2) Device Address Table Location 1 of Device7 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE7_LOC1) Device Address Table Location 2 of Device7 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE7_LOC2) Device Address Table Location 1 of Device8 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE8_LOC1) Device Address Table Location 2 of Device8 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE8_LOC2) Response Queue Port Register (DWC_mipi_i3c_HCI_block.RESPONSE_QUEUE_PORT) Transmit and Receive Data Port Register (DWC_mipi_i3c_HCI_block.DATA_PORT) Transmit and Receive Data Port Register (DWC_mipi_i3c_HCI_block.RX_DATA_PORT) Transmit and Receive Data Port Register (DWC_mipi_i3c_HCI_block.TX_DATA_PORT) IBI Port Register (DWC_mipi_i3c_HCI_block.IBI_PORT) Queue Threshold Control Register (DWC_mipi_i3c_HCI_block.QUEUE_THLD_CTRL) Data Buffer Threshold Control Register (DWC_mipi_i3c_HCI_block.DATA_BUFFER_THLD_CTRL) Queue Size Register (DWC_mipi_i3c_HCI_block.QUEUE_SIZE_CTRL) PIO Interrupt Status Register (DWC_mipi_i3c_HCI_block.PIO_INTR_STATUS) PIO Interrupt Status Enable Register (DWC_mipi_i3c_HCI_block.PIO_INTR_STATUS_ENABLE) PIO Interrupt Signal Enable Register (DWC_mipi_i3c_HCI_block.PIO_INTR_SIGNAL_ENABLE) PIO Interrupt Force Register (DWC_mipi_i3c_HCI_block.PIO_INTR_FORCE) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE1_LOC1) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE1_LOC2) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE1_LOC3) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE1_LOC4) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE2_LOC1) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE2_LOC2) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE2_LOC3) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE2_LOC4) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE3_LOC1) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE3_LOC2) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE3_LOC3) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE3_LOC4) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE4_LOC1) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE4_LOC2) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE4_LOC3) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE4_LOC4) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE5_LOC1) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE5_LOC2) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE5_LOC3) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE5_LOC4) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE6_LOC1) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE6_LOC2) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE6_LOC3) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE6_LOC4) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE7_LOC1) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE7_LOC2) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE7_LOC3) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE7_LOC4) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE8_LOC1) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE8_LOC2) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE8_LOC3) (DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE8_LOC4) Hardware Identification header Register (DWC_mipi_i3c_HCI_block.HW_IDENTIFICATION_HEADER) SCL I3C Open Drain Timing Register (DWC_mipi_i3c_HCI_block.SCL_I3C_OD_TIMING) SCL I3C Push Pull Timing Register (DWC_mipi_i3c_HCI_block.SCL_I3C_PP_TIMING) SCL I2C Fast Mode Timing Register (DWC_mipi_i3c_HCI_block.SCL_I2C_FM_TIMING) SCL I2C Fast Mode Plus Timing Register (DWC_mipi_i3c_HCI_block.SCL_I2C_FMP_TIMING) SCL I2C Standard Speed Timing Register (DWC_mipi_i3c_HCI_block.SCL_I2C_SS_TIMING) SCL Extended Low Count Timing Register (DWC_mipi_i3c_HCI_block.SCL_EXT_LCNT_TIMING) SCL Termination Bit Low count Timing Register (DWC_mipi_i3c_HCI_block.SCL_EXT_TERMN_LCNT_TIMING) SDA Hold and Mode Switch Delay Timing Register (DWC_mipi_i3c_HCI_block.SDA_HOLD_SWITCH_DLY_TIMING) Debug specific header Register (DWC_mipi_i3c_HCI_block.DS_EXTCAP_HEADER) Queue Status Level Register (DWC_mipi_i3c_HCI_block.QUEUE_STATUS_LEVEL) Data Buffer Status Level Register (DWC_mipi_i3c_HCI_block.DATA_BUFFER_STATUS_LEVEL) Present State Register (DWC_mipi_i3c_HCI_block.PRESENT_STATE_DEBUG) Master Extended specific header Register (DWC_mipi_i3c_HCI_block.MASTER_EXT_HEADER) Master Config Register (DWC_mipi_i3c_HCI_block.MASTER_CONFIG)
HCI Version register (DWC_mipi_i3c_HCI_block.HCI_VERSION)
HC_CONTROL (DWC_mipi_i3c_HCI_block.HC_CONTROL)
Master Device Address Register (DWC_mipi_i3c_HCI_block.MASTER_DEVICE_ADDR)
HC Capabilities Register (DWC_mipi_i3c_HCI_block.HC_CAPABILITIES)
Reset Control Register (DWC_mipi_i3c_HCI_block.RESET_CONTROL)
Present State Register (DWC_mipi_i3c_HCI_block.PRESENT_STATE)
Interrupt Status Register (DWC_mipi_i3c_HCI_block.INTR_STATUS)
Interrupt Status Enable Register (DWC_mipi_i3c_HCI_block.INTR_STATUS_ENABLE)
Interrupt Signal Enable Register (DWC_mipi_i3c_HCI_block.INTR_SIGNAL_ENABLE)
Interrupt Force Enable Register (DWC_mipi_i3c_HCI_block.INTR_FORCE)
Device Characteristics Table Pointer (DWC_mipi_i3c_HCI_block.DCT_SECTION_OFFSET)
Ring Headers Section Offset Register (DWC_mipi_i3c_HCI_block.RING_HEADERS_SECTION_OFFSET)
PIO Section Offset Register (DWC_mipi_i3c_HCI_block.PIO_SECTION_OFFSET)
Extended Capabilities Section Offset Register (DWC_mipi_i3c_HCI_block.EXTCAPS_SECTION_OFFSET)
IBI Queue Control Register (DWC_mipi_i3c_HCI_block.IBI_NOTIFY_CTRL)
Device Context Address Low Register (DWC_mipi_i3c_HCI_block.DEV_CTX_BASE_LO)
Device Context Address High Register (DWC_mipi_i3c_HCI_block.DEV_CTX_BASE_HI)
Device Address Table Location 1 of Device1 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE1_LOC1)
Device Address Table Location 2 of Device1 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE1_LOC2)
Device Address Table Location 1 of Device2 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE2_LOC1)
Device Address Table Location 2 of Device2 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE2_LOC2)
Device Address Table Location 1 of Device3 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE3_LOC1)
Device Address Table Location 2 of Device3 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE3_LOC2)
Device Address Table Location 1 of Device4 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE4_LOC1)
Device Address Table Location 2 of Device4 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE4_LOC2)
Device Address Table Location 1 of Device5 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE5_LOC1)
Device Address Table Location 2 of Device5 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE5_LOC2)
Device Address Table Location 1 of Device6 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE6_LOC1)
Device Address Table Location 2 of Device6 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE6_LOC2)
Device Address Table Location 1 of Device7 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE7_LOC1)
Device Address Table Location 2 of Device7 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE7_LOC2)
Device Address Table Location 1 of Device8 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE8_LOC1)
Device Address Table Location 2 of Device8 (DWC_mipi_i3c_HCI_block.DEV_ADDR_TABLE8_LOC2)
Response Queue Port Register (DWC_mipi_i3c_HCI_block.RESPONSE_QUEUE_PORT)
Transmit and Receive Data Port Register (DWC_mipi_i3c_HCI_block.DATA_PORT)
Transmit and Receive Data Port Register (DWC_mipi_i3c_HCI_block.RX_DATA_PORT)
Transmit and Receive Data Port Register (DWC_mipi_i3c_HCI_block.TX_DATA_PORT)
IBI Port Register (DWC_mipi_i3c_HCI_block.IBI_PORT)
Queue Threshold Control Register (DWC_mipi_i3c_HCI_block.QUEUE_THLD_CTRL)
Data Buffer Threshold Control Register (DWC_mipi_i3c_HCI_block.DATA_BUFFER_THLD_CTRL)
Queue Size Register (DWC_mipi_i3c_HCI_block.QUEUE_SIZE_CTRL)
PIO Interrupt Status Register (DWC_mipi_i3c_HCI_block.PIO_INTR_STATUS)
PIO Interrupt Status Enable Register (DWC_mipi_i3c_HCI_block.PIO_INTR_STATUS_ENABLE)
PIO Interrupt Signal Enable Register (DWC_mipi_i3c_HCI_block.PIO_INTR_SIGNAL_ENABLE)
PIO Interrupt Force Register (DWC_mipi_i3c_HCI_block.PIO_INTR_FORCE)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE1_LOC1)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE1_LOC2)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE1_LOC3)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE1_LOC4)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE2_LOC1)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE2_LOC2)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE2_LOC3)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE2_LOC4)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE3_LOC1)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE3_LOC2)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE3_LOC3)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE3_LOC4)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE4_LOC1)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE4_LOC2)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE4_LOC3)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE4_LOC4)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE5_LOC1)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE5_LOC2)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE5_LOC3)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE5_LOC4)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE6_LOC1)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE6_LOC2)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE6_LOC3)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE6_LOC4)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE7_LOC1)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE7_LOC2)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE7_LOC3)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE7_LOC4)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE8_LOC1)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE8_LOC2)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE8_LOC3)
(DWC_mipi_i3c_HCI_block.DEV_CHAR_TABLE8_LOC4)
Hardware Identification header Register (DWC_mipi_i3c_HCI_block.HW_IDENTIFICATION_HEADER)
SCL I3C Open Drain Timing Register (DWC_mipi_i3c_HCI_block.SCL_I3C_OD_TIMING)
SCL I3C Push Pull Timing Register (DWC_mipi_i3c_HCI_block.SCL_I3C_PP_TIMING)
SCL I2C Fast Mode Timing Register (DWC_mipi_i3c_HCI_block.SCL_I2C_FM_TIMING)
SCL I2C Fast Mode Plus Timing Register (DWC_mipi_i3c_HCI_block.SCL_I2C_FMP_TIMING)
SCL I2C Standard Speed Timing Register (DWC_mipi_i3c_HCI_block.SCL_I2C_SS_TIMING)
SCL Extended Low Count Timing Register (DWC_mipi_i3c_HCI_block.SCL_EXT_LCNT_TIMING)
SCL Termination Bit Low count Timing Register (DWC_mipi_i3c_HCI_block.SCL_EXT_TERMN_LCNT_TIMING)
SDA Hold and Mode Switch Delay Timing Register (DWC_mipi_i3c_HCI_block.SDA_HOLD_SWITCH_DLY_TIMING)
Debug specific header Register (DWC_mipi_i3c_HCI_block.DS_EXTCAP_HEADER)
Queue Status Level Register (DWC_mipi_i3c_HCI_block.QUEUE_STATUS_LEVEL)
Data Buffer Status Level Register (DWC_mipi_i3c_HCI_block.DATA_BUFFER_STATUS_LEVEL)
Present State Register (DWC_mipi_i3c_HCI_block.PRESENT_STATE_DEBUG)
Master Extended specific header Register (DWC_mipi_i3c_HCI_block.MASTER_EXT_HEADER)
Master Config Register (DWC_mipi_i3c_HCI_block.MASTER_CONFIG)
I3C PCI Configuration (D17:F0/1)
I3C PCI Configuration (D17:F0/1) Device Id And Vendor Id Register (DEVVENDID) Status And Command (STATUSCOMMAND) Revision Id And Class Code (REVCLASSCODE) Cache Line Latency Header And Bist (CLLATHEADERBIST) Base Address Register (BAR) Base Address Register High (BAR_HIGH) Base Address Register1 (BAR1) Base Address Register1 High (BAR1_HIGH) Subsystem Vendor And Subsystem Id (SUBSYSTEMID) Expansion Rom Base Address (EXPANSION_ROM_BASEADDR) Capabilities Pointer (CAPABILITYPTR) Interrupt Register (INTERRUPTREG) Power Management Capability Id (POWERCAPID) Power Management Control And Status Register (PMECTRLSTATUS) Pci Device Idle Vendor Capability Register (PCIDEVIDLE_CAP_RECORD) Vendor Specific Extended Capability Register (DEVID_VEND_SPECIFIC_REG) Software Ltr Update Mmio Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG) Device Idle Pointer Register (DEVICE_IDLE_POINTER_REG) D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG) General Purpose Read Write Register1 (GEN_PCI_REGRW1) General Purpose Read Write Register2 (GEN_PCI_REGRW2) General Purpose Read Write Register3 (GEN_PCI_REGRW3) General Purpose Read Write Register4 (GEN_PCI_REGRW4) General Purpose Input Register (GEN_INPUT_REG)
Device Id And Vendor Id Register (DEVVENDID)
Status And Command (STATUSCOMMAND)
Revision Id And Class Code (REVCLASSCODE)
Cache Line Latency Header And Bist (CLLATHEADERBIST)
Base Address Register (BAR)
Base Address Register High (BAR_HIGH)
Base Address Register1 (BAR1)
Base Address Register1 High (BAR1_HIGH)
Subsystem Vendor And Subsystem Id (SUBSYSTEMID)
Expansion Rom Base Address (EXPANSION_ROM_BASEADDR)
Capabilities Pointer (CAPABILITYPTR)
Interrupt Register (INTERRUPTREG)
Power Management Capability Id (POWERCAPID)
Power Management Control And Status Register (PMECTRLSTATUS)
Pci Device Idle Vendor Capability Register (PCIDEVIDLE_CAP_RECORD)
Vendor Specific Extended Capability Register (DEVID_VEND_SPECIFIC_REG)
Software Ltr Update Mmio Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device Idle Pointer Register (DEVICE_IDLE_POINTER_REG)
D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG)
General Purpose Read Write Register1 (GEN_PCI_REGRW1)
General Purpose Read Write Register2 (GEN_PCI_REGRW2)
General Purpose Read Write Register3 (GEN_PCI_REGRW3)
General Purpose Read Write Register4 (GEN_PCI_REGRW4)
General Purpose Input Register (GEN_INPUT_REG)
IDE Redirection (IDE-R) PCI Configuration (D22:F2)
IDE Redirection (IDE-R) PCI Configuration (D22:F2) Device ID And Vendor ID (IDE_HOST_DID_VID) Status And Command (IDE_HOST_STS_CMD) Class Code And Revision ID (IDE_HOST_CC_RID) BIST, Header Type, Latency Timer, And Cache Line Size (IDE_HOST_BIST_HTYPE_LT_CLS) IDE Primary Command Block IO BAR (IDE_HOST_PCMDIOBAR) IDE Primary Control Block IO BAR (IDE_HOST_PCTLIOBAR) IDE Secondary Command Block IO BAR (IDE_HOST_SCMDIOBAR) IDE Secondary Control Block IO BAR (IDE_HOST_SCTLIOBAR) IDE Bus Initiator Block IO BAR (IDE_HOST_BMIOBAR) Cardbus CIS Pointer (IDE_HOST_CCP) Subsystem ID And Subsystem Vendor ID (IDE_HOST_SID_SVID) Expansion ROM Base Address (IDE_HOST_XRBAR) Capabilities List Pointer (IDE_HOST_CAPP) Maximum Latency, Minimum Grant, Interrupt Pin And Interrupt Line (IDE_HOST_MAXL_MING_INTP_INTL) MSI Message Control, Next Pointer And Capability ID (IDE_HOST_MSIMC_MSINP_MSICID) MSI Message Address (IDE_HOST_MSIMA) MSI Message Upper Address (IDE_HOST_MSIMUA) MSI Message Data (IDE_HOST_MSIMD) Power Management Capabilities, Next Pointer And Capability ID (IDE_HOST_PMCAP_PMNP_PMCID) Power Management Data, Control/Status Register Bridge Support Extensions, Control And Status (IDE_HOST_PMD_PMCSRBSE_PMCSR)
Device ID And Vendor ID (IDE_HOST_DID_VID)
Status And Command (IDE_HOST_STS_CMD)
Class Code And Revision ID (IDE_HOST_CC_RID)
BIST, Header Type, Latency Timer, And Cache Line Size (IDE_HOST_BIST_HTYPE_LT_CLS)
IDE Primary Command Block IO BAR (IDE_HOST_PCMDIOBAR)
IDE Primary Control Block IO BAR (IDE_HOST_PCTLIOBAR)
IDE Secondary Command Block IO BAR (IDE_HOST_SCMDIOBAR)
IDE Secondary Control Block IO BAR (IDE_HOST_SCTLIOBAR)
IDE Bus Initiator Block IO BAR (IDE_HOST_BMIOBAR)
Cardbus CIS Pointer (IDE_HOST_CCP)
Subsystem ID And Subsystem Vendor ID (IDE_HOST_SID_SVID)
Expansion ROM Base Address (IDE_HOST_XRBAR)
Capabilities List Pointer (IDE_HOST_CAPP)
Maximum Latency, Minimum Grant, Interrupt Pin And Interrupt Line (IDE_HOST_MAXL_MING_INTP_INTL)
MSI Message Control, Next Pointer And Capability ID (IDE_HOST_MSIMC_MSINP_MSICID)
MSI Message Address (IDE_HOST_MSIMA)
MSI Message Upper Address (IDE_HOST_MSIMUA)
MSI Message Data (IDE_HOST_MSIMD)
Power Management Capabilities, Next Pointer And Capability ID (IDE_HOST_PMCAP_PMNP_PMCID)
Power Management Data, Control/Status Register Bridge Support Extensions, Control And Status (IDE_HOST_PMD_PMCSRBSE_PMCSR)
Integrated GbE Configuration (D31:F6)
Integrated GbE Configuration (D31:F6) GbE Vendor and Device Identification Register (GBE_VID_DID) PCI Command & Status Register (PCICMD_STS) Revision Identification & Class Code Register (RID_CC) Cache Line Size Primary Latency Timer & Header Type Register (CLS_PLT_HEADTYP) Memory Base Address Register A (MBARA) Memory Base Address Register B (MBARB) Address (ADDR) Address 2 (ADDR2) Address 3 (ADDR3) Subsystem Vendor & Subsytem ID (SS) Expansion ROM Base Address Register (ERBA) Capabilities List Pointer Register (CAPP) Interrupt Information & Maximum Latency/Minimum GrantRegister (INTR_MLMG) LAN Disable Control (LANDISCTRL) Lock LAN Disable (LOCKLANDIS)
GbE Vendor and Device Identification Register (GBE_VID_DID)
PCI Command & Status Register (PCICMD_STS)
Revision Identification & Class Code Register (RID_CC)
Cache Line Size Primary Latency Timer & Header Type Register (CLS_PLT_HEADTYP)
Memory Base Address Register A (MBARA)
Memory Base Address Register B (MBARB)
Address (ADDR)
Address 2 (ADDR2)
Address 3 (ADDR3)
Subsystem Vendor & Subsytem ID (SS)
Expansion ROM Base Address Register (ERBA)
Capabilities List Pointer Register (CAPP)
Interrupt Information & Maximum Latency/Minimum GrantRegister (INTR_MLMG)
LAN Disable Control (LANDISCTRL)
Lock LAN Disable (LOCKLANDIS)
Intel® CSME HECI 1 Memory Mapped I/O
Intel® CSME HECI 1 Memory Mapped I/O DEVIDLE Control (HECI1_DEVIDLEC)
DEVIDLE Control (HECI1_DEVIDLEC)
Intel® CSME HECI 2 Memory Mapped I/O
Intel® CSME HECI 2 Memory Mapped I/O DEVIDLE Control (HECI2_DEVIDLEC)
DEVIDLE Control (HECI2_DEVIDLEC)
Intel® CSME HECI 3 Memory Mapped I/O
Intel® CSME HECI 3 Memory Mapped I/O DEVIDLE Control (HECI3_DEVIDLEC)
DEVIDLE Control (HECI3_DEVIDLEC)
Intel® CSME HECI 4 Memory Mapped I/O
Intel® CSME HECI 4 Memory Mapped I/O DEVIDLE Control (HECI4_DEVIDLEC)
DEVIDLE Control (HECI4_DEVIDLEC)
Intel® CSME HECI PCI Configuration (D22:F0/1/4/5)
Intel® CSME HECI PCI Configuration (D22:F0/1/4/5) Identification (HECI1_ID) Command (HECI1_CMD) Status (HECI1_STS) Revision ID And Class Code (HECI1_RID_CC) Cache Line Size (HECI1_CLS) Initiator Latency Timer (HECI1_MLT) Header Type (HECI1_HTYPE) Built In Self-Test (HECI1_BIST) MMIO Base Address Low (HECI1_MMIO_MBAR_LO) MMIO Base Address High (HECI1_MMIO_MBAR_HI) Sub System Identifiers (HECI1_SS) Capabilities Pointer (HECI1_CAP) Interrupt Information (HECI1_INTR) Minimum Grant (HECI1_MGNT) Maximum Latency (HECI1_MLAT) Host Firmware Status Crash Log (HECI1_HFS) Miscellaneous Shadow (HECI1_MISC_SHDW) General Status Shadow 1 CrashLog (HECI1_GS_SHDW1) Host General Status (HECI1_H_GS1) PCI Power Management Capability ID (HECI1_PID) PCI Power Management Capabilities (HECI1_PC) PCI Power Management Control And Status (HECI1_PMCS) General Status Shadow 2 CrashLog (HECI1_GS_SHDW2) General Status Shadow 3 CrashLog (HECI1_GS_SHDW3) General Status Shadow 4 CrashLog (HECI1_GS_SHDW4) General Status Shadow 5 CrashLog (HECI1_GS_SHDW5) Host General Status 2 (HECI1_H_GS2) Host General Status 3 (HECI1_H_GS3) Message Signaled Interrupt Identifiers (HECI1_MID) Message Signaled Interrupt Message Control (HECI1_MC) Message Signaled Interrupt Message Address (HECI1_MA) Message Signaled Interrupt Upper Address (HECI1_MUA) Message Signaled Interrupt Message Data (HECI1_MD) Interrupt Delivery Mode (HECI1_HIDM) Vendor Specific Capability Register (HECI1_VSCR) Vendor Specific Extended Capability Register (HECI1_VSEC) SW LTR Pointer Register (HECI1_SWLTRPTR) Device Idle Pointer Register (HECI1_DEVIDLEPTR) Device Idle Power On Latency (HECI1_DEVIDLEPOL) DevIdle Power Control Enabled Register (HECI1_PWRCTRLEN) Host Extend Register Status (HECI1_HERS) Host Extend Register DW1 (HECI1_HER1) Host Extend Register DW2 (HECI1_HER2) Host Extend Register DW3 (HECI1_HER3) Host Extend Register DW4 (HECI1_HER4) Host Extend Register DW5 (HECI1_HER5) Host Extend Register DW6 (HECI1_HER6) Host Extend Register DW7 (HECI1_HER7) Host Extend Register DW8 (HECI1_HER8)
Identification (HECI1_ID)
Command (HECI1_CMD)
Status (HECI1_STS)
Revision ID And Class Code (HECI1_RID_CC)
Cache Line Size (HECI1_CLS)
Initiator Latency Timer (HECI1_MLT)
Header Type (HECI1_HTYPE)
Built In Self-Test (HECI1_BIST)
MMIO Base Address Low (HECI1_MMIO_MBAR_LO)
MMIO Base Address High (HECI1_MMIO_MBAR_HI)
Sub System Identifiers (HECI1_SS)
Capabilities Pointer (HECI1_CAP)
Interrupt Information (HECI1_INTR)
Minimum Grant (HECI1_MGNT)
Maximum Latency (HECI1_MLAT)
Host Firmware Status Crash Log (HECI1_HFS)
Miscellaneous Shadow (HECI1_MISC_SHDW)
General Status Shadow 1 CrashLog (HECI1_GS_SHDW1)
Host General Status (HECI1_H_GS1)
PCI Power Management Capability ID (HECI1_PID)
PCI Power Management Capabilities (HECI1_PC)
PCI Power Management Control And Status (HECI1_PMCS)
General Status Shadow 2 CrashLog (HECI1_GS_SHDW2)
General Status Shadow 3 CrashLog (HECI1_GS_SHDW3)
General Status Shadow 4 CrashLog (HECI1_GS_SHDW4)
General Status Shadow 5 CrashLog (HECI1_GS_SHDW5)
Host General Status 2 (HECI1_H_GS2)
Host General Status 3 (HECI1_H_GS3)
Message Signaled Interrupt Identifiers (HECI1_MID)
Message Signaled Interrupt Message Control (HECI1_MC)
Message Signaled Interrupt Message Address (HECI1_MA)
Message Signaled Interrupt Upper Address (HECI1_MUA)
Message Signaled Interrupt Message Data (HECI1_MD)
Interrupt Delivery Mode (HECI1_HIDM)
Vendor Specific Capability Register (HECI1_VSCR)
Vendor Specific Extended Capability Register (HECI1_VSEC)
SW LTR Pointer Register (HECI1_SWLTRPTR)
Device Idle Pointer Register (HECI1_DEVIDLEPTR)
Device Idle Power On Latency (HECI1_DEVIDLEPOL)
DevIdle Power Control Enabled Register (HECI1_PWRCTRLEN)
Host Extend Register Status (HECI1_HERS)
Host Extend Register DW1 (HECI1_HER1)
Host Extend Register DW2 (HECI1_HER2)
Host Extend Register DW3 (HECI1_HER3)
Host Extend Register DW4 (HECI1_HER4)
Host Extend Register DW5 (HECI1_HER5)
Host Extend Register DW6 (HECI1_HER6)
Host Extend Register DW7 (HECI1_HER7)
Host Extend Register DW8 (HECI1_HER8)
Intel® Trace Hub PCI Configuration (D31:F7)
Intel® Trace Hub PCI Configuration (D31:F7) Vendor ID Register (VID) Command Register (CMD) Class Code Register (RID) Header Type Register (HT) MSC Trace Buffer Lower BAR (MTB_LBAR) MSC Trace Buffer Upper BAR (MTB_UBAR) Software Lower BAR (SW_LBAR) Software Upper BAR (SW_UBAR) RTIT Lower BAR (RTIT_LBAR) RTIT Upper BAR (RTIT_UBAR) Subsystem Vendor ID (SVID) Capabilities Pointer (CAP) Interrupt Line (INTL) MSI Capability ID (MSICID) MSI Lower Message Address (MSILMA) MSI Upper Message Address (MSIUMA) MSI Message Data (MSIMD) Firmware Lower Bar (FW_LBAR) Firmware Upper Bar (FW_UBAR) Device Specific Control (NPKDSC) Power Control Enable Register (DEVIDLEPCE)
Vendor ID Register (VID)
Command Register (CMD)
Class Code Register (RID)
Header Type Register (HT)
MSC Trace Buffer Lower BAR (MTB_LBAR)
MSC Trace Buffer Upper BAR (MTB_UBAR)
Software Lower BAR (SW_LBAR)
Software Upper BAR (SW_UBAR)
RTIT Lower BAR (RTIT_LBAR)
RTIT Upper BAR (RTIT_UBAR)
Subsystem Vendor ID (SVID)
Capabilities Pointer (CAP)
Interrupt Line (INTL)
MSI Capability ID (MSICID)
MSI Lower Message Address (MSILMA)
MSI Upper Message Address (MSIUMA)
MSI Message Data (MSIMD)
Firmware Lower Bar (FW_LBAR)
Firmware Upper Bar (FW_UBAR)
Device Specific Control (NPKDSC)
Power Control Enable Register (DEVIDLEPCE)
Intel® Trusted Execution Technology Configuration
Intel® Trusted Execution Technology Configuration Status Register (STS) Error Status Register (ESTS) Crash Register (CRASH) SPAD Done Register (SPAD_DONE) DID Register (DIDVID) LT EMC Version Number Register (VER_EMIF) SINIT Memory Base Register (SINIT_MEMORY_BASE) SINIT Memory Size Register (SINIT_MEMORY_SIZE) SVMM Join Base Register (SVMM_JOIN) Heap Base (HEAP_BASE) Heap Size (HEAP_SIZE) DMA Protected Range (DPR) Scratchpad (LT_SCRATCHPAD6)
Status Register (STS)
Error Status Register (ESTS)
Crash Register (CRASH)
SPAD Done Register (SPAD_DONE)
DID Register (DIDVID)
LT EMC Version Number Register (VER_EMIF)
SINIT Memory Base Register (SINIT_MEMORY_BASE)
SINIT Memory Size Register (SINIT_MEMORY_SIZE)
SVMM Join Base Register (SVMM_JOIN)
Heap Base (HEAP_BASE)
Heap Size (HEAP_SIZE)
DMA Protected Range (DPR)
Scratchpad (LT_SCRATCHPAD6)
Intergrated Sensor Hub (ISH) PCI Configuration (D18:F0)
Intergrated Sensor Hub (ISH) PCI Configuration (D18:F0) Device Id And Vendor Id Register (DEVVENDID) Status And Command (STATUSCOMMAND) Revision Id And Class Code (REVCLASSCODE) Cache Line Latency Header And Bist (CLLATHEADERBIST) Base Address Register (BAR) Base Address Register High (BAR_HIGH) Base Address Register1 (BAR1) Base Address Register1 High (BAR1_HIGH) Subsystem Vendor And Subsystem Id (SUBSYSTEMID) Expansion Rom Base Address (EXPANSION_ROM_BASEADDR) Capabilities Pointer (CAPABILITYPTR) Interrupt Register (INTERRUPTREG) Power Management Capability Id (POWERCAPID) Power Management Control And Status Register (PMECTRLSTATUS) Pci Device Idle Vendor Capability Register (PCIDEVIDLE_CAP_RECORD) Vendor Specific Extended Capability Register (DEVID_VEND_SPECIFIC_REG) Software Ltr Update Mmio Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG) Device Idle Pointer Register (DEVICE_IDLE_POINTER_REG) D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG) General Purpose Input Register (GEN_INPUT_REG) Msi Capability Register (MSI_CAP_REG) Msi Message Low Address (MSI_ADDR_LOW) Msi Message High Address (MSI_ADDR_HIGH) Msi Message Data (MSI_MSG_DATA) Msi Mask Register (MSI_MASK) Msi Pending Register (MSI_PENDING)
Device Id And Vendor Id Register (DEVVENDID)
Status And Command (STATUSCOMMAND)
Revision Id And Class Code (REVCLASSCODE)
Cache Line Latency Header And Bist (CLLATHEADERBIST)
Base Address Register (BAR)
Base Address Register High (BAR_HIGH)
Base Address Register1 (BAR1)
Base Address Register1 High (BAR1_HIGH)
Subsystem Vendor And Subsystem Id (SUBSYSTEMID)
Expansion Rom Base Address (EXPANSION_ROM_BASEADDR)
Capabilities Pointer (CAPABILITYPTR)
Interrupt Register (INTERRUPTREG)
Power Management Capability Id (POWERCAPID)
Power Management Control And Status Register (PMECTRLSTATUS)
Pci Device Idle Vendor Capability Register (PCIDEVIDLE_CAP_RECORD)
Vendor Specific Extended Capability Register (DEVID_VEND_SPECIFIC_REG)
Software Ltr Update Mmio Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device Idle Pointer Register (DEVICE_IDLE_POINTER_REG)
D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG)
General Purpose Input Register (GEN_INPUT_REG)
Msi Capability Register (MSI_CAP_REG)
Msi Message Low Address (MSI_ADDR_LOW)
Msi Message High Address (MSI_ADDR_HIGH)
Msi Message Data (MSI_MSG_DATA)
Msi Mask Register (MSI_MASK)
Msi Pending Register (MSI_PENDING)
Interrupt I/O
Interrupt I/O Master Initialization Command Word 1 (MICW1) Master Operational Control Word 2 (MOCW2) Master Operational Control Word 3 (MOCW3) Master Initialization Command Word 2 (MICW2) Master Initialization Command Word 3 (MICW3) Master Initialization Command Word 4 (MICW4) Master Operational Control Word 1 (MOCW1) Slave Initialization Command Word 1 (SICW1) Slave Operational Control Word 2 (SOCW2) Slave Operational Control Word 3 (SOCW3) Slave Initialization Command Word 2 (SICW2) Slave Initialization Command Word 3 (SICW3) Slave Initialization Command Word 4 (SICW4) Slave Operational Control Word 1 (SOCW1) Master Edge/Level Control (ELCR1) Slave Edge/Level Control (ELCR2)
Master Initialization Command Word 1 (MICW1)
Master Operational Control Word 2 (MOCW2)
Master Operational Control Word 3 (MOCW3)
Master Initialization Command Word 2 (MICW2)
Master Initialization Command Word 3 (MICW3)
Master Initialization Command Word 4 (MICW4)
Master Operational Control Word 1 (MOCW1)
Slave Initialization Command Word 1 (SICW1)
Slave Operational Control Word 2 (SOCW2)
Slave Operational Control Word 3 (SOCW3)
Slave Initialization Command Word 2 (SICW2)
Slave Initialization Command Word 3 (SICW3)
Slave Initialization Command Word 4 (SICW4)
Slave Operational Control Word 1 (SOCW1)
Master Edge/Level Control (ELCR1)
Slave Edge/Level Control (ELCR2)
Interrupt PCR
Interrupt PCR PIRQA Routing Control (PARC) PIRQB Routing Control (PBRC) PIRQC Routing Control (PCRC) PIRQD Routing Control (PDRC) PIRQE Routing Control (PERC) PIRQF Routing Control (PFRC) PIRQG Routing Control (PGRC) PIRQH Routing Control (PHRC) Message Decoder Control (MSGDC) PCI Interrupt Route 0 (PIR0) PCI Interrupt Route 1 (PIR1) PCI Interrupt Route 2 (PIR2) PCI Interrupt Route 3 (PIR3) PCI Interrupt Route 4 (PIR4) PCI Interrupt Route 5 (PIR5) PCI Interrupt Route 6 (PIR6) PCI Interrupt Route 7 (PIR7) PCI Interrupt Route 8 (PIR8) PCI Interrupt Route 9 (PIR9) PCI Interrupt Route 10 (PIR10) PCI Interrupt Route 11 (PIR11) PCI Interrupt Route 12 (PIR12) PCI Interrupt Route 13 (PIR13) PCI Interrupt Route 14 (PIR14) PCI Interrupt Route 15 (PIR15) PCI Interrupt Route 16 (PIR16) PCI Interrupt Route 17 (PIR17) PCI Interrupt Route 18 (PIR18) PCI Interrupt Route 19 (PIR19) PCI Interrupt Route 20 (PIR20) PCI Interrupt Route 21 (PIR21) PCI Interrupt Route 22 (PIR22) PCI Interrupt Route 23 (PIR23) PCI Interrupt Route 24 (PIR24) PCI Interrupt Route 25 (PIR25) PCI Interrupt Route 26 (PIR26) PCI Interrupt Route 27 (PIR27) PCI Interrupt Route 28 (PIR28) PCI Interrupt Route 29 (PIR29) PCI Interrupt Route 30 (PIR30) PCI Interrupt Route 31 (PIR31) General Interrupt Control (GIC) Interrupt Polarity Control 0 (IPC0) Interrupt Polarity Control 1 (IPC1) Interrupt Polarity Control 2 (IPC2) Interrupt Polarity Control 3 (IPC3) Interrupt Blocking Control (IBC) Interrupt Edge-Trigger Extension 0 (IETE0) Interrupt Edge-Trigger Extension 1 (IETE1) Interrupt Edge-Trigger Extension 2 (IETE2) Interrupt Edge-Trigger Extension 3 (IETE3) ITSS Power Reduction Control (ITSSPRC) SIDE Clock Timing (SIDECT) IPCI Clock Timing (IPCICT) PGCB Clock Timing (PGCBCT) Uncorrectable Error Mask (UEM) Uncorrectable Error Severity (UEV) Correctable Error Mask (CEM) NMI Control (NMI) Master Message Control (MMC) Master Message Status (MMSTS)
PIRQA Routing Control (PARC)
PIRQB Routing Control (PBRC)
PIRQC Routing Control (PCRC)
PIRQD Routing Control (PDRC)
PIRQE Routing Control (PERC)
PIRQF Routing Control (PFRC)
PIRQG Routing Control (PGRC)
PIRQH Routing Control (PHRC)
Message Decoder Control (MSGDC)
PCI Interrupt Route 0 (PIR0)
PCI Interrupt Route 1 (PIR1)
PCI Interrupt Route 2 (PIR2)
PCI Interrupt Route 3 (PIR3)
PCI Interrupt Route 4 (PIR4)
PCI Interrupt Route 5 (PIR5)
PCI Interrupt Route 6 (PIR6)
PCI Interrupt Route 7 (PIR7)
PCI Interrupt Route 8 (PIR8)
PCI Interrupt Route 9 (PIR9)
PCI Interrupt Route 10 (PIR10)
PCI Interrupt Route 11 (PIR11)
PCI Interrupt Route 12 (PIR12)
PCI Interrupt Route 13 (PIR13)
PCI Interrupt Route 14 (PIR14)
PCI Interrupt Route 15 (PIR15)
PCI Interrupt Route 16 (PIR16)
PCI Interrupt Route 17 (PIR17)
PCI Interrupt Route 18 (PIR18)
PCI Interrupt Route 19 (PIR19)
PCI Interrupt Route 20 (PIR20)
PCI Interrupt Route 21 (PIR21)
PCI Interrupt Route 22 (PIR22)
PCI Interrupt Route 23 (PIR23)
PCI Interrupt Route 24 (PIR24)
PCI Interrupt Route 25 (PIR25)
PCI Interrupt Route 26 (PIR26)
PCI Interrupt Route 27 (PIR27)
PCI Interrupt Route 28 (PIR28)
PCI Interrupt Route 29 (PIR29)
PCI Interrupt Route 30 (PIR30)
PCI Interrupt Route 31 (PIR31)
General Interrupt Control (GIC)
Interrupt Polarity Control 0 (IPC0)
Interrupt Polarity Control 1 (IPC1)
Interrupt Polarity Control 2 (IPC2)
Interrupt Polarity Control 3 (IPC3)
Interrupt Blocking Control (IBC)
Interrupt Edge-Trigger Extension 0 (IETE0)
Interrupt Edge-Trigger Extension 1 (IETE1)
Interrupt Edge-Trigger Extension 2 (IETE2)
Interrupt Edge-Trigger Extension 3 (IETE3)
ITSS Power Reduction Control (ITSSPRC)
SIDE Clock Timing (SIDECT)
IPCI Clock Timing (IPCICT)
PGCB Clock Timing (PGCBCT)
Uncorrectable Error Mask (UEM)
Uncorrectable Error Severity (UEV)
Correctable Error Mask (CEM)
NMI Control (NMI)
Master Message Control (MMC)
Master Message Status (MMSTS)
iSCLK Camera Registers
iSCLK Camera Registers CAMERA1 (camera1) CAMERA2 (camera2) CAMERA2 (camera3)
CAMERA1 (camera1)
CAMERA2 (camera2)
CAMERA2 (camera3)
Keyboard and Text (KT) Redirection PCI Configuration (D22:F3)
Keyboard and Text (KT) Redirection PCI Configuration (D22:F3) Device ID And Vendor ID (KT_HOST_DID_VID) Status And Command (KT_HOST_STS_CMD) Class Code And Revision ID (KT_HOST_CC_RID) BIST, Header Type, Latency Timer, And Cache Line Size (KT_HOST_BIST_HTYPE_LT_CLS) KT IO BAR (KT_HOST_IOBAR) KT Memory BAR (KT_HOST_MEMBAR) Cardbus CIS Pointer (KT_HOST_CCP) Subsystem ID And Subsystem Vendor ID (KT_HOST_SID_SVID) Expansion ROM Base Address (KT_HOST_XRBAR) Capabilities List Pointer (KT_HOST_CAPP) Maximum Latency, Minimum Grant, Interrupt Pin And Interrupt Line (KT_HOST_MAXL_MING_INTP_INTL) MSI Message Control, Next Pointer And Capability ID (KT_HOST_MSIMC_MSINP_MSICID) MSI Message Address (KT_HOST_MSIMA) MSI Message Upper Address (KT_HOST_MSIMUA) MSI Message Data (KT_HOST_MSIMD) Power Management Capabilities, Next Pointer And Capability ID (KT_HOST_PMCAP_PMNP_PMCID) Power Management Data, Control/Status Register Bridge Support Extensions, Control And Status (KT_HOST_PMD_PMCSRBSE_PMCSR)
Device ID And Vendor ID (KT_HOST_DID_VID)
Status And Command (KT_HOST_STS_CMD)
Class Code And Revision ID (KT_HOST_CC_RID)
BIST, Header Type, Latency Timer, And Cache Line Size (KT_HOST_BIST_HTYPE_LT_CLS)
KT IO BAR (KT_HOST_IOBAR)
KT Memory BAR (KT_HOST_MEMBAR)
Cardbus CIS Pointer (KT_HOST_CCP)
Subsystem ID And Subsystem Vendor ID (KT_HOST_SID_SVID)
Expansion ROM Base Address (KT_HOST_XRBAR)
Capabilities List Pointer (KT_HOST_CAPP)
Maximum Latency, Minimum Grant, Interrupt Pin And Interrupt Line (KT_HOST_MAXL_MING_INTP_INTL)
MSI Message Control, Next Pointer And Capability ID (KT_HOST_MSIMC_MSINP_MSICID)
MSI Message Address (KT_HOST_MSIMA)
MSI Message Upper Address (KT_HOST_MSIMUA)
MSI Message Data (KT_HOST_MSIMD)
Power Management Capabilities, Next Pointer And Capability ID (KT_HOST_PMCAP_PMNP_PMCID)
Power Management Data, Control/Status Register Bridge Support Extensions, Control And Status (KT_HOST_PMD_PMCSRBSE_PMCSR)
P2SB Bridge PCI Configuration (D31:F1, D18:F1)
P2SB Bridge PCI Configuration (D31:F1, D18:F1) PCI Status (PCISTS) Revision ID (PCIRID_CC) Sideband Register Access BAR (SBREG_BAR) Sideband Register BAR High DWORD (SBREG_BARH) PCI Subsystem Identifiers (PCIHSS) PCI Capabilities Pointer (CAPPTR) VLW Bus:Device:Function (VBDF) High Performance Event Timer Configuration (HPTC) IOxAPIC Configuration (IOAC) IOxAPIC Bus:Device:Function (IBDF) HPET Bus:Device:Function (HBDF) PCI Express Capability List Register (EXPCAPLST) PCI Express Capabilities Register (EXPCAP) Device Capabilities Register (DEVCAP) Device Control Register (DEVCTL) Device Status Register (DEVSTS) Link Capabilities Register (LNKCAP) Link Control Register (LNKCTL) Link Status Register (LNKSTS) SBI Address (SBIADDR) SBI Data (SBIDATA) SBI Status (SBISTAT) SBI Routing Identification (SBIRID) SBI Extended Address (SBIEXTADDR) P2SB Control (P2SBC) Power Control Enable (PCE) Unsupported Request Error Status (URES) Unsupported Request Error Control (UREC) Sideband Register Posted 0 (SBREGPOSTED0) Sideband Register Posted 1 (SBREGPOSTED1) Sideband Register Posted 2 (SBREGPOSTED2) Sideband Register Posted 3 (SBREGPOSTED3) Sideband Register Posted 4 (SBREGPOSTED4) Sideband Register Posted 5 (SBREGPOSTED5) Sideband Register Posted 6 (SBREGPOSTED6) Sideband Register Posted 7 (SBREGPOSTED7) Endpoint Mask 0 (EPMASK0) Endpoint Mask 1 (EPMASK1) Endpoint Mask 2 (EPMASK2) Endpoint Mask 3 (EPMASK3) Endpoint Mask 4 (EPMASK4) Endpoint Mask 5 (EPMASK5) Endpoint Mask 6 (EPMASK6) Endpoint Mask 7 (EPMASK7)
PCI Status (PCISTS)
Revision ID (PCIRID_CC)
Sideband Register Access BAR (SBREG_BAR)
Sideband Register BAR High DWORD (SBREG_BARH)
PCI Subsystem Identifiers (PCIHSS)
PCI Capabilities Pointer (CAPPTR)
VLW Bus:Device:Function (VBDF)
High Performance Event Timer Configuration (HPTC)
IOxAPIC Configuration (IOAC)
IOxAPIC Bus:Device:Function (IBDF)
HPET Bus:Device:Function (HBDF)
PCI Express Capability List Register (EXPCAPLST)
PCI Express Capabilities Register (EXPCAP)
Device Capabilities Register (DEVCAP)
Device Control Register (DEVCTL)
Device Status Register (DEVSTS)
Link Capabilities Register (LNKCAP)
Link Control Register (LNKCTL)
Link Status Register (LNKSTS)
SBI Address (SBIADDR)
SBI Data (SBIDATA)
SBI Status (SBISTAT)
SBI Routing Identification (SBIRID)
SBI Extended Address (SBIEXTADDR)
P2SB Control (P2SBC)
Power Control Enable (PCE)
Unsupported Request Error Status (URES)
Unsupported Request Error Control (UREC)
Sideband Register Posted 0 (SBREGPOSTED0)
Sideband Register Posted 1 (SBREGPOSTED1)
Sideband Register Posted 2 (SBREGPOSTED2)
Sideband Register Posted 3 (SBREGPOSTED3)
Sideband Register Posted 4 (SBREGPOSTED4)
Sideband Register Posted 5 (SBREGPOSTED5)
Sideband Register Posted 6 (SBREGPOSTED6)
Sideband Register Posted 7 (SBREGPOSTED7)
Endpoint Mask 0 (EPMASK0)
Endpoint Mask 1 (EPMASK1)
Endpoint Mask 2 (EPMASK2)
Endpoint Mask 3 (EPMASK3)
Endpoint Mask 4 (EPMASK4)
Endpoint Mask 5 (EPMASK5)
Endpoint Mask 6 (EPMASK6)
Endpoint Mask 7 (EPMASK7)
PCI Express* (PCIe*) Configuration (D28:F0/1/2/3/4/5/6/7)
PCI Express* (PCIe*) Configuration (D28:F0/1/2/3/4/5/6/7) PCIE Identifiers (ID) Device Command (CMD) Primary Status (PSTS) Revision ID (RID_CC) Cache Line Size (CLS) Primary Latency Timer (PLT) Header Type (HTYPE) Base Address Register 0 (BAR0) Base Address Register 1 (BAR1) Bus Numbers (BNUM_SLT) I/O Base And Limit (IOBL) Secondary Status (SSTS) Memory Base And Limit (MBL) Prefetchable Memory Base And Limit (PMBL) Prefetchable Memory Base Upper 32 Bits (PMBU32) Prefetchable Memory Limit Upper 32 Bits (PMLU32) Capabilities List Pointer (CAPP) Interrupt Information Byte 0 (INTRB0) Interrupt Information Byte 1 (INTRB1) Bridge Control (BCTRL) Capabilities List (CLIST) PCI Express Capabilities (XCAP) Device Capabilities (DCAP) Device Control (DCTL) Device Status (DSTS) Link Capabilities (LCAP) Link Control (LCTL) Link Status (LSTS) Slot Capabilities (SLCAP) Slot Control (SLCTL) Slot Status (SLSTS) Root Control (RCTL) Root Capabilities (ROOTCAP) Root Status (RSTS) Device Capabilities 2 (DCAP2) Device Control 2 (DCTL2) Link Capabilities 2 (LCAP2) Link Control 2 (LCTL2) Link Status 2 (LSTS2) Message Signaled Interrupt Identifiers (MID) Message Signaled Interrupt Message (MC) Message Signaled Interrupt Message Address (MA) Message Signaled Interrupt Message Upper Address (MUA) Message Signaled Interrupt Message Data (MD) Subsystem Vendor Capability (SVCAP) Subsystem Vendor IDs (SVID) Power Management Capability (PMCAP) PCI Power Management Capabilities (PMC) PCI Power Management Control (PMCS) Advanced Error Extended (AECH) Uncorrectable Error Status (UES) Uncorrectable Error Mask (UEM) Uncorrectable Error Severity (UEV) Correctable Error Status (CES) Correctable Error Mask (CEM) Advanced Error Capabilities And Control (AECC) Root Error Command (REC) Root Error Status (RES) Error Source Identification (ESID) PTM Extended Capability Header (PTMECH) PTM Capability Register (PTMCAPR) PTM Control Register (PTMCTLR) L1 Sub-States Extended Capability Header (L1SECH) L1 Sub-States Capabilities (L1SCAP) L1 Sub-States Control 1 (L1SCTL1) L1 Sub-States Control 2 (L1SCTL2) ACS Extended Capability Header (ACSECH) ACS Capability Register (ACSCAPR) ACS Control Register (ACSCTLR) Port VC Capability Register 1 (PVCCR1) Port VC Capability 2 (PVCC2) Port VC Control (PVCC) Port VC Status (PVCS) Virtual Channel 0 Resource Capability (V0VCRC) Virtual Channel 0 Resource Control (V0CTL) Virtual Channel 0 Resource Status (V0STS) Virtual Channel 1 Resource Capability (V1VCRC) Virtual Channel 1 Resource Control (V1CTL) Virtual Channel 1 Resource Status (V1STS) Latency Tolerance Reporting Override 2 (LTROVR2) DPC Extended Capability Header (DPCECH) DPC Capability Register (DPCCAPR) DPC Control Register (DPCCTLR) DPC Status Register (DPCSR) DPC Error Source ID Register (DPCESIDR) RP PIO Status Register (RPPIOSR) RP PIO Mask Register (RPPIOMR) RP PIO Severity Register (RPPIOVR) RP PIO SysError Register (RPPIOSER) RP PIO Exception Register (RPPIOER) RP PIO Header Log DW1 Register (RPPIOHLR_DW1) RP PIO Header Log DW2 Register (RPPIOHLR_DW2) RP PIO Header Log DW3 Register (RPPIOHLR_DW3) RP PIO Header Log DW4 Register (RPPIOHLR_DW4) Secondary PCI Express Extended Capability Header (SPEECH) Link Control 3 (LCTL3) Lane Error Status (LES) Data Link Feature Extended Capability Header (DLFECH) Data Link Feature Capabilities Register (DLFCAP) Data Link Feature Status Register (DLFSTS) Physical Layer 16.0 GT/s Extended Capability Header (PL16GECH) Physical Layer 16.0 GT/s Status Register (PL16S) Physical Layer 16.0 GT/s First Retimer Data Parity Mismatch Status Register (PL16FRDPMS) Physical Layer 16.0 GT/s Second Retimer Data Parity Mismatch Status Register (PL16SRDPMS) Physical Layer 32.0 GT/s Extended Capability Header (G5ECH) Physical Layer 32.0 GT/s Capability Register (G5CAP) Physical Layer 32.0 GT/s Control Register (G5CTL) Physical Layer 32.0 GT/s Status Register (G5STS) Receiver Modified TS Data 1 Register (RCVDMODTSDATA1) Receiver Modified TS Data 2 Register (RCVDMODTSDATA2) Transmitted Modified TS Data 1 Register (TRNSMODTSDATA1) Transmitted Modified TS Data 2 Register (TRNSMODTSDATA2) Alternate Protocol Extended Capability Header (APEC) Alternate Protocol Capabilities Register (APCAPR) Alternate Protocol Control Register (APCTRLR) Alternate Protocol Data 1 Register (APD1R) Alternate Protocol Data 2 Register (APD2R) Alternate Protocol Selective Enable Mask Register (APSEMR) Multicast Extended Capability Header (MCECH) Multicast Extended Capability Register (MCAPR) Multicast Control Register (MCCTLR) Multicast Base Address Register 1 (MCBADRR1) Multicast Base Address Register 2 (MCBADRR2) Multicast Receive Register (MCRR) Multicast Block All Register (MCBAR) Multicast Block Untranslated Register (MCBUR) Multicast Overlay BAR 1 (MCOB1) Multicast Overlay BAR 2 (MCOB2) VNN Removal Control (VNNREMCTL)
PCIE Identifiers (ID)
Device Command (CMD)
Primary Status (PSTS)
Revision ID (RID_CC)
Cache Line Size (CLS)
Primary Latency Timer (PLT)
Header Type (HTYPE)
Base Address Register 0 (BAR0)
Base Address Register 1 (BAR1)
Bus Numbers (BNUM_SLT)
I/O Base And Limit (IOBL)
Secondary Status (SSTS)
Memory Base And Limit (MBL)
Prefetchable Memory Base And Limit (PMBL)
Prefetchable Memory Base Upper 32 Bits (PMBU32)
Prefetchable Memory Limit Upper 32 Bits (PMLU32)
Capabilities List Pointer (CAPP)
Interrupt Information Byte 0 (INTRB0)
Interrupt Information Byte 1 (INTRB1)
Bridge Control (BCTRL)
Capabilities List (CLIST)
PCI Express Capabilities (XCAP)
Device Capabilities (DCAP)
Device Control (DCTL)
Device Status (DSTS)
Link Capabilities (LCAP)
Link Control (LCTL)
Link Status (LSTS)
Slot Capabilities (SLCAP)
Slot Control (SLCTL)
Slot Status (SLSTS)
Root Control (RCTL)
Root Capabilities (ROOTCAP)
Root Status (RSTS)
Device Capabilities 2 (DCAP2)
Device Control 2 (DCTL2)
Link Capabilities 2 (LCAP2)
Link Control 2 (LCTL2)
Link Status 2 (LSTS2)
Message Signaled Interrupt Identifiers (MID)
Message Signaled Interrupt Message (MC)
Message Signaled Interrupt Message Address (MA)
Message Signaled Interrupt Message Upper Address (MUA)
Message Signaled Interrupt Message Data (MD)
Subsystem Vendor Capability (SVCAP)
Subsystem Vendor IDs (SVID)
Power Management Capability (PMCAP)
PCI Power Management Capabilities (PMC)
PCI Power Management Control (PMCS)
Advanced Error Extended (AECH)
Uncorrectable Error Status (UES)
Uncorrectable Error Mask (UEM)
Uncorrectable Error Severity (UEV)
Correctable Error Status (CES)
Correctable Error Mask (CEM)
Advanced Error Capabilities And Control (AECC)
Root Error Command (REC)
Root Error Status (RES)
Error Source Identification (ESID)
PTM Extended Capability Header (PTMECH)
PTM Capability Register (PTMCAPR)
PTM Control Register (PTMCTLR)
L1 Sub-States Extended Capability Header (L1SECH)
L1 Sub-States Capabilities (L1SCAP)
L1 Sub-States Control 1 (L1SCTL1)
L1 Sub-States Control 2 (L1SCTL2)
ACS Extended Capability Header (ACSECH)
ACS Capability Register (ACSCAPR)
ACS Control Register (ACSCTLR)
Port VC Capability Register 1 (PVCCR1)
Port VC Capability 2 (PVCC2)
Port VC Control (PVCC)
Port VC Status (PVCS)
Virtual Channel 0 Resource Capability (V0VCRC)
Virtual Channel 0 Resource Control (V0CTL)
Virtual Channel 0 Resource Status (V0STS)
Virtual Channel 1 Resource Capability (V1VCRC)
Virtual Channel 1 Resource Control (V1CTL)
Virtual Channel 1 Resource Status (V1STS)
Latency Tolerance Reporting Override 2 (LTROVR2)
DPC Extended Capability Header (DPCECH)
DPC Capability Register (DPCCAPR)
DPC Control Register (DPCCTLR)
DPC Status Register (DPCSR)
DPC Error Source ID Register (DPCESIDR)
RP PIO Status Register (RPPIOSR)
RP PIO Mask Register (RPPIOMR)
RP PIO Severity Register (RPPIOVR)
RP PIO SysError Register (RPPIOSER)
RP PIO Exception Register (RPPIOER)
RP PIO Header Log DW1 Register (RPPIOHLR_DW1)
RP PIO Header Log DW2 Register (RPPIOHLR_DW2)
RP PIO Header Log DW3 Register (RPPIOHLR_DW3)
RP PIO Header Log DW4 Register (RPPIOHLR_DW4)
Secondary PCI Express Extended Capability Header (SPEECH)
Link Control 3 (LCTL3)
Lane Error Status (LES)
Data Link Feature Extended Capability Header (DLFECH)
Data Link Feature Capabilities Register (DLFCAP)
Data Link Feature Status Register (DLFSTS)
Physical Layer 16.0 GT/s Extended Capability Header (PL16GECH)
Physical Layer 16.0 GT/s Status Register (PL16S)
Physical Layer 16.0 GT/s First Retimer Data Parity Mismatch Status Register (PL16FRDPMS)
Physical Layer 16.0 GT/s Second Retimer Data Parity Mismatch Status Register (PL16SRDPMS)
Physical Layer 32.0 GT/s Extended Capability Header (G5ECH)
Physical Layer 32.0 GT/s Capability Register (G5CAP)
Physical Layer 32.0 GT/s Control Register (G5CTL)
Physical Layer 32.0 GT/s Status Register (G5STS)
Receiver Modified TS Data 1 Register (RCVDMODTSDATA1)
Receiver Modified TS Data 2 Register (RCVDMODTSDATA2)
Transmitted Modified TS Data 1 Register (TRNSMODTSDATA1)
Transmitted Modified TS Data 2 Register (TRNSMODTSDATA2)
Alternate Protocol Extended Capability Header (APEC)
Alternate Protocol Capabilities Register (APCAPR)
Alternate Protocol Control Register (APCTRLR)
Alternate Protocol Data 1 Register (APD1R)
Alternate Protocol Data 2 Register (APD2R)
Alternate Protocol Selective Enable Mask Register (APSEMR)
Multicast Extended Capability Header (MCECH)
Multicast Extended Capability Register (MCAPR)
Multicast Control Register (MCCTLR)
Multicast Base Address Register 1 (MCBADRR1)
Multicast Base Address Register 2 (MCBADRR2)
Multicast Receive Register (MCRR)
Multicast Block All Register (MCBAR)
Multicast Block Untranslated Register (MCBUR)
Multicast Overlay BAR 1 (MCOB1)
Multicast Overlay BAR 2 (MCOB2)
VNN Removal Control (VNNREMCTL)
PCI Express* (PCIe*) Configuration (D6:F0/1) (Gen 5)
PCI Express* (PCIe*) Configuration (D6:F0/1) (Gen 5) PCIE Identifiers (ID) Device Command (CMD) Primary Status (PSTS) Revision ID (RID_CC) Cache Line Size (CLS) Primary Latency Timer (PLT) Header Type (HTYPE) Base Address Register 0 (BAR0) Base Address Register 1 (BAR1) Bus Numbers (BNUM_SLT) I/O Base And Limit (IOBL) Secondary Status (SSTS) Memory Base And Limit (MBL) Prefetchable Memory Base And Limit (PMBL) Prefetchable Memory Base Upper 32 Bits (PMBU32) Prefetchable Memory Limit Upper 32 Bits (PMLU32) Capabilities List Pointer (CAPP) Interrupt Information Byte 0 (INTRB0) Interrupt Information Byte 1 (INTRB1) Bridge Control (BCTRL) Capabilities List (CLIST) PCI Express Capabilities (XCAP) Device Capabilities (DCAP) Device Control (DCTL) Device Status (DSTS) Link Capabilities (LCAP) Link Control (LCTL) Link Status (LSTS) Slot Capabilities (SLCAP) Slot Control (SLCTL) Slot Status (SLSTS) Root Control (RCTL) Root Capabilities (ROOTCAP) Root Status (RSTS) Device Capabilities 2 (DCAP2) Device Control 2 (DCTL2) Link Capabilities 2 (LCAP2) Link Control 2 (LCTL2) Link Status 2 (LSTS2) Message Signaled Interrupt Identifiers (MID) Message Signaled Interrupt Message (MC) Message Signaled Interrupt Message Address (MA) Message Signaled Interrupt Message Upper Address (MUA) Message Signaled Interrupt Message Data (MD) Subsystem Vendor Capability (SVCAP) Subsystem Vendor IDs (SVID) Power Management Capability (PMCAP) PCI Power Management Capabilities (PMC) PCI Power Management Control (PMCS) Advanced Error Extended (AECH) Uncorrectable Error Status (UES) Uncorrectable Error Mask (UEM) Uncorrectable Error Severity (UEV) Correctable Error Status (CES) Correctable Error Mask (CEM) Advanced Error Capabilities And Control (AECC) Root Error Command (REC) Root Error Status (RES) Error Source Identification (ESID) PTM Extended Capability Header (PTMECH) PTM Capability Register (PTMCAPR) PTM Control Register (PTMCTLR) L1 Sub-States Extended Capability Header (L1SECH) L1 Sub-States Capabilities (L1SCAP) L1 Sub-States Control 1 (L1SCTL1) L1 Sub-States Control 2 (L1SCTL2) ACS Extended Capability Header (ACSECH) ACS Capability Register (ACSCAPR) ACS Control Register (ACSCTLR) Port VC Capability Register 1 (PVCCR1) Port VC Capability 2 (PVCC2) Port VC Control (PVCC) Port VC Status (PVCS) Virtual Channel 0 Resource Capability (V0VCRC) Virtual Channel 0 Resource Control (V0CTL) Virtual Channel 0 Resource Status (V0STS) Virtual Channel 1 Resource Capability (V1VCRC) Virtual Channel 1 Resource Control (V1CTL) Virtual Channel 1 Resource Status (V1STS) DPC Extended Capability Header (DPCECH) DPC Capability Register (DPCCAPR) DPC Control Register (DPCCTLR) DPC Status Register (DPCSR) DPC Error Source ID Register (DPCESIDR) RP PIO Status Register (RPPIOSR) RP PIO Mask Register (RPPIOMR) RP PIO Severity Register (RPPIOVR) RP PIO SysError Register (RPPIOSER) RP PIO Exception Register (RPPIOER) RP PIO Header Log DW1 Register (RPPIOHLR_DW1) RP PIO Header Log DW2 Register (RPPIOHLR_DW2) RP PIO Header Log DW3 Register (RPPIOHLR_DW3) RP PIO Header Log DW4 Register (RPPIOHLR_DW4) Secondary PCI Express Extended Capability Header (SPEECH) Link Control 3 (LCTL3) Lane Error Status (LES) Data Link Feature Extended Capability Header (DLFECH) Data Link Feature Capabilities Register (DLFCAP) Data Link Feature Status Register (DLFSTS) Physical Layer 16.0 GT/s Extended Capability Header (PL16GECH) Physical Layer 16.0 GT/s Status Register (PL16S) Physical Layer 16.0 GT/s First Retimer Data Parity Mismatch Status Register (PL16FRDPMS) Physical Layer 16.0 GT/s Second Retimer Data Parity Mismatch Status Register (PL16SRDPMS) Physical Layer 32.0 GT/s Extended Capability Header (G5ECH) Physical Layer 32.0 GT/s Capability Register (G5CAP) Physical Layer 32.0 GT/s Control Register (G5CTL) Physical Layer 32.0 GT/s Status Register (G5STS) Receiver Modified TS Data 1 Register (RCVDMODTSDATA1) Receiver Modified TS Data 2 Register (RCVDMODTSDATA2) Transmitted Modified TS Data 1 Register (TRNSMODTSDATA1) Transmitted Modified TS Data 2 Register (TRNSMODTSDATA2) Alternate Protocol Extended Capability Header (APEC) Alternate Protocol Capabilities Register (APCAPR) Alternate Protocol Control Register (APCTRLR) Alternate Protocol Data 1 Register (APD1R) Alternate Protocol Data 2 Register (APD2R) Alternate Protocol Selective Enable Mask Register (APSEMR) Multicast Extended Capability Header (MCECH) Multicast Extended Capability Register (MCAPR) Multicast Control Register (MCCTLR) Multicast Base Address Register 1 (MCBADRR1) Multicast Base Address Register 2 (MCBADRR2) Multicast Receive Register (MCRR) Multicast Block All Register (MCBAR) Multicast Block Untranslated Register (MCBUR) Multicast Overlay BAR 1 (MCOB1) Multicast Overlay BAR 2 (MCOB2) VNN Removal Control (VNNREMCTL)
PCIE Identifiers (ID)
Device Command (CMD)
Primary Status (PSTS)
Revision ID (RID_CC)
Cache Line Size (CLS)
Primary Latency Timer (PLT)
Header Type (HTYPE)
Base Address Register 0 (BAR0)
Base Address Register 1 (BAR1)
Bus Numbers (BNUM_SLT)
I/O Base And Limit (IOBL)
Secondary Status (SSTS)
Memory Base And Limit (MBL)
Prefetchable Memory Base And Limit (PMBL)
Prefetchable Memory Base Upper 32 Bits (PMBU32)
Prefetchable Memory Limit Upper 32 Bits (PMLU32)
Capabilities List Pointer (CAPP)
Interrupt Information Byte 0 (INTRB0)
Interrupt Information Byte 1 (INTRB1)
Bridge Control (BCTRL)
Capabilities List (CLIST)
PCI Express Capabilities (XCAP)
Device Capabilities (DCAP)
Device Control (DCTL)
Device Status (DSTS)
Link Capabilities (LCAP)
Link Control (LCTL)
Link Status (LSTS)
Slot Capabilities (SLCAP)
Slot Control (SLCTL)
Slot Status (SLSTS)
Root Control (RCTL)
Root Capabilities (ROOTCAP)
Root Status (RSTS)
Device Capabilities 2 (DCAP2)
Device Control 2 (DCTL2)
Link Capabilities 2 (LCAP2)
Link Control 2 (LCTL2)
Link Status 2 (LSTS2)
Message Signaled Interrupt Identifiers (MID)
Message Signaled Interrupt Message (MC)
Message Signaled Interrupt Message Address (MA)
Message Signaled Interrupt Message Upper Address (MUA)
Message Signaled Interrupt Message Data (MD)
Subsystem Vendor Capability (SVCAP)
Subsystem Vendor IDs (SVID)
Power Management Capability (PMCAP)
PCI Power Management Capabilities (PMC)
PCI Power Management Control (PMCS)
Advanced Error Extended (AECH)
Uncorrectable Error Status (UES)
Uncorrectable Error Mask (UEM)
Uncorrectable Error Severity (UEV)
Correctable Error Status (CES)
Correctable Error Mask (CEM)
Advanced Error Capabilities And Control (AECC)
Root Error Command (REC)
Root Error Status (RES)
Error Source Identification (ESID)
PTM Extended Capability Header (PTMECH)
PTM Capability Register (PTMCAPR)
PTM Control Register (PTMCTLR)
L1 Sub-States Extended Capability Header (L1SECH)
L1 Sub-States Capabilities (L1SCAP)
L1 Sub-States Control 1 (L1SCTL1)
L1 Sub-States Control 2 (L1SCTL2)
ACS Extended Capability Header (ACSECH)
ACS Capability Register (ACSCAPR)
ACS Control Register (ACSCTLR)
Port VC Capability Register 1 (PVCCR1)
Port VC Capability 2 (PVCC2)
Port VC Control (PVCC)
Port VC Status (PVCS)
Virtual Channel 0 Resource Capability (V0VCRC)
Virtual Channel 0 Resource Control (V0CTL)
Virtual Channel 0 Resource Status (V0STS)
Virtual Channel 1 Resource Capability (V1VCRC)
Virtual Channel 1 Resource Control (V1CTL)
Virtual Channel 1 Resource Status (V1STS)
DPC Extended Capability Header (DPCECH)
DPC Capability Register (DPCCAPR)
DPC Control Register (DPCCTLR)
DPC Status Register (DPCSR)
DPC Error Source ID Register (DPCESIDR)
RP PIO Status Register (RPPIOSR)
RP PIO Mask Register (RPPIOMR)
RP PIO Severity Register (RPPIOVR)
RP PIO SysError Register (RPPIOSER)
RP PIO Exception Register (RPPIOER)
RP PIO Header Log DW1 Register (RPPIOHLR_DW1)
RP PIO Header Log DW2 Register (RPPIOHLR_DW2)
RP PIO Header Log DW3 Register (RPPIOHLR_DW3)
RP PIO Header Log DW4 Register (RPPIOHLR_DW4)
Secondary PCI Express Extended Capability Header (SPEECH)
Link Control 3 (LCTL3)
Lane Error Status (LES)
Data Link Feature Extended Capability Header (DLFECH)
Data Link Feature Capabilities Register (DLFCAP)
Data Link Feature Status Register (DLFSTS)
Physical Layer 16.0 GT/s Extended Capability Header (PL16GECH)
Physical Layer 16.0 GT/s Status Register (PL16S)
Physical Layer 16.0 GT/s First Retimer Data Parity Mismatch Status Register (PL16FRDPMS)
Physical Layer 16.0 GT/s Second Retimer Data Parity Mismatch Status Register (PL16SRDPMS)
Physical Layer 32.0 GT/s Extended Capability Header (G5ECH)
Physical Layer 32.0 GT/s Capability Register (G5CAP)
Physical Layer 32.0 GT/s Control Register (G5CTL)
Physical Layer 32.0 GT/s Status Register (G5STS)
Receiver Modified TS Data 1 Register (RCVDMODTSDATA1)
Receiver Modified TS Data 2 Register (RCVDMODTSDATA2)
Transmitted Modified TS Data 1 Register (TRNSMODTSDATA1)
Transmitted Modified TS Data 2 Register (TRNSMODTSDATA2)
Alternate Protocol Extended Capability Header (APEC)
Alternate Protocol Capabilities Register (APCAPR)
Alternate Protocol Control Register (APCTRLR)
Alternate Protocol Data 1 Register (APD1R)
Alternate Protocol Data 2 Register (APD2R)
Alternate Protocol Selective Enable Mask Register (APSEMR)
Multicast Extended Capability Header (MCECH)
Multicast Extended Capability Register (MCAPR)
Multicast Control Register (MCCTLR)
Multicast Base Address Register 1 (MCBADRR1)
Multicast Base Address Register 2 (MCBADRR2)
Multicast Receive Register (MCRR)
Multicast Block All Register (MCBAR)
Multicast Block Untranslated Register (MCBUR)
Multicast Overlay BAR 1 (MCOB1)
Multicast Overlay BAR 2 (MCOB2)
VNN Removal Control (VNNREMCTL)
PMC I/O Based
PMC I/O Based Power Management 1 Enables and Status (PM1_EN_STS) Power Management 1 Control (PM1_CNT) Power Management 1 Timer (PM1_TMR) General Purpose Event 1 Status [31:0] (GPE1_STS_31_0) General Purpose Event 1 Status [63:32] (GPE1_STS_63_32) General Purpose Event 1 Status [63:32] (GPE1_STS_95_64) General Purpose Event 1 Enable [31:0] (GPE1_EN_31_0) General Purpose Event 1 Enable [63:32] (GPE1_EN_63_32) General Purpose Event 1 Enable [63:32] (GPE1_EN_95_64) SMI Control and Enable (SMI_EN) SMI Status Register (SMI_STS) SMI Control and Enable 1 (SMI_EN_1) SMI Status Register 1 (SMI_STS_1) General Purpose Event Control (GPE_CTRL) Device Trap Status Register (DEVTRAP_STS) Therm Timer Delay Register (THERM_TIMER_DELAY) PM2a Control Block (PM2A_CNT_BLK) Over-Clocking WDT Control (OC_WDT_CTL) General Purpose Event 0 Status [31:0] (GPE0_STS_31_0) General Purpose Event 0 Status [63:32] (GPE0_STS_63_32) General Purpose Event 0 Status [95:64] (GPE0_STS_95_64) General Purpose Event 0 Status [127:96] (GPE0_STS_127_96) General Purpose Event 0 Enable [31:0] (GPE0_EN_31_0) General Purpose Event 0 Enable [63:32] (GPE0_EN_63_32) General Purpose Event 0 Enable [95:64] (GPE0_EN_95_64) General Purpose Event 0 Enable [127:96] (GPE0_EN_127_96)
Power Management 1 Enables and Status (PM1_EN_STS)
Power Management 1 Control (PM1_CNT)
Power Management 1 Timer (PM1_TMR)
General Purpose Event 1 Status [31:0] (GPE1_STS_31_0)
General Purpose Event 1 Status [63:32] (GPE1_STS_63_32)
General Purpose Event 1 Status [63:32] (GPE1_STS_95_64)
General Purpose Event 1 Enable [31:0] (GPE1_EN_31_0)
General Purpose Event 1 Enable [63:32] (GPE1_EN_63_32)
General Purpose Event 1 Enable [63:32] (GPE1_EN_95_64)
SMI Control and Enable (SMI_EN)
SMI Status Register (SMI_STS)
SMI Control and Enable 1 (SMI_EN_1)
SMI Status Register 1 (SMI_STS_1)
General Purpose Event Control (GPE_CTRL)
Device Trap Status Register (DEVTRAP_STS)
Therm Timer Delay Register (THERM_TIMER_DELAY)
PM2a Control Block (PM2A_CNT_BLK)
Over-Clocking WDT Control (OC_WDT_CTL)
General Purpose Event 0 Status [31:0] (GPE0_STS_31_0)
General Purpose Event 0 Status [63:32] (GPE0_STS_63_32)
General Purpose Event 0 Status [95:64] (GPE0_STS_95_64)
General Purpose Event 0 Status [127:96] (GPE0_STS_127_96)
General Purpose Event 0 Enable [31:0] (GPE0_EN_31_0)
General Purpose Event 0 Enable [63:32] (GPE0_EN_63_32)
General Purpose Event 0 Enable [95:64] (GPE0_EN_95_64)
General Purpose Event 0 Enable [127:96] (GPE0_EN_127_96)
PMC MMIO
PMC MMIO General PM Configuration A (GEN_PMCON_A) General PM Configuration B (GEN_PMCON_B) Configured Revision ID (CRID) Extended Test Mode Register 3 (ETR3) SET STRAP MSG LOCK (SSML) SET STRAP MSG CONTROL (SSMC) SET STRAP MSG DATA (SSMD) Configured Revision ID (CRID_UIP) SLP S0 DEBUG REG0 (SLP_S0_DBG_0) SLP S0 DEBUG REG1 (SLP_S0_DBG_1) SLP S0 DEBUG REG2 (SLP_S0_DBG_2) HSIO Power Management Configuration Reg 1 (MODPHY_PM_CFG1) HSIO Power Management Configuration Reg 2 (MODPHY_PM_CFG2) HSIO Power Management Configuration Reg 3 (MODPHY_PM_CFG3) HSIO Power Management Configuration Reg 4 (MODPHY_PM_CFG4) HSIO Power Management Configuration Reg 5 (MODPHY_PM_CFG5) HSIO Power Management Configuration Reg 6 (MODPHY_PM_CFG6) EXT FET RAMP CFG (EXT_FET_RAMP_CFG) VCCIN AUX CONFIG Register (VCCIN_AUX_CFG) Always Running Timer Value 31:0 (ARTV_31_0) Always Running Timer Value 31:0 (ARTV_63_32) Always Running Timer Value Control (ARTV_CTRL) Timed GPIO Control 0 (TGPIOCTL0) Timed GPIO 0 Comparator Value 31:0 (TGPIOCOMPV0_31_0) Timed GPIO Comparator Value 63:32 (TGPIOCOMPV0_63_32) Timed GPIO0 Periodic Interval Value 31_0 (TGPIOPIV0_31_0) Timed GPIO 0 Periodic Interval Value 63_32 (TGPIOPIV0_63_32) Timed GPIO Time Capture Register 31_0 (TGPIOTCV0_31_0) Timed GPIO0 Time Capture Register 63_32 (TGPIOTCV0_63_32) Timed GPIO0 Event Counter Capture Register 31_0 (TGPIOECCV0_31_0) Timed GPIO0 Event Counter Capture Register 63_32 (TGPIOECCV0_63_32) Timed GPIO0 Event Counter Register 31_0 (TGPIOEC0_31_0) Timed GPIO0 Event Counter Register 63_32 (TGPIOEC0_63_32) Timed GPIO Control 1 (TGPIOCTL1) Timed GPIO 1 Comparator Value 31:0 (TGPIOCOMPV1_31_0) Timed GPIO Comparator Value 63:32 (TGPIOCOMPV1_63_32) Timed GPIO1 Periodic Interval Value 31_0 (TGPIOPIV1_31_0) Timed GPIO 1 Periodic Interval Value 63_32 (TGPIOPIV1_63_32) Timed GPIO Time Capture Register 31_0 (TGPIOTCV1_31_0) Timed GPIO Time Capture Register 63_32 (TGPIOTCV1_63_32) Timed GPIO0 Event Counter Capture Register 31_0 (TGPIOECCV1_31_0) Timed GPIO0 Event Counter Capture Register 63_32 (TGPIOECCV1_63_32) Timed GPIO1 Event Counter Register 31_0 (TGPIOEC1_31_0) Timed GPIO Event Counter Register 63_32 (TGPIOEC1_63_32) Min Temperature (MIN_TEMP) Max Temperature (MAX_TEMP) Catastrophic Trip Point Enable (CTEN) EC Thermal Sensor Reporting Enable (ECRPTEN) Throttle Level (TL) Throttle Levels Enable (TLEN) Thermal Sensor Alert High Value (TSAHV) Thermal Sensor Alert Low Value (TSALV) Thermal Alert Trip Status (TAS) PCH Hot Level Control (PHLC) Temperature Sensor Control and Status (TSS0) SoC-to-IOE Force Thermal Throttling Control (S2I_FTT_CTRL) SoC Internal Fabric Thermal Throttling Configuration (SOCIFTTC) Telemetry Mailbox Interface Register (TELEMETRY_MB_INTERFACE) Telemtry Mailbox Data 0 Register (TELEMETRY_MB_DATA0) Telemtry Mailbox Data 1 Register (TELEMETRY_MB_DATA1) Telemtry Mailbox Data 2 Register (TELEMETRY_MB_DATA2) Telemtry Mailbox Data 3 Register (TELEMETRY_MB_DATA3) Low Power Mode Enable (LPM_EN) Low Power Mode 0 Residency Counter (LPM_0_RES) Low Power Mode 1 Residency Counter (LPM_1_RES) Low Power Mode 2 Residency Counter (LPM_2_RES) Low Power Mode 3 Residency Counter (LPM_3_RES) Low Power Mode 4 Residency Counter (LPM_4_RES) Low Power Mode 5 Residency Counter (LPM_5_RES) Low Power Mode 6 Residency Counter (LPM_6_RES) Low Power Mode 7 Residency Counter (LPM_7_RES) Wake Alarm Device Timer: AC (WADT_AC) Wake Alarm Device Timer: DC (WADT_DC) Wake Alarm Device Expired Timer: AC (WADT_EXP_AC) Wake Alarm Device Expired Timer: DC (WADT_EXP_DC) Power and Reset Status (PRSTS) Power Management Configuration Reg 1 (PM_CFG) S3 Power Gating Policies (S3_PWRGATE_POL) S4 Power Gating Policies (S4_PWRGATE_POL) S5 Power Gating Policies (S5_PWRGATE_POL) DeepSx Configuration (DSX_CFG) Power Management Configuration Reg 2 (PM_CFG2) Power Management Configuration Reg 3 (PM_CFG3) Power Management Configuration Reg 4 (PM_CFG4) CPU Early Power-on Configuration (CPU_EPOC) ACPI Timer Control (ACPI_TMR_CTL) Last TSC Alarm Value[31:0] (TSC_ALARM_LO) Last TSC Alarm Value[63:32] (TSC_ALARM_HI) GPIO Configuration (GPIO_CFG) Global Reset Causes 0 (GBLRST_CAUSE0) Global Reset Causes 1 (GBLRST_CAUSE1) Host Partition Reset Causes (HPR_CAUSE0) Latency Limit Residency 0 (LAT_LIM_RES_0) Latency Limit Residency 1 (LAT_LIM_RES_1) Latency Limit Residency 2 (LAT_LIM_RES_2) SLP_S0 Residency (SLP_S0_RESIDENCY) Latency Limit Control (LATENCY_LIMIT_CONTROL) ACPI Control (ACTL) S0 Residency (S0_RES) PGD PFET Enable Ack Status Register 0 (PPFEAR0) PGD PFET Enable Ack Status Register 1 (PPFEAR1) PGD PFET Enable Ack Status Register 1 (PPFEAR2) PGD PG_REQ Status Register 0 (PPRSR0) PGD PG_REQ Status Register 1 (PPRSR1) PGD PG_REQ Status Register 1 (PPRSR2) ST_PG_FDIS_PMC - Register 1 (ST_PG_FDIS_PMC_1) ST_PG_FDIS_PMC - Register 2 (ST_PG_FDIS_PMC_2) MPHY LASSOC 0 (MPHY_LASSOC_0) MPHY LASSOC 1 (MPHY_LASSOC_1) BIOS SMI and Legacy USB SMI Counter (BIOS_LEGACY_USB_SMI_CNTR) GPE0 SMI and GPIO SMI Counter (GPE0_GPIO_SMI_CNTR) MCSMI SMI and DEVMON SMI Counter (MCSMI_DEVMON_SMI_CNTR) Periodic SMI and TCO SMI Counter (TCO_PERIODIC_SMI_CNTR) Legacy USB2 SMI and Thermal SMI Counter (LEGACY_USB2_THERM_SMI_CNTR) Monitor SMI and Internal TT SMI Counter (MONITOR_INTERNAL_TT_SMI_CNTR) SPI SMI and GPIO Unlock SMI Counter (SPI_GPIO_UNLOCK_SMI_CNTR) ESPI SMI and LPSS SMI Counter (ESPI_LPSS_SMI_CNTR) ME SMI and XHCI SMI Counter (ME_XHCI_SMI_CNTR) TC XHCI SMI and OSSE SMI Counter (TC_XHCI_OSSE_SMI_CNTR)
General PM Configuration A (GEN_PMCON_A)
General PM Configuration B (GEN_PMCON_B)
Configured Revision ID (CRID)
Extended Test Mode Register 3 (ETR3)
SET STRAP MSG LOCK (SSML)
SET STRAP MSG CONTROL (SSMC)
SET STRAP MSG DATA (SSMD)
Configured Revision ID (CRID_UIP)
SLP S0 DEBUG REG0 (SLP_S0_DBG_0)
SLP S0 DEBUG REG1 (SLP_S0_DBG_1)
SLP S0 DEBUG REG2 (SLP_S0_DBG_2)
HSIO Power Management Configuration Reg 1 (MODPHY_PM_CFG1)
HSIO Power Management Configuration Reg 2 (MODPHY_PM_CFG2)
HSIO Power Management Configuration Reg 3 (MODPHY_PM_CFG3)
HSIO Power Management Configuration Reg 4 (MODPHY_PM_CFG4)
HSIO Power Management Configuration Reg 5 (MODPHY_PM_CFG5)
HSIO Power Management Configuration Reg 6 (MODPHY_PM_CFG6)
EXT FET RAMP CFG (EXT_FET_RAMP_CFG)
VCCIN AUX CONFIG Register (VCCIN_AUX_CFG)
Always Running Timer Value 31:0 (ARTV_31_0)
Always Running Timer Value 31:0 (ARTV_63_32)
Always Running Timer Value Control (ARTV_CTRL)
Timed GPIO Control 0 (TGPIOCTL0)
Timed GPIO 0 Comparator Value 31:0 (TGPIOCOMPV0_31_0)
Timed GPIO Comparator Value 63:32 (TGPIOCOMPV0_63_32)
Timed GPIO0 Periodic Interval Value 31_0 (TGPIOPIV0_31_0)
Timed GPIO 0 Periodic Interval Value 63_32 (TGPIOPIV0_63_32)
Timed GPIO Time Capture Register 31_0 (TGPIOTCV0_31_0)
Timed GPIO0 Time Capture Register 63_32 (TGPIOTCV0_63_32)
Timed GPIO0 Event Counter Capture Register 31_0 (TGPIOECCV0_31_0)
Timed GPIO0 Event Counter Capture Register 63_32 (TGPIOECCV0_63_32)
Timed GPIO0 Event Counter Register 31_0 (TGPIOEC0_31_0)
Timed GPIO0 Event Counter Register 63_32 (TGPIOEC0_63_32)
Timed GPIO Control 1 (TGPIOCTL1)
Timed GPIO 1 Comparator Value 31:0 (TGPIOCOMPV1_31_0)
Timed GPIO Comparator Value 63:32 (TGPIOCOMPV1_63_32)
Timed GPIO1 Periodic Interval Value 31_0 (TGPIOPIV1_31_0)
Timed GPIO 1 Periodic Interval Value 63_32 (TGPIOPIV1_63_32)
Timed GPIO Time Capture Register 31_0 (TGPIOTCV1_31_0)
Timed GPIO Time Capture Register 63_32 (TGPIOTCV1_63_32)
Timed GPIO0 Event Counter Capture Register 31_0 (TGPIOECCV1_31_0)
Timed GPIO0 Event Counter Capture Register 63_32 (TGPIOECCV1_63_32)
Timed GPIO1 Event Counter Register 31_0 (TGPIOEC1_31_0)
Timed GPIO Event Counter Register 63_32 (TGPIOEC1_63_32)
Min Temperature (MIN_TEMP)
Max Temperature (MAX_TEMP)
Catastrophic Trip Point Enable (CTEN)
EC Thermal Sensor Reporting Enable (ECRPTEN)
Throttle Level (TL)
Throttle Levels Enable (TLEN)
Thermal Sensor Alert High Value (TSAHV)
Thermal Sensor Alert Low Value (TSALV)
Thermal Alert Trip Status (TAS)
PCH Hot Level Control (PHLC)
Temperature Sensor Control and Status (TSS0)
SoC-to-IOE Force Thermal Throttling Control (S2I_FTT_CTRL)
SoC Internal Fabric Thermal Throttling Configuration (SOCIFTTC)
Telemetry Mailbox Interface Register (TELEMETRY_MB_INTERFACE)
Telemtry Mailbox Data 0 Register (TELEMETRY_MB_DATA0)
Telemtry Mailbox Data 1 Register (TELEMETRY_MB_DATA1)
Telemtry Mailbox Data 2 Register (TELEMETRY_MB_DATA2)
Telemtry Mailbox Data 3 Register (TELEMETRY_MB_DATA3)
Low Power Mode Enable (LPM_EN)
Low Power Mode 0 Residency Counter (LPM_0_RES)
Low Power Mode 1 Residency Counter (LPM_1_RES)
Low Power Mode 2 Residency Counter (LPM_2_RES)
Low Power Mode 3 Residency Counter (LPM_3_RES)
Low Power Mode 4 Residency Counter (LPM_4_RES)
Low Power Mode 5 Residency Counter (LPM_5_RES)
Low Power Mode 6 Residency Counter (LPM_6_RES)
Low Power Mode 7 Residency Counter (LPM_7_RES)
Wake Alarm Device Timer: AC (WADT_AC)
Wake Alarm Device Timer: DC (WADT_DC)
Wake Alarm Device Expired Timer: AC (WADT_EXP_AC)
Wake Alarm Device Expired Timer: DC (WADT_EXP_DC)
Power and Reset Status (PRSTS)
Power Management Configuration Reg 1 (PM_CFG)
S3 Power Gating Policies (S3_PWRGATE_POL)
S4 Power Gating Policies (S4_PWRGATE_POL)
S5 Power Gating Policies (S5_PWRGATE_POL)
DeepSx Configuration (DSX_CFG)
Power Management Configuration Reg 2 (PM_CFG2)
Power Management Configuration Reg 3 (PM_CFG3)
Power Management Configuration Reg 4 (PM_CFG4)
CPU Early Power-on Configuration (CPU_EPOC)
ACPI Timer Control (ACPI_TMR_CTL)
Last TSC Alarm Value[31:0] (TSC_ALARM_LO)
Last TSC Alarm Value[63:32] (TSC_ALARM_HI)
GPIO Configuration (GPIO_CFG)
Global Reset Causes 0 (GBLRST_CAUSE0)
Global Reset Causes 1 (GBLRST_CAUSE1)
Host Partition Reset Causes (HPR_CAUSE0)
Latency Limit Residency 0 (LAT_LIM_RES_0)
Latency Limit Residency 1 (LAT_LIM_RES_1)
Latency Limit Residency 2 (LAT_LIM_RES_2)
SLP_S0 Residency (SLP_S0_RESIDENCY)
Latency Limit Control (LATENCY_LIMIT_CONTROL)
ACPI Control (ACTL)
S0 Residency (S0_RES)
PGD PFET Enable Ack Status Register 0 (PPFEAR0)
PGD PFET Enable Ack Status Register 1 (PPFEAR1)
PGD PFET Enable Ack Status Register 1 (PPFEAR2)
PGD PG_REQ Status Register 0 (PPRSR0)
PGD PG_REQ Status Register 1 (PPRSR1)
PGD PG_REQ Status Register 1 (PPRSR2)
ST_PG_FDIS_PMC - Register 1 (ST_PG_FDIS_PMC_1)
ST_PG_FDIS_PMC - Register 2 (ST_PG_FDIS_PMC_2)
MPHY LASSOC 0 (MPHY_LASSOC_0)
MPHY LASSOC 1 (MPHY_LASSOC_1)
BIOS SMI and Legacy USB SMI Counter (BIOS_LEGACY_USB_SMI_CNTR)
GPE0 SMI and GPIO SMI Counter (GPE0_GPIO_SMI_CNTR)
MCSMI SMI and DEVMON SMI Counter (MCSMI_DEVMON_SMI_CNTR)
Periodic SMI and TCO SMI Counter (TCO_PERIODIC_SMI_CNTR)
Legacy USB2 SMI and Thermal SMI Counter (LEGACY_USB2_THERM_SMI_CNTR)
Monitor SMI and Internal TT SMI Counter (MONITOR_INTERNAL_TT_SMI_CNTR)
SPI SMI and GPIO Unlock SMI Counter (SPI_GPIO_UNLOCK_SMI_CNTR)
ESPI SMI and LPSS SMI Counter (ESPI_LPSS_SMI_CNTR)
ME SMI and XHCI SMI Counter (ME_XHCI_SMI_CNTR)
TC XHCI SMI and OSSE SMI Counter (TC_XHCI_OSSE_SMI_CNTR)
PMC PCI Configuration (D31:F2)
PMC PCI Configuration (D31:F2) Device Vendor ID (DEVVENDID) Status and Command (STATUSCOMMAND) Revision Class Codes (REVCLASSCODE) Cache Line Latency Header And BIST (CLLATHEADERBIST) Base Address Register (BAR) (BAR) Base Address Register (BAR) High (BAR_HIGH) Base Address Register 1 (BAR1) (BAR1) Base Address Register 1 (BAR1) High (BAR1_HIGH) Base Address Register 2 (BAR 2) (BAR2) Subsystem Identifiers (SUBSYSTEMID) EXPANSION ROM base address (EXPANSION_ROM_BASEADDR) Capabilities Pointer (CAPABILITYPTR) Interrupt Register (INTERRUPTREG) PowerManagement Capability ID (POWERCAPID) Power Management Control and Status (PMECTRLSTATUS) PCI Device Idle Capability Record (PCIDEVIDLE_CAP_RECORD) Device Vendor Specific (DEVID_VEND_SPECIFIC_REG) D0I3 Control SW LTR MMIO (D0I3_CONTROL_SW_LTR_MMIO_REG) Device IDLE pointer (DEVICE_IDLE_POINTER_REG) D0I3 Max Power Latency (D0I3_MAX_POW_LAT_PG_CONFIG) General Purpose Read Write Register1 (GEN_REGRW1) General Purpose Read Write Register2 (GEN_REGRW2) General Purpose Read Write Register3 (GEN_REGRW3) General Purpose Read Write Register4 (GEN_REGRW4) General Purpose Input Register (GEN_INPUT_REG)
Device Vendor ID (DEVVENDID)
Status and Command (STATUSCOMMAND)
Revision Class Codes (REVCLASSCODE)
Cache Line Latency Header And BIST (CLLATHEADERBIST)
Base Address Register (BAR) (BAR)
Base Address Register (BAR) High (BAR_HIGH)
Base Address Register 1 (BAR1) (BAR1)
Base Address Register 1 (BAR1) High (BAR1_HIGH)
Base Address Register 2 (BAR 2) (BAR2)
Subsystem Identifiers (SUBSYSTEMID)
EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)
Capabilities Pointer (CAPABILITYPTR)
Interrupt Register (INTERRUPTREG)
PowerManagement Capability ID (POWERCAPID)
Power Management Control and Status (PMECTRLSTATUS)
PCI Device Idle Capability Record (PCIDEVIDLE_CAP_RECORD)
Device Vendor Specific (DEVID_VEND_SPECIFIC_REG)
D0I3 Control SW LTR MMIO (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device IDLE pointer (DEVICE_IDLE_POINTER_REG)
D0I3 Max Power Latency (D0I3_MAX_POW_LAT_PG_CONFIG)
General Purpose Read Write Register1 (GEN_REGRW1)
General Purpose Read Write Register2 (GEN_REGRW2)
General Purpose Read Write Register3 (GEN_REGRW3)
General Purpose Read Write Register4 (GEN_REGRW4)
General Purpose Input Register (GEN_INPUT_REG)
Processor I/O
Processor I/O NMI Status and Control (NMI_STS_CNT) NMI Enable (and Real Time Clock Index) (NMI_EN) Init Register (PORT92) Reset Control Register (RST_CNT)
NMI Status and Control (NMI_STS_CNT)
NMI Enable (and Real Time Clock Index) (NMI_EN)
Init Register (PORT92)
Reset Control Register (RST_CNT)
RTC I/O
RTC I/O Seconds Value (Sec) Seconds Alarm (Sec_Alarm) Minutes Value (Minutes) Minutes Alarm (Minutes_Alarm) Hours Value (Hours) Hours Alarm (Hours_Alarm) Day Of Week (Day_of_Week) Day Of Month (Day_of_Month) Month Value (Month) Year Value (Year) Register A (Register_A) Register B General Configuration (Register_B) Register C Flag Register (Register_C) Register D Flag Register (Register_D) 114 Bytes Of Lower User RAM (Register_E) 128 Bytes Of Upper User RAM (Register_80)
Seconds Value (Sec)
Seconds Alarm (Sec_Alarm)
Minutes Value (Minutes)
Minutes Alarm (Minutes_Alarm)
Hours Value (Hours)
Hours Alarm (Hours_Alarm)
Day Of Week (Day_of_Week)
Day Of Month (Day_of_Month)
Month Value (Month)
Year Value (Year)
Register A (Register_A)
Register B General Configuration (Register_B)
Register C Flag Register (Register_C)
Register D Flag Register (Register_D)
114 Bytes Of Lower User RAM (Register_E)
128 Bytes Of Upper User RAM (Register_80)
RTC Index
RTC Index RTC Index Register (INDEX) RTC Target Register (TARGET)
RTC Index Register (INDEX)
RTC Target Register (TARGET)
RTC PCR
RTC PCR RTC Configuration (RC) Backed Up Control (BUC) SAI Policy Group 1 Control Policy (SAIPG1_CP_LO) RTC Update In Progress SMI Control (UIPSMI)
RTC Configuration (RC)
Backed Up Control (BUC)
SAI Policy Group 1 Control Policy (SAIPG1_CP_LO)
RTC Update In Progress SMI Control (UIPSMI)
Shared SRAM PCI Configuration (D20:F2)
Shared SRAM PCI Configuration (D20:F2) Device Vendor ID (DEVVENDID) STATUSCOMMAND Status and Command (STATUSCOMMAND) Revision Class Codes (REVCLASSCODE) CLLATHEADERBIST Cache Line Latency Header And BIST (CLLATHEADERBIST) 32-bit Base Address Register (BAR) BAR HIGH (BAR_HIGH) 32-bit Base Address Register1 (BAR1) BAR1 HIGH (BAR1_HIGH) Subsystem Identifiers (SUBSYSTEMID) EXPANSION ROM BASEADDR (EXPANSION_ROM_BASEADDR) CAPABILITY PTR (CAPABILITYPTR) INTERRUPT REG Interrupt Register (INTERRUPTREG) POWER CAP ID PowerManagement Capability ID (POWERCAPID) PME CTRL STATUS (PMECTRLSTATUS) PCIDEVIDLE CAP RECORD (PCIDEVIDLE_CAP_RECORD) DEVID VEND SPECIFIC REG (DEVID_VEND_SPECIFIC_REG) D0I3 CONTROL SW LTR MMIO REG (D0I3_CONTROL_SW_LTR_MMIO_REG) DEVICE IDLE POINTER REG (DEVICE_IDLE_POINTER_REG) D0I3 MAX POW LAT PG CONFIG (D0I3_MAX_POW_LAT_PG_CONFIG) GEN REG RW1 (GEN_REGRW1) GEN REG RW2 (GEN_REGRW2) GEN REG RW3 (GEN_REGRW3) GEN REG RW4 (GEN_REGRW4) GEN INPUT REG (GEN_INPUT_REG)
Device Vendor ID (DEVVENDID)
STATUSCOMMAND Status and Command (STATUSCOMMAND)
Revision Class Codes (REVCLASSCODE)
CLLATHEADERBIST Cache Line Latency Header And BIST (CLLATHEADERBIST)
32-bit Base Address Register (BAR)
BAR HIGH (BAR_HIGH)
32-bit Base Address Register1 (BAR1)
BAR1 HIGH (BAR1_HIGH)
Subsystem Identifiers (SUBSYSTEMID)
EXPANSION ROM BASEADDR (EXPANSION_ROM_BASEADDR)
CAPABILITY PTR (CAPABILITYPTR)
INTERRUPT REG Interrupt Register (INTERRUPTREG)
POWER CAP ID PowerManagement Capability ID (POWERCAPID)
PME CTRL STATUS (PMECTRLSTATUS)
PCIDEVIDLE CAP RECORD (PCIDEVIDLE_CAP_RECORD)
DEVID VEND SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)
D0I3 CONTROL SW LTR MMIO REG (D0I3_CONTROL_SW_LTR_MMIO_REG)
DEVICE IDLE POINTER REG (DEVICE_IDLE_POINTER_REG)
D0I3 MAX POW LAT PG CONFIG (D0I3_MAX_POW_LAT_PG_CONFIG)
GEN REG RW1 (GEN_REGRW1)
GEN REG RW2 (GEN_REGRW2)
GEN REG RW3 (GEN_REGRW3)
GEN REG RW4 (GEN_REGRW4)
GEN INPUT REG (GEN_INPUT_REG)
SMBus I/O
SMBus I/O Host Status Register Address (HSTS) Host Control Register (HCTL) Host Command Register (HCMD) Transmit Slave Address Register (TSA) Data 0 Register (HD0) Data 1 Register (HD1) Host Block Data (HBD) Packet Error Check Data Register (PEC) Receive Slave Address Register (RSA) Slave Data Register (SD) Auxiliary Status (AUXS) Auxiliary Control (AUXC) SMLINK_PIN_CTL Register (SMLC) SMBUS_PIN_CTL Register (SMBC) Slave Status Register (SSTS) Slave Command Register (SCMD) Notify Device Address Register (NDA) Notify Data Low Byte Register (NDLB) Notify Data High Byte Register (NDHB)
Host Status Register Address (HSTS)
Host Control Register (HCTL)
Host Command Register (HCMD)
Transmit Slave Address Register (TSA)
Data 0 Register (HD0)
Data 1 Register (HD1)
Host Block Data (HBD)
Packet Error Check Data Register (PEC)
Receive Slave Address Register (RSA)
Slave Data Register (SD)
Auxiliary Status (AUXS)
Auxiliary Control (AUXC)
SMLINK_PIN_CTL Register (SMLC)
SMBUS_PIN_CTL Register (SMBC)
Slave Status Register (SSTS)
Slave Command Register (SCMD)
Notify Device Address Register (NDA)
Notify Data Low Byte Register (NDLB)
Notify Data High Byte Register (NDHB)
SMBus MMIO
SMBus MMIO Host Status Register Address (HSTS) Host Control Register (HCTL) Host Command Register (HCMD) Transmit Slave Address Register (TSA) Data 0 Register (HD0) Data 1 Register (HD1) Host Block Data (HBD) Packet Error Check Data Register (PEC) Receive Slave Address Register (RSA) Slave Data Register (SD) Auxiliary Status (AUXS) Auxiliary Control (AUXC) SMLINK_PIN_CTL Register (SMLC) SMBUS_PIN_CTL Register (SMBC) Slave Status Register (SSTS) Slave Command Register (SCMD) Notify Device Address Register (NDA) Notify Data Low Byte Register (NDLB) Notify Data High Byte Register (NDHB)
Host Status Register Address (HSTS)
Host Control Register (HCTL)
Host Command Register (HCMD)
Transmit Slave Address Register (TSA)
Data 0 Register (HD0)
Data 1 Register (HD1)
Host Block Data (HBD)
Packet Error Check Data Register (PEC)
Receive Slave Address Register (RSA)
Slave Data Register (SD)
Auxiliary Status (AUXS)
Auxiliary Control (AUXC)
SMLINK_PIN_CTL Register (SMLC)
SMBUS_PIN_CTL Register (SMBC)
Slave Status Register (SSTS)
Slave Command Register (SCMD)
Notify Device Address Register (NDA)
Notify Data Low Byte Register (NDLB)
Notify Data High Byte Register (NDHB)
SMBus PCI Configuration (D31:F4)
SMBus PCI Configuration (D31:F4) Vendor ID (VID) Device ID (DID) Command Register (CMD) Device Status (DS) Revision ID (RID) Programming Interface (PI) Sub Class Code (SCC) Base Class Code (BCC) SMBus Memory Base Address_31_0 (SMBMBAR_31_0) SMBus Memory Base Address_63_32 (SMBMBAR_63_32) SMB Base Address (SBA) Subsystem Vendor Identifiers (SVID) Subsystem Identifiers (SID) Interrupt Line (INTLN) Interrupt Pin (INTPN) Host Configuration (HCFG) TCO Base Address (TCOBASE) TCO Control (TCOCTL) SMBus Configuration Register 80 (SMBSM)
Vendor ID (VID)
Device ID (DID)
Command Register (CMD)
Device Status (DS)
Revision ID (RID)
Programming Interface (PI)
Sub Class Code (SCC)
Base Class Code (BCC)
SMBus Memory Base Address_31_0 (SMBMBAR_31_0)
SMBus Memory Base Address_63_32 (SMBMBAR_63_32)
SMB Base Address (SBA)
Subsystem Vendor Identifiers (SVID)
Subsystem Identifiers (SID)
Interrupt Line (INTLN)
Interrupt Pin (INTPN)
Host Configuration (HCFG)
TCO Base Address (TCOBASE)
TCO Control (TCOCTL)
SMBus Configuration Register 80 (SMBSM)
SMBus PCR
SMBus PCR TCO Configuration (TCOCFG) General Control (GC) Power Control Enable (PCE)
TCO Configuration (TCOCFG)
General Control (GC)
Power Control Enable (PCE)
SMBus TCO I/O
SMBus TCO I/O TCO_RLD Register (TRLD) TCO_DAT_IN Register (TDI) TCO_DAT_OUT Register (TDO) TCO1_STS Register (TSTS1) TCO2_STS Register (TSTS2) TCO1_CNT Register (TCTL1) TCO2_CNT Register (TCTL2) TCO Message Registers (TMSG) TCO_WDSTATUS Register (TWDS) LEGACY_ELIM Register (LE) TCO_TMR Register (TTMR)
TCO_RLD Register (TRLD)
TCO_DAT_IN Register (TDI)
TCO_DAT_OUT Register (TDO)
TCO1_STS Register (TSTS1)
TCO2_STS Register (TSTS2)
TCO1_CNT Register (TCTL1)
TCO2_CNT Register (TCTL2)
TCO Message Registers (TMSG)
TCO_WDSTATUS Register (TWDS)
LEGACY_ELIM Register (LE)
TCO_TMR Register (TTMR)
SPI MMIO
SPI MMIO BIOS Flash Primary Region (BIOS_BFPREG) Hardware Sequencing Flash Status and Control (BIOS_HSFSTS_CTL) Flash Address (BIOS_FADDR) Discrete Lock Bits (BIOS_DLOCK) Flash Data (BIOS_FDATA0) Flash Data (BIOS_FDATA1) Flash Data (BIOS_FDATA2) Flash Data (BIOS_FDATA3) Flash Data (BIOS_FDATA4) Flash Data (BIOS_FDATA5) Flash Data (BIOS_FDATA6) Flash Data (BIOS_FDATA7) Flash Data (BIOS_FDATA8) Flash Data (BIOS_FDATA9) Flash Data (BIOS_FDATA10) Flash Data (BIOS_FDATA11) Flash Data (BIOS_FDATA12) Flash Data (BIOS_FDATA13) Flash Data (BIOS_FDATA14) Flash Data (BIOS_FDATA15) Flash Region Access Permissions (BIOS_FRACC) Flash Region (BIOS_FREG0) Flash Region (BIOS_FREG1) Flash Region (BIOS_FREG2) Flash Region (BIOS_FREG3) Flash Region (BIOS_FREG4) Flash Region (BIOS_FREG5) Flash Region (BIOS_FREG6) Flash Region (BIOS_FREG7) Flash Region (BIOS_FREG8) Flash Region (BIOS_FREG9) Flash Region (BIOS_FREG10) Flash Region (BIOS_FREG11) Flash Protected Range (BIOS_FPR0) Flash Protected Range (BIOS_FPR1) Flash Protected Range (BIOS_FPR2) Flash Protected Range (BIOS_FPR3) Flash Protected Range (BIOS_FPR4) Global Protected Range 0 (BIOS_GPR0) Secondary Flash Region Access Permissions (BIOS_SFRACC) Flash Descriptor Observability Control (BIOS_FDOC) Flash Descriptor Observability Data (BIOS_FDOD) Additional Flash Control (BIOS_AFC) Vendor Specific Component Capabilities for Component 0 (BIOS_SFDP0_VSCC0) Vendor Specific Component Capabilities for Component 1 (BIOS_SFDP1_VSCC1) Parameter Table Index (BIOS_PTINX) Parameter Table Data (BIOS_PTDATA) SPI Bus Requester Status (BIOS_SBRS) Flash Region (BIOS_FREG12) Flash Region (BIOS_FREG13) Flash Region (BIOS_FREG14) Flash Region (BIOS_FREG15) RPMC SFDP Table (BIOS_RPMC0_D0) RPMC SFDP Table (BIOS_RPMC1_D0) RPMC SFDP Table (BIOS_RPMC0_D1) RPMC SFDP Table (BIOS_RPMC1_D1) BIOS Master Read Access Permissions (BIOS_BM_RAP) BIOS Master Write Access Permissions (BIOS_BM_WAP)
BIOS Flash Primary Region (BIOS_BFPREG)
Hardware Sequencing Flash Status and Control (BIOS_HSFSTS_CTL)
Flash Address (BIOS_FADDR)
Discrete Lock Bits (BIOS_DLOCK)
Flash Data (BIOS_FDATA0)
Flash Data (BIOS_FDATA1)
Flash Data (BIOS_FDATA2)
Flash Data (BIOS_FDATA3)
Flash Data (BIOS_FDATA4)
Flash Data (BIOS_FDATA5)
Flash Data (BIOS_FDATA6)
Flash Data (BIOS_FDATA7)
Flash Data (BIOS_FDATA8)
Flash Data (BIOS_FDATA9)
Flash Data (BIOS_FDATA10)
Flash Data (BIOS_FDATA11)
Flash Data (BIOS_FDATA12)
Flash Data (BIOS_FDATA13)
Flash Data (BIOS_FDATA14)
Flash Data (BIOS_FDATA15)
Flash Region Access Permissions (BIOS_FRACC)
Flash Region (BIOS_FREG0)
Flash Region (BIOS_FREG1)
Flash Region (BIOS_FREG2)
Flash Region (BIOS_FREG3)
Flash Region (BIOS_FREG4)
Flash Region (BIOS_FREG5)
Flash Region (BIOS_FREG6)
Flash Region (BIOS_FREG7)
Flash Region (BIOS_FREG8)
Flash Region (BIOS_FREG9)
Flash Region (BIOS_FREG10)
Flash Region (BIOS_FREG11)
Flash Protected Range (BIOS_FPR0)
Flash Protected Range (BIOS_FPR1)
Flash Protected Range (BIOS_FPR2)
Flash Protected Range (BIOS_FPR3)
Flash Protected Range (BIOS_FPR4)
Global Protected Range 0 (BIOS_GPR0)
Secondary Flash Region Access Permissions (BIOS_SFRACC)
Flash Descriptor Observability Control (BIOS_FDOC)
Flash Descriptor Observability Data (BIOS_FDOD)
Additional Flash Control (BIOS_AFC)
Vendor Specific Component Capabilities for Component 0 (BIOS_SFDP0_VSCC0)
Vendor Specific Component Capabilities for Component 1 (BIOS_SFDP1_VSCC1)
Parameter Table Index (BIOS_PTINX)
Parameter Table Data (BIOS_PTDATA)
SPI Bus Requester Status (BIOS_SBRS)
Flash Region (BIOS_FREG12)
Flash Region (BIOS_FREG13)
Flash Region (BIOS_FREG14)
Flash Region (BIOS_FREG15)
RPMC SFDP Table (BIOS_RPMC0_D0)
RPMC SFDP Table (BIOS_RPMC1_D0)
RPMC SFDP Table (BIOS_RPMC0_D1)
RPMC SFDP Table (BIOS_RPMC1_D1)
BIOS Master Read Access Permissions (BIOS_BM_RAP)
BIOS Master Write Access Permissions (BIOS_BM_WAP)
SPI PCI Configuration (D31:F5)
SPI PCI Configuration (D31:F5) Device ID and Vendor ID (BIOS_SPI_DID_VID) Status and Command (BIOS_SPI_STS_CMD) Revision ID and Class Code (BIOS_SPI_CC_RID) BIST, Header Type, Latency Timer, Cache Line Size (BIOS_SPI_BIST_HTYPE_LT_CLS) SPI BAR0 MMIO (BIOS_SPI_BAR0) Subsystem and Vendor ID (BIOS_SPI_SID_SVID) SPI Unsupported Request Status (BIOS_SPI_UR_STS_CTL) BIOS Decode Enable (BIOS_SPI_BDE) BIOS Control (BIOS_SPI_BC) SPI BAR1 MMIO (BIOS_SPI_BAR1)
Device ID and Vendor ID (BIOS_SPI_DID_VID)
Status and Command (BIOS_SPI_STS_CMD)
Revision ID and Class Code (BIOS_SPI_CC_RID)
BIST, Header Type, Latency Timer, Cache Line Size (BIOS_SPI_BIST_HTYPE_LT_CLS)
SPI BAR0 MMIO (BIOS_SPI_BAR0)
Subsystem and Vendor ID (BIOS_SPI_SID_SVID)
SPI Unsupported Request Status (BIOS_SPI_UR_STS_CTL)
BIOS Decode Enable (BIOS_SPI_BDE)
BIOS Control (BIOS_SPI_BC)
SPI BAR1 MMIO (BIOS_SPI_BAR1)
Touch Host Controller (THC) MMIO Common
Touch Host Controller (THC) MMIO Common Device Idle Control Register (THC_M_CMN_DEVIDLECTRL) THC LTR Control Register (THC_M_CMN_LTR_CTRL)
Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
THC LTR Control Register (THC_M_CMN_LTR_CTRL)
Touch Host Controller (THC) MMIO Port
Touch Host Controller (THC) MMIO Port Touch Host Controller Control Register (THC_M_PRT_CONTROL) THC SPI Bus Configuration Register (THC_M_PRT_SPI_CFG) THC SPI Bus Read Opcode Register (THC_M_PRT_SPI_ICRRD_OPCODE) THC SPI Bus Read Opcode Register (THC_M_PRT_SPI_DMARD_OPCODE) THC SPI Bus Write Opcode Register (THC_M_PRT_SPI_WR_OPCODE) THC Interrupt Enable Register (THC_M_PRT_INT_EN) THC Interrupt Status Register (THC_M_PRT_INT_STATUS) THC Error Cause Register (THC_M_PRT_ERR_CAUSE) THC SW sequencing Control (THC_M_PRT_SW_SEQ_CNTRL) THC SW sequencing Status (THC_M_PRT_SW_SEQ_STS) THC SW Sequencing Data DW0 or SPI Address Register (THC_M_PRT_SW_SEQ_DATA0_ADDR) THC SW sequencing Data DW1 (THC_M_PRT_SW_SEQ_DATA1) THC SW sequencing Data DW2 (THC_M_PRT_SW_SEQ_DATA2) THC SW sequencing Data DW3 (THC_M_PRT_SW_SEQ_DATA3) THC SW sequencing Data DW4 (THC_M_PRT_SW_SEQ_DATA4) THC SW sequencing Data DW5 (THC_M_PRT_SW_SEQ_DATA5) THC SW sequencing Data DW6 (THC_M_PRT_SW_SEQ_DATA6) THC SW sequencing Data DW7 (THC_M_PRT_SW_SEQ_DATA7) THC SW sequencing Data DW8 (THC_M_PRT_SW_SEQ_DATA8) THC SW sequencing Data DW9 (THC_M_PRT_SW_SEQ_DATA9) THC SW sequencing Data DW10 (THC_M_PRT_SW_SEQ_DATA10) THC SW sequencing Data DW11 (THC_M_PRT_SW_SEQ_DATA11) THC SW sequencing Data DW12 (THC_M_PRT_SW_SEQ_DATA12) THC SW sequencing Data DW13 (THC_M_PRT_SW_SEQ_DATA13) THC SW sequencing Data DW14 (THC_M_PRT_SW_SEQ_DATA14) THC SW sequencing Data DW15 (THC_M_PRT_SW_SEQ_DATA15) THC SW sequencing Data DW16 (THC_M_PRT_SW_SEQ_DATA16) THC Write PRD Base Address Register Low (THC_M_PRT_WPRD_BA_LOW) THC Write PRD Base Address Register High (THC_M_PRT_WPRD_BA_HI) THC Write DMA Control (THC_M_PRT_WRITE_DMA_CNTRL) THC Write Interrupt Status (THC_M_PRT_WRITE_INT_STS) THC device address for the bulk write (THC_M_PRT_WR_BULK_ADDR) THC Device Interrupt Cause Register Address (THC_M_PRT_DEV_INT_CAUSE_ADDR) THC Device Interrupt Cause Register Value (THC_M_PRT_DEV_INT_CAUSE_REG_VAL) THC TXDMA Frame Count (THC_M_PRT_TX_FRM_CNT) THC TXDMA Packet Count (THC_M_PRT_TXDMA_PKT_CNT) THC Device Interrupt Count on this port (THC_M_PRT_DEVINT_CNT) Touch Device Interrupt Cause register Format Configuration Register 1 (THC_M_PRT_DEVINT_CFG_1) Touch Device Interrupt Cause register Format Configuration Register 2 (THC_M_PRT_DEVINT_CFG_2) THC Read PRD Base Address Low for the 1st RXDMA (THC_M_PRT_RPRD_BA_LOW_1) THC Read PRD Base Address High for the 1st RXDMA (THC_M_PRT_RPRD_BA_HI_1) THC Read PRD Control for the 1st RXDMA (THC_M_PRT_RPRD_CNTRL_1) THC Read DMA Control for the 1st RXDMA (THC_M_PRT_READ_DMA_CNTRL_1) THC Read Interrupt Status for the 1st RXDMA (THC_M_PRT_READ_DMA_INT_STS_1) THC Read DMA Error Register for the 1st RXDMA (THC_M_PRT_READ_DMA_ERR_1) Touch Sequencer GuC Tail Offset Address Low for the 1st RXDMA (THC_M_PRT_GUC_OFFSET_LOW_1) Touch Sequencer GuC Tail Offset Address High for the 1st RXDMA (THC_M_PRT_GUC_OFFSET_HI_1) Touch Host Controller GuC Work Queue Item Size for the 1st RXDMA (THC_M_PRT_GUC_WORKQ_ITEM_SZ_1) Touch Host Controller GuC Control register for the 1st RXDMA (THC_M_PRT_GUC_WORKQ_SZ_1) Touch Sequencer Control for the 1st DMA (THC_M_PRT_TSEQ_CNTRL_1) Touch Sequencer GuC Doorbell Address Low for the 1st RXDMA (THC_M_PRT_GUC_DB_ADDR_LOW_1) Touch Sequencer GuC Doorbell Address High for the 1st RXDMA (THC_M_PRT_GUC_DB_ADDR_HI_1) Touch Sequencer GuC Doorbell Data (THC_M_PRT_GUC_DB_DATA_1) Touch Sequencer GuC Tail Offset Initial Value for the 1st RXDMA (THC_M_PRT_GUC_OFFSET_INITVAL_1) THC Device Address for the bulk/touch data read for the 1st RXDMA (THC_M_PRT_RD_BULK_ADDR_1) THC Gfx/SW Doorbell Count from the 1st Stream RXDMA on this port (THC_M_PRT_DB_CNT_1) THC Frame Count from the 1st Stream RXDMA on this port (THC_M_PRT_FRM_CNT_1) THC Micro Frame Count from the 1st Stream RXDMA on this port (THC_M_PRT_UFRM_CNT_1) THC Packet Count from the 1st Stream RXDMA on this port (THC_M_PRT_RXDMA_PKT_CNT_1) THC Software Interrupt Count from the 1st Stream RXDMA on this port (THC_M_PRT_SWINT_CNT_1) Touch Sequencer Frame Drop Counter for the 1st RXDMA (THC_M_PRT_FRAME_DROP_CNT_1) THC Coaescing 1 (THC_M_PRT_COALESCE_1) THC Read PRD Base Address Low for the 2nd RXDMA (THC_M_PRT_RPRD_BA_LOW_2) THC Read PRD Base Address High for the 2nd RXDMA (THC_M_PRT_RPRD_BA_HI_2) THC Read PRD Control for the 2nd RXDMA (THC_M_PRT_RPRD_CNTRL_2) THC Read DMA Control for the 2nd RXDMA (THC_M_PRT_READ_DMA_CNTRL_2) THC Read Interrupt Status for the 2nd RXDMA (THC_M_PRT_READ_DMA_INT_STS_2) THC Read DMA Error Register for the 2nd RXDMA (THC_M_PRT_READ_DMA_ERR_2) Touch Sequencer GuC Tail Offset Address Low for the 2nd RXDMA (THC_M_PRT_GUC_OFFSET_LOW_2) Touch Sequencer GuC Tail Offset Address High for the 2nd RXDMA (THC_M_PRT_GUC_OFFSET_HI_2) Touch Host Controller GuC Work Queue Item Size for the 2nd RXDMA (THC_M_PRT_GUC_WORKQ_ITEM_SZ_2) Touch Host Controller GuC Control register for the 2nd RXDMA (THC_M_PRT_GUC_WORKQ_SZ_2) Touch Sequencer Control for the 2nd DMA (THC_M_PRT_TSEQ_CNTRL_2) Touch Sequencer GuC Doorbell Address Low for the 2nd RXDMA (THC_M_PRT_GUC_DB_ADDR_LOW_2) Touch Sequencer GuC Doorbell Address High for the 2nd RXDMA (THC_M_PRT_GUC_DB_ADDR_HI_2) Touch Sequencer GuC Doorbell Data for PRD2 (THC_M_PRT_GUC_DB_DATA_2) Touch Sequencer GuC Tail Offset Initial Value for the 2nd RXDMA (THC_M_PRT_GUC_OFFSET_INITVAL_2) THC Device Address for the bulk/touch data read for the 2nd RXDMA (THC_M_PRT_RD_BULK_ADDR_2) THC Gfx/SW Doorbell Count from the 2nd Stream RXDMA on this port (THC_M_PRT_DB_CNT_2) THC Frame Count from the 2nd Stream RXDMA on this port (THC_M_PRT_FRM_CNT_2) THC Micro Frame Count from the 2nd Stream RXDMA on this port (THC_M_PRT_UFRM_CNT_2) THC Packet Count from the 2nd Stream RXDMA on this port (THC_M_PRT_RXDMA_PKT_CNT_2) THC Software Interrupt Count from the 2nd Stream RXDMA on this port (THC_M_PRT_SWINT_CNT_2) Touch Sequencer Frame Drop Counter for the 2nd RXDMA (THC_M_PRT_FRAME_DROP_CNT_2)
Touch Host Controller Control Register (THC_M_PRT_CONTROL)
THC SPI Bus Configuration Register (THC_M_PRT_SPI_CFG)
THC SPI Bus Read Opcode Register (THC_M_PRT_SPI_ICRRD_OPCODE)
THC SPI Bus Read Opcode Register (THC_M_PRT_SPI_DMARD_OPCODE)
THC SPI Bus Write Opcode Register (THC_M_PRT_SPI_WR_OPCODE)
THC Interrupt Enable Register (THC_M_PRT_INT_EN)
THC Interrupt Status Register (THC_M_PRT_INT_STATUS)
THC Error Cause Register (THC_M_PRT_ERR_CAUSE)
THC SW sequencing Control (THC_M_PRT_SW_SEQ_CNTRL)
THC SW sequencing Status (THC_M_PRT_SW_SEQ_STS)
THC SW Sequencing Data DW0 or SPI Address Register (THC_M_PRT_SW_SEQ_DATA0_ADDR)
THC SW sequencing Data DW1 (THC_M_PRT_SW_SEQ_DATA1)
THC SW sequencing Data DW2 (THC_M_PRT_SW_SEQ_DATA2)
THC SW sequencing Data DW3 (THC_M_PRT_SW_SEQ_DATA3)
THC SW sequencing Data DW4 (THC_M_PRT_SW_SEQ_DATA4)
THC SW sequencing Data DW5 (THC_M_PRT_SW_SEQ_DATA5)
THC SW sequencing Data DW6 (THC_M_PRT_SW_SEQ_DATA6)
THC SW sequencing Data DW7 (THC_M_PRT_SW_SEQ_DATA7)
THC SW sequencing Data DW8 (THC_M_PRT_SW_SEQ_DATA8)
THC SW sequencing Data DW9 (THC_M_PRT_SW_SEQ_DATA9)
THC SW sequencing Data DW10 (THC_M_PRT_SW_SEQ_DATA10)
THC SW sequencing Data DW11 (THC_M_PRT_SW_SEQ_DATA11)
THC SW sequencing Data DW12 (THC_M_PRT_SW_SEQ_DATA12)
THC SW sequencing Data DW13 (THC_M_PRT_SW_SEQ_DATA13)
THC SW sequencing Data DW14 (THC_M_PRT_SW_SEQ_DATA14)
THC SW sequencing Data DW15 (THC_M_PRT_SW_SEQ_DATA15)
THC SW sequencing Data DW16 (THC_M_PRT_SW_SEQ_DATA16)
THC Write PRD Base Address Register Low (THC_M_PRT_WPRD_BA_LOW)
THC Write PRD Base Address Register High (THC_M_PRT_WPRD_BA_HI)
THC Write DMA Control (THC_M_PRT_WRITE_DMA_CNTRL)
THC Write Interrupt Status (THC_M_PRT_WRITE_INT_STS)
THC device address for the bulk write (THC_M_PRT_WR_BULK_ADDR)
THC Device Interrupt Cause Register Address (THC_M_PRT_DEV_INT_CAUSE_ADDR)
THC Device Interrupt Cause Register Value (THC_M_PRT_DEV_INT_CAUSE_REG_VAL)
THC TXDMA Frame Count (THC_M_PRT_TX_FRM_CNT)
THC TXDMA Packet Count (THC_M_PRT_TXDMA_PKT_CNT)
THC Device Interrupt Count on this port (THC_M_PRT_DEVINT_CNT)
Touch Device Interrupt Cause register Format Configuration Register 1 (THC_M_PRT_DEVINT_CFG_1)
Touch Device Interrupt Cause register Format Configuration Register 2 (THC_M_PRT_DEVINT_CFG_2)
THC Read PRD Base Address Low for the 1st RXDMA (THC_M_PRT_RPRD_BA_LOW_1)
THC Read PRD Base Address High for the 1st RXDMA (THC_M_PRT_RPRD_BA_HI_1)
THC Read PRD Control for the 1st RXDMA (THC_M_PRT_RPRD_CNTRL_1)
THC Read DMA Control for the 1st RXDMA (THC_M_PRT_READ_DMA_CNTRL_1)
THC Read Interrupt Status for the 1st RXDMA (THC_M_PRT_READ_DMA_INT_STS_1)
THC Read DMA Error Register for the 1st RXDMA (THC_M_PRT_READ_DMA_ERR_1)
Touch Sequencer GuC Tail Offset Address Low for the 1st RXDMA (THC_M_PRT_GUC_OFFSET_LOW_1)
Touch Sequencer GuC Tail Offset Address High for the 1st RXDMA (THC_M_PRT_GUC_OFFSET_HI_1)
Touch Host Controller GuC Work Queue Item Size for the 1st RXDMA (THC_M_PRT_GUC_WORKQ_ITEM_SZ_1)
Touch Host Controller GuC Control register for the 1st RXDMA (THC_M_PRT_GUC_WORKQ_SZ_1)
Touch Sequencer Control for the 1st DMA (THC_M_PRT_TSEQ_CNTRL_1)
Touch Sequencer GuC Doorbell Address Low for the 1st RXDMA (THC_M_PRT_GUC_DB_ADDR_LOW_1)
Touch Sequencer GuC Doorbell Address High for the 1st RXDMA (THC_M_PRT_GUC_DB_ADDR_HI_1)
Touch Sequencer GuC Doorbell Data (THC_M_PRT_GUC_DB_DATA_1)
Touch Sequencer GuC Tail Offset Initial Value for the 1st RXDMA (THC_M_PRT_GUC_OFFSET_INITVAL_1)
THC Device Address for the bulk/touch data read for the 1st RXDMA (THC_M_PRT_RD_BULK_ADDR_1)
THC Gfx/SW Doorbell Count from the 1st Stream RXDMA on this port (THC_M_PRT_DB_CNT_1)
THC Frame Count from the 1st Stream RXDMA on this port (THC_M_PRT_FRM_CNT_1)
THC Micro Frame Count from the 1st Stream RXDMA on this port (THC_M_PRT_UFRM_CNT_1)
THC Packet Count from the 1st Stream RXDMA on this port (THC_M_PRT_RXDMA_PKT_CNT_1)
THC Software Interrupt Count from the 1st Stream RXDMA on this port (THC_M_PRT_SWINT_CNT_1)
Touch Sequencer Frame Drop Counter for the 1st RXDMA (THC_M_PRT_FRAME_DROP_CNT_1)
THC Coaescing 1 (THC_M_PRT_COALESCE_1)
THC Read PRD Base Address Low for the 2nd RXDMA (THC_M_PRT_RPRD_BA_LOW_2)
THC Read PRD Base Address High for the 2nd RXDMA (THC_M_PRT_RPRD_BA_HI_2)
THC Read PRD Control for the 2nd RXDMA (THC_M_PRT_RPRD_CNTRL_2)
THC Read DMA Control for the 2nd RXDMA (THC_M_PRT_READ_DMA_CNTRL_2)
THC Read Interrupt Status for the 2nd RXDMA (THC_M_PRT_READ_DMA_INT_STS_2)
THC Read DMA Error Register for the 2nd RXDMA (THC_M_PRT_READ_DMA_ERR_2)
Touch Sequencer GuC Tail Offset Address Low for the 2nd RXDMA (THC_M_PRT_GUC_OFFSET_LOW_2)
Touch Sequencer GuC Tail Offset Address High for the 2nd RXDMA (THC_M_PRT_GUC_OFFSET_HI_2)
Touch Host Controller GuC Work Queue Item Size for the 2nd RXDMA (THC_M_PRT_GUC_WORKQ_ITEM_SZ_2)
Touch Host Controller GuC Control register for the 2nd RXDMA (THC_M_PRT_GUC_WORKQ_SZ_2)
Touch Sequencer Control for the 2nd DMA (THC_M_PRT_TSEQ_CNTRL_2)
Touch Sequencer GuC Doorbell Address Low for the 2nd RXDMA (THC_M_PRT_GUC_DB_ADDR_LOW_2)
Touch Sequencer GuC Doorbell Address High for the 2nd RXDMA (THC_M_PRT_GUC_DB_ADDR_HI_2)
Touch Sequencer GuC Doorbell Data for PRD2 (THC_M_PRT_GUC_DB_DATA_2)
Touch Sequencer GuC Tail Offset Initial Value for the 2nd RXDMA (THC_M_PRT_GUC_OFFSET_INITVAL_2)
THC Device Address for the bulk/touch data read for the 2nd RXDMA (THC_M_PRT_RD_BULK_ADDR_2)
THC Gfx/SW Doorbell Count from the 2nd Stream RXDMA on this port (THC_M_PRT_DB_CNT_2)
THC Frame Count from the 2nd Stream RXDMA on this port (THC_M_PRT_FRM_CNT_2)
THC Micro Frame Count from the 2nd Stream RXDMA on this port (THC_M_PRT_UFRM_CNT_2)
THC Packet Count from the 2nd Stream RXDMA on this port (THC_M_PRT_RXDMA_PKT_CNT_2)
THC Software Interrupt Count from the 2nd Stream RXDMA on this port (THC_M_PRT_SWINT_CNT_2)
Touch Sequencer Frame Drop Counter for the 2nd RXDMA (THC_M_PRT_FRAME_DROP_CNT_2)
Touch Host Controller (THC) PCI Configuration (D16:F0/1)
Touch Host Controller (THC) PCI Configuration (D16:F0/1) Device ID and Vendor ID (THC_CFG_DID_VID) Status and Command (THC_CFG_STS_CMD) Revision ID and Class Code (THC_CFG_CC_RID) BIST_Header Type_Latency Timer_Cache Line Size (THC_CFG_BIST_HTYPE_LT_CLS) THC BAR0 MMIO Low (THC_CFG_BAR0_LOW) THC BAR0 MMIO High (THC_CFG_BAR0_HI) Subsystem and Vendor ID (THC_CFG_SID_SVID) Capability List Pointer (THC_CFG_CAPP) Interrupt Configuration (THC_CFG_INT) THC Unsupported Request Status (THC_CFG_UR_STS_CTL) MSI Message Control_ Next Pointer and Capability ID (THC_CFG_MSIMC_MSINP_MSICID) MSI Message Address (THC_CFG_MSIMA) MSI Message Upper Address (THC_CFG_MSIMUA) MSI Message Data (THC_CFG_MSIMD) PCI Power Management Capability (THC_CFG_PMCAP_PMNP_PMCID) PCI Power Management Control and Status (THC_CFG_PMD_PMCSRBSE_PMCSR) Device Idle Capability (THC_CFG_DEVIDLE) Vendor Specific Header (THC_CFG_VSHDR) SW LTR Pointer Regsiter (THC_CFG_SWLTRPTR) Device Idle Pointer Register (THC_CFG_DEVIDLEPTR) Device Idle Power On Latency (THC_CFG_DEVIDLEPOL) Power Control Enables (THC_CFG_PCE)
Device ID and Vendor ID (THC_CFG_DID_VID)
Status and Command (THC_CFG_STS_CMD)
Revision ID and Class Code (THC_CFG_CC_RID)
BIST_Header Type_Latency Timer_Cache Line Size (THC_CFG_BIST_HTYPE_LT_CLS)
THC BAR0 MMIO Low (THC_CFG_BAR0_LOW)
THC BAR0 MMIO High (THC_CFG_BAR0_HI)
Subsystem and Vendor ID (THC_CFG_SID_SVID)
Capability List Pointer (THC_CFG_CAPP)
Interrupt Configuration (THC_CFG_INT)
THC Unsupported Request Status (THC_CFG_UR_STS_CTL)
MSI Message Control_ Next Pointer and Capability ID (THC_CFG_MSIMC_MSINP_MSICID)
MSI Message Address (THC_CFG_MSIMA)
MSI Message Upper Address (THC_CFG_MSIMUA)
MSI Message Data (THC_CFG_MSIMD)
PCI Power Management Capability (THC_CFG_PMCAP_PMNP_PMCID)
PCI Power Management Control and Status (THC_CFG_PMD_PMCSRBSE_PMCSR)
Device Idle Capability (THC_CFG_DEVIDLE)
Vendor Specific Header (THC_CFG_VSHDR)
SW LTR Pointer Regsiter (THC_CFG_SWLTRPTR)
Device Idle Pointer Register (THC_CFG_DEVIDLEPTR)
Device Idle Power On Latency (THC_CFG_DEVIDLEPOL)
Power Control Enables (THC_CFG_PCE)
TPM Configuration
TPM Configuration TPM IF Version Number Register (VER_FTIF1)
TPM IF Version Number Register (VER_FTIF1)
Type-C Subsystem xHCI PCI Configuration (D13:F0)
Type-C Subsystem xHCI PCI Configuration (D13:F0) Vendor ID (VID) Device ID (DID) Command Reg (CMD) Device Status (STS) Revision ID (RID) Programming Interface (PI) Sub Class Code (SCC) Base Class Code (BCC) Cache Line Size (CLS) Master Latency Timer (MLT) Header Type (HT) Memory Base Address (MBAR) USB Subsystem Vendor ID (SSVID) USB Subsystem ID (SSID) Capabilities Pointer (CAP_PTR) Interrupt Line (ILINE) Interrupt Pin (IPIN) Audio Time Synchronization (AUDSYNC) Serial Bus Release Number (SBRN) Frame Length Adjustment (FLADJ) Best Effort Service Latency (BESL) PCI Power Management Capability ID (PM_CID) Next Item Pointer 1 (PM_NEXT) Power Management Capabilities (PM_CAP) Power Management Control/Status (PM_CS) Message Signaled Interrupt CID (MSI_CID) Next Item Pointer (MSI_NEXT) Message Signaled Interrupt Message Control (MSI_MCTL) Message Signaled Interrupt Message Address (MSI_MAD) Message Signaled Interrupt Upper Address (MSI_MUAD) Message Signaled Interrupt Message Data (MSI_MD) High Speed Configuration 2 (HSCFG2)
Vendor ID (VID)
Device ID (DID)
Command Reg (CMD)
Device Status (STS)
Revision ID (RID)
Programming Interface (PI)
Sub Class Code (SCC)
Base Class Code (BCC)
Cache Line Size (CLS)
Master Latency Timer (MLT)
Header Type (HT)
Memory Base Address (MBAR)
USB Subsystem Vendor ID (SSVID)
USB Subsystem ID (SSID)
Capabilities Pointer (CAP_PTR)
Interrupt Line (ILINE)
Interrupt Pin (IPIN)
Audio Time Synchronization (AUDSYNC)
Serial Bus Release Number (SBRN)
Frame Length Adjustment (FLADJ)
Best Effort Service Latency (BESL)
PCI Power Management Capability ID (PM_CID)
Next Item Pointer 1 (PM_NEXT)
Power Management Capabilities (PM_CAP)
Power Management Control/Status (PM_CS)
Message Signaled Interrupt CID (MSI_CID)
Next Item Pointer (MSI_NEXT)
Message Signaled Interrupt Message Control (MSI_MCTL)
Message Signaled Interrupt Message Address (MSI_MAD)
Message Signaled Interrupt Upper Address (MSI_MUAD)
Message Signaled Interrupt Message Data (MSI_MD)
High Speed Configuration 2 (HSCFG2)
UART Additional MMIO
UART Additional MMIO REG CLOCKS (CLOCKS) REG RESETS (RESETS) REG GENERAL (GENERAL) REG ACTIVELTR_VALUE (ACTIVELTR_VALUE) REG IDLELTR_VALUE (IDLELTR_VALUE) REG TX_BYTE_COUNT (TX_BYTE_COUNT) REG RX_BYTE_COUNT (RX_BYTE_COUNT) REG Spare_0 (Spare_0) REG Spare_1 (Spare_1) REG SW_SCRATCH_0 (SW_SCRATCH_0) REG SW_SCRATCH_1 (SW_SCRATCH_1) REG SW_SCRATCH_2 (SW_SCRATCH_2) REG SW_SCRATCH_3 (SW_SCRATCH_3) REG CLOCK_GATE (CLOCK_GATE) REG Spare_2 (Spare_2) REG REMAP_ADDR_LO (REMAP_ADDR_LO) REG REMAP_ADDR_HI (REMAP_ADDR_HI) REG Spare_3 (Spare_3) REG DEVIDLE_CONTROL (DEVIDLE_CONTROL) REG CTS_Override (CTS_Override) REG UART_HVM_MISR_CRCOUT (UART_HVM_MISR_CRCOUT) REG CAPABLITIES (CAPABLITIES)
REG CLOCKS (CLOCKS)
REG RESETS (RESETS)
REG GENERAL (GENERAL)
REG ACTIVELTR_VALUE (ACTIVELTR_VALUE)
REG IDLELTR_VALUE (IDLELTR_VALUE)
REG TX_BYTE_COUNT (TX_BYTE_COUNT)
REG RX_BYTE_COUNT (RX_BYTE_COUNT)
REG Spare_0 (Spare_0)
REG Spare_1 (Spare_1)
REG SW_SCRATCH_0 (SW_SCRATCH_0)
REG SW_SCRATCH_1 (SW_SCRATCH_1)
REG SW_SCRATCH_2 (SW_SCRATCH_2)
REG SW_SCRATCH_3 (SW_SCRATCH_3)
REG CLOCK_GATE (CLOCK_GATE)
REG Spare_2 (Spare_2)
REG REMAP_ADDR_LO (REMAP_ADDR_LO)
REG REMAP_ADDR_HI (REMAP_ADDR_HI)
REG Spare_3 (Spare_3)
REG DEVIDLE_CONTROL (DEVIDLE_CONTROL)
REG CTS_Override (CTS_Override)
REG UART_HVM_MISR_CRCOUT (UART_HVM_MISR_CRCOUT)
REG CAPABLITIES (CAPABLITIES)
UART MMIO
UART MMIO REG DLL (DLL) REG RBR (RBR) REG THR (THR) REG DLH (DLH) REG IER (IER) REG FCR (FCR) REG IIR (IIR) REG LCR (LCR) REG MCR (MCR) REG LSR (LSR) REG MSR (MSR) REG SCR (SCR) REG SRBR_STHR0 (SRBR_STHR0) REG SRBR_STHR1 (SRBR_STHR1) REG SRBR_STHR2 (SRBR_STHR2) REG SRBR_STHR3 (SRBR_STHR3) REG SRBR_STHR4 (SRBR_STHR4) REG SRBR_STHR5 (SRBR_STHR5) REG SRBR_STHR6 (SRBR_STHR6) REG SRBR_STHR7 (SRBR_STHR7) REG SRBR_STHR8 (SRBR_STHR8) REG SRBR_STHR9 (SRBR_STHR9) REG SRBR_STHR10 (SRBR_STHR10) REG SRBR_STHR11 (SRBR_STHR11) REG SRBR_STHR12 (SRBR_STHR12) REG SRBR_STHR13 (SRBR_STHR13) REG SRBR_STHR14 (SRBR_STHR14) REG SRBR_STHR15 (SRBR_STHR15) REG FAR (FAR) REG TFR (TFR) REG RFW (RFW) REG USR (USR) REG TFL (TFL) REG RFL (RFL) REG SRR (SRR) REG SRTS (SRTS) REG SBCR (SBCR) REG SDMAM (SDMAM) REG SFE (SFE) REG SRT (SRT) REG STET (STET) REG HTX (HTX) REG DMASA (DMASA) REG CPR (CPR) REG UCV (UCV) REG CTR (CTR)
REG DLL (DLL)
REG RBR (RBR)
REG THR (THR)
REG DLH (DLH)
REG IER (IER)
REG FCR (FCR)
REG IIR (IIR)
REG LCR (LCR)
REG MCR (MCR)
REG LSR (LSR)
REG MSR (MSR)
REG SCR (SCR)
REG SRBR_STHR0 (SRBR_STHR0)
REG SRBR_STHR1 (SRBR_STHR1)
REG SRBR_STHR2 (SRBR_STHR2)
REG SRBR_STHR3 (SRBR_STHR3)
REG SRBR_STHR4 (SRBR_STHR4)
REG SRBR_STHR5 (SRBR_STHR5)
REG SRBR_STHR6 (SRBR_STHR6)
REG SRBR_STHR7 (SRBR_STHR7)
REG SRBR_STHR8 (SRBR_STHR8)
REG SRBR_STHR9 (SRBR_STHR9)
REG SRBR_STHR10 (SRBR_STHR10)
REG SRBR_STHR11 (SRBR_STHR11)
REG SRBR_STHR12 (SRBR_STHR12)
REG SRBR_STHR13 (SRBR_STHR13)
REG SRBR_STHR14 (SRBR_STHR14)
REG SRBR_STHR15 (SRBR_STHR15)
REG FAR (FAR)
REG TFR (TFR)
REG RFW (RFW)
REG USR (USR)
REG TFL (TFL)
REG RFL (RFL)
REG SRR (SRR)
REG SRTS (SRTS)
REG SBCR (SBCR)
REG SDMAM (SDMAM)
REG SFE (SFE)
REG SRT (SRT)
REG STET (STET)
REG HTX (HTX)
REG DMASA (DMASA)
REG CPR (CPR)
REG UCV (UCV)
REG CTR (CTR)
UART PCI Configuration (D30:F0/1, D25:F2)
UART PCI Configuration (D30:F0/1, D25:F2) Device Id And Vendor Id Register (DEVVENDID) Status And Command (STATUSCOMMAND) Revision Id And Class Code (REVCLASSCODE) Cache Line Latency Header And Bist (CLLATHEADERBIST) Base Address Register (BAR) Base Address Register High (BAR_HIGH) Base Address Register1 (BAR1) Base Address Register1 High (BAR1_HIGH) Subsystem Vendor And Subsystem Id (SUBSYSTEMID) Expansion Rom Base Address (EXPANSION_ROM_BASEADDR) Capabilities Pointer (CAPABILITYPTR) Interrupt Register (INTERRUPTREG) Power Management Capability Id (POWERCAPID) Power Management Control And Status Register (PMECTRLSTATUS) Pci Device Idle Vendor Capability Register (PCIDEVIDLE_CAP_RECORD) Vendor Specific Extended Capability Register (DEVID_VEND_SPECIFIC_REG) Software Ltr Update Mmio Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG) Device Idle Pointer Register (DEVICE_IDLE_POINTER_REG) D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG) General Purpose Read Write Register1 (GEN_PCI_REGRW1) General Purpose Read Write Register2 (GEN_PCI_REGRW2) General Purpose Read Write Register3 (GEN_PCI_REGRW3) General Purpose Read Write Register4 (GEN_PCI_REGRW4) General Purpose Input Register (GEN_INPUT_REG)
Device Id And Vendor Id Register (DEVVENDID)
Status And Command (STATUSCOMMAND)
Revision Id And Class Code (REVCLASSCODE)
Cache Line Latency Header And Bist (CLLATHEADERBIST)
Base Address Register (BAR)
Base Address Register High (BAR_HIGH)
Base Address Register1 (BAR1)
Base Address Register1 High (BAR1_HIGH)
Subsystem Vendor And Subsystem Id (SUBSYSTEMID)
Expansion Rom Base Address (EXPANSION_ROM_BASEADDR)
Capabilities Pointer (CAPABILITYPTR)
Interrupt Register (INTERRUPTREG)
Power Management Capability Id (POWERCAPID)
Power Management Control And Status Register (PMECTRLSTATUS)
Pci Device Idle Vendor Capability Register (PCIDEVIDLE_CAP_RECORD)
Vendor Specific Extended Capability Register (DEVID_VEND_SPECIFIC_REG)
Software Ltr Update Mmio Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device Idle Pointer Register (DEVICE_IDLE_POINTER_REG)
D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG)
General Purpose Read Write Register1 (GEN_PCI_REGRW1)
General Purpose Read Write Register2 (GEN_PCI_REGRW2)
General Purpose Read Write Register3 (GEN_PCI_REGRW3)
General Purpose Read Write Register4 (GEN_PCI_REGRW4)
General Purpose Input Register (GEN_INPUT_REG)
USB Type-C Subsystem PCIe Root Port PCI Configuration (D7:F0/1/2/3)
USB Type-C Subsystem PCIe Root Port PCI Configuration (D7:F0/1/2/3) Identifiers (ID) Device Command (CMD) Primary Status (PSTS) Revision ID (RID_CC) Cache Line Size (CLS) Primary Latency Timer (PLT) Header Type (HTYPE) Bus Numbers (BNUM_SLT) I/O Base And Limit (IOBL) Secondary Status (SSTS) Memory Base And Limit (MBL) Prefetchable Memory Base And Limit (PMBL) Prefetchable Memory Base Upper 32 Bits (PMBU32) Prefetchable Memory Limit Upper 32 Bits (PMLU32) Capabilities List Pointer (CAPP) Interrupt Information (INTR) Bridge Control (BCTRL) Capabilities List (CLIST) PCI Express Capabilities (XCAP) Device Capabilities (DCAP) Device Control (DCTL) Device Status (DSTS) Link Capabilities (LCAP) Link Control (LCTL) Link Status (LSTS) Slot Capabilities (SLCAP) Slot Control (SLCTL) Slot Status (SLSTS) Root Control (RCTL) Root Status (RSTS) Device Capabilities 2 (DCAP2) Device Control 2 (DCTL2) Device Status 2 (DSTS2) Link Capabilities 2 (LCAP2) Link Control 2 (LCTL2) Link Status 2 (LSTS2) Slot Capabilities 2 (SLCAP2) Slot Control 2 (SLCTL2) Slot Status 2 (SLSTS2) Message Signaled Interrupt Identifiers (MID) Message Signaled Interrupt Message (MC) Message Signaled Interrupt Message Address (MA) Message Signaled Interrupt Message Data (MD) Subsystem Vendor Capability (SVCAP) Subsystem Vendor IDs (SVID) Power Management Capability (PMCAP) PCI Power Management Capabilities (PMC) PCI Power Management Control (PMCS) FPB Capability Header (FPBCAP) FPB Capabilities Register (FPBCAPR) FPB RID Vector Control 1 (FPBRIDVC1) FPB RID Vector Control 2 (FPBRIDVC2) FPB MEM Low Vector Control (FPBMEMLVC) FPB MEM High Vector Control 1 (FPBMEMHVC1) FPB MEM High Vector Control 2 (FPBMEMHVC2) FPB Vector Access Control (FPBVAC) FPB Vector Access Data (FPBVD) Advanced Error Extended (AECH) Uncorrectable Error Status (UES) Uncorrectable Error Mask (UEM) Uncorrectable Error Severity (UEV) Correctable Error Status (CES) Correctable Error Mask (CEM) Advanced Error Capabilities And Control (AECC) Header Log (HL_DW1) Header Log (HL_DW2) Header Log (HL_DW3) Header Log (HL_DW4) Root Error Command (REC) Root Error Status (RES) Error Source Identification (ESID) PTM Extended Capability Header (PTMECH) PTM Capability Register (PTMCAPR) PTM Control Register (PTMCTLR) L1 Sub-States Extended Capability Header (L1SECH) L1 Sub-States Capabilities (L1SCAP) L1 Sub-States Control 1 (L1SCTL1) L1 Sub-States Control 2 (L1SCTL2) ACS Extended Capability Header (ACSECH) ACS Capability Register (ACSCAPR) ACS Control Register (ACSCTLR) Port VC Capability Register 1 (PVCCR1) Port VC Capability 2 (PVCC2) Port VC Control (PVCC) Port VC Status (PVCS) Virtual Channel 0 Resource Capability (V0VCRC) Virtual Channel 0 Resource Control (V0CTL) Virtual Channel 0 Resource Status (V0STS) Virtual Channel 1 Resource Capability (V1VCRC) Virtual Channel 1 Resource Control (V1CTL) Virtual Channel 1 Resource Status (V1STS) DPC Extended Capability Header (DPCECH) DPC Capability Register (DPCCAPR) DPC Control Register (DPCCTLR) DPC Status Register (DPCSR) DPC Error Source ID Register (DPCESIDR) RP PIO Status Register (RPPIOSR) RP PIO Mask Register (RPPIOMR) RP PIO Severity Register (RPPIOVR) RP PIO SysError Register (RPPIOSER) RP PIO Exception Register (RPPIOER) RP PIO Header Log DW1 Register (RPPIOHLR_DW1) RP PIO Header Log DW2 Register (RPPIOHLR_DW2) RP PIO Header Log DW3 Register (RPPIOHLR_DW3) RP PIO Header Log DW4 Register (RPPIOHLR_DW4) Secondary PCI Express Extended Capability Header (SPEECH) Link Control 3 (LCTL3) Lane Error Status (LES) Lane 0 And Lane 1 Equalization Control (L01EC) Lane 2 And Lane 3 Equalization Control (L23EC) Lane 4 And Lane 5 Equalization Control (L45EC) Lane 6 And Lane 7 Equalization Control (L67EC) Lane 8 And Lane 9 Equalization Control (L89EC) Lane 10 And Lane 11 Equalization Control (L1011EC) Lane 12 And Lane 13 Equalization Control (L1213EC) Lane 14 And Lane 15 Equalization Control (L1415EC) Data Link Feature Extended Capability Header (DLFECH) Data Link Feature Capabilities Register (DLFCAP) Data Link Feature Status Register (DLFSTS)
Identifiers (ID)
Device Command (CMD)
Primary Status (PSTS)
Revision ID (RID_CC)
Cache Line Size (CLS)
Primary Latency Timer (PLT)
Header Type (HTYPE)
Bus Numbers (BNUM_SLT)
I/O Base And Limit (IOBL)
Secondary Status (SSTS)
Memory Base And Limit (MBL)
Prefetchable Memory Base And Limit (PMBL)
Prefetchable Memory Base Upper 32 Bits (PMBU32)
Prefetchable Memory Limit Upper 32 Bits (PMLU32)
Capabilities List Pointer (CAPP)
Interrupt Information (INTR)
Bridge Control (BCTRL)
Capabilities List (CLIST)
PCI Express Capabilities (XCAP)
Device Capabilities (DCAP)
Device Control (DCTL)
Device Status (DSTS)
Link Capabilities (LCAP)
Link Control (LCTL)
Link Status (LSTS)
Slot Capabilities (SLCAP)
Slot Control (SLCTL)
Slot Status (SLSTS)
Root Control (RCTL)
Root Status (RSTS)
Device Capabilities 2 (DCAP2)
Device Control 2 (DCTL2)
Device Status 2 (DSTS2)
Link Capabilities 2 (LCAP2)
Link Control 2 (LCTL2)
Link Status 2 (LSTS2)
Slot Capabilities 2 (SLCAP2)
Slot Control 2 (SLCTL2)
Slot Status 2 (SLSTS2)
Message Signaled Interrupt Identifiers (MID)
Message Signaled Interrupt Message (MC)
Message Signaled Interrupt Message Address (MA)
Message Signaled Interrupt Message Data (MD)
Subsystem Vendor Capability (SVCAP)
Subsystem Vendor IDs (SVID)
Power Management Capability (PMCAP)
PCI Power Management Capabilities (PMC)
PCI Power Management Control (PMCS)
FPB Capability Header (FPBCAP)
FPB Capabilities Register (FPBCAPR)
FPB RID Vector Control 1 (FPBRIDVC1)
FPB RID Vector Control 2 (FPBRIDVC2)
FPB MEM Low Vector Control (FPBMEMLVC)
FPB MEM High Vector Control 1 (FPBMEMHVC1)
FPB MEM High Vector Control 2 (FPBMEMHVC2)
FPB Vector Access Control (FPBVAC)
FPB Vector Access Data (FPBVD)
Advanced Error Extended (AECH)
Uncorrectable Error Status (UES)
Uncorrectable Error Mask (UEM)
Uncorrectable Error Severity (UEV)
Correctable Error Status (CES)
Correctable Error Mask (CEM)
Advanced Error Capabilities And Control (AECC)
Header Log (HL_DW1)
Header Log (HL_DW2)
Header Log (HL_DW3)
Header Log (HL_DW4)
Root Error Command (REC)
Root Error Status (RES)
Error Source Identification (ESID)
PTM Extended Capability Header (PTMECH)
PTM Capability Register (PTMCAPR)
PTM Control Register (PTMCTLR)
L1 Sub-States Extended Capability Header (L1SECH)
L1 Sub-States Capabilities (L1SCAP)
L1 Sub-States Control 1 (L1SCTL1)
L1 Sub-States Control 2 (L1SCTL2)
ACS Extended Capability Header (ACSECH)
ACS Capability Register (ACSCAPR)
ACS Control Register (ACSCTLR)
Port VC Capability Register 1 (PVCCR1)
Port VC Capability 2 (PVCC2)
Port VC Control (PVCC)
Port VC Status (PVCS)
Virtual Channel 0 Resource Capability (V0VCRC)
Virtual Channel 0 Resource Control (V0CTL)
Virtual Channel 0 Resource Status (V0STS)
Virtual Channel 1 Resource Capability (V1VCRC)
Virtual Channel 1 Resource Control (V1CTL)
Virtual Channel 1 Resource Status (V1STS)
DPC Extended Capability Header (DPCECH)
DPC Capability Register (DPCCAPR)
DPC Control Register (DPCCTLR)
DPC Status Register (DPCSR)
DPC Error Source ID Register (DPCESIDR)
RP PIO Status Register (RPPIOSR)
RP PIO Mask Register (RPPIOMR)
RP PIO Severity Register (RPPIOVR)
RP PIO SysError Register (RPPIOSER)
RP PIO Exception Register (RPPIOER)
RP PIO Header Log DW1 Register (RPPIOHLR_DW1)
RP PIO Header Log DW2 Register (RPPIOHLR_DW2)
RP PIO Header Log DW3 Register (RPPIOHLR_DW3)
RP PIO Header Log DW4 Register (RPPIOHLR_DW4)
Secondary PCI Express Extended Capability Header (SPEECH)
Link Control 3 (LCTL3)
Lane Error Status (LES)
Lane 0 And Lane 1 Equalization Control (L01EC)
Lane 2 And Lane 3 Equalization Control (L23EC)
Lane 4 And Lane 5 Equalization Control (L45EC)
Lane 6 And Lane 7 Equalization Control (L67EC)
Lane 8 And Lane 9 Equalization Control (L89EC)
Lane 10 And Lane 11 Equalization Control (L1011EC)
Lane 12 And Lane 13 Equalization Control (L1213EC)
Lane 14 And Lane 15 Equalization Control (L1415EC)
Data Link Feature Extended Capability Header (DLFECH)
Data Link Feature Capabilities Register (DLFCAP)
Data Link Feature Status Register (DLFSTS)
xDCI (USB Device Control) MMIO Device
xDCI (USB Device Control) MMIO Device Device Configuration Register (DCFG) Device Control Register (DCTL) Device Event Enable Register (DEVTEN) Device Status Register (DSTS) Device Generic Command Parameter (DGCMDPAR) Device Generic Command Register (DGCMD) Device Active USB Endpoint Enable (DALEPENA) Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2_0) Device Physical Endpoint-n Command Parameter 1 (DEPCMDPAR1_0) Device Physical Endpoint-n Command Parameter 0 (DEPCMDPAR0_0) Device Physical Endpoint-n Command (DEPCMD_0)
Device Configuration Register (DCFG)
Device Control Register (DCTL)
Device Event Enable Register (DEVTEN)
Device Status Register (DSTS)
Device Generic Command Parameter (DGCMDPAR)
Device Generic Command Register (DGCMD)
Device Active USB Endpoint Enable (DALEPENA)
Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2_0)
Device Physical Endpoint-n Command Parameter 1 (DEPCMDPAR1_0)
Device Physical Endpoint-n Command Parameter 0 (DEPCMDPAR0_0)
Device Physical Endpoint-n Command (DEPCMD_0)
xDCI (USB Device Control) MMIO Global
xDCI (USB Device Control) MMIO Global GSBUSCFG0 (GSBUSCFG0) GSBUSCFG1 (GSBUSCFG1) GTXTHRCFG (GTXTHRCFG) GRXTHRCFG (GRXTHRCFG) GCTL (GCTL) GSTS (GSTS) GBUSERRADDRLO (GBUSERRADDRLO) GBUSERRADDRHI (GBUSERRADDRHI)
GSBUSCFG0 (GSBUSCFG0)
GSBUSCFG1 (GSBUSCFG1)
GTXTHRCFG (GTXTHRCFG)
GRXTHRCFG (GRXTHRCFG)
GCTL (GCTL)
GSTS (GSTS)
GBUSERRADDRLO (GBUSERRADDRLO)
GBUSERRADDRHI (GBUSERRADDRHI)
xDCI (USB Device Control) PCI Configuration (D20:F1)
xDCI (USB Device Control) PCI Configuration (D20:F1) Device Id And Vendor Id Register (DEVVENDID) Status And Command (STATUSCOMMAND) Revision Id And Class Code (REVCLASSCODE) Cache Line Latency Header And Bist (CLLATHEADERBIST) Base Address Register (BAR) Base Address Register High (BAR_HIGH) Base Address Register1 (BAR1) Base Address Register1 High (BAR1_HIGH) Subsystem Vendor And Subsystem Id (SUBSYSTEMID) Expansion Rom Base Address (EXPANSION_ROM_BASEADDR) Capabilities Pointer Register (CAPABILITYPTR) Interrupt Register (INTERRUPTREG) Power Management Capability Id (POWERCAPID) Power Management Control And Status Register (PMECTRLSTATUS) Pci Device Idle Vendor Capability Register (PCIDEVIDLE_CAP_RECORD) Vendor Specific Extended Capability Register (DEVID_VEND_SPECIFIC_REG) Software Ltr Update Mmio Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG) Device Idle Pointer Register (DEVICE_IDLE_POINTER_REG) D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG)
Device Id And Vendor Id Register (DEVVENDID)
Status And Command (STATUSCOMMAND)
Revision Id And Class Code (REVCLASSCODE)
Cache Line Latency Header And Bist (CLLATHEADERBIST)
Base Address Register (BAR)
Base Address Register High (BAR_HIGH)
Base Address Register1 (BAR1)
Base Address Register1 High (BAR1_HIGH)
Subsystem Vendor And Subsystem Id (SUBSYSTEMID)
Expansion Rom Base Address (EXPANSION_ROM_BASEADDR)
Capabilities Pointer Register (CAPABILITYPTR)
Interrupt Register (INTERRUPTREG)
Power Management Capability Id (POWERCAPID)
Power Management Control And Status Register (PMECTRLSTATUS)
Pci Device Idle Vendor Capability Register (PCIDEVIDLE_CAP_RECORD)
Vendor Specific Extended Capability Register (DEVID_VEND_SPECIFIC_REG)
Software Ltr Update Mmio Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device Idle Pointer Register (DEVICE_IDLE_POINTER_REG)
D0i3 And Power Control Enable Register (D0I3_MAX_POW_LAT_PG_CONFIG)
xHCI MMIO
xHCI MMIO Capability Registers Length (CAPLENGTH) Host Controller Interface Version Number (HCIVERSION) Structural Parameters 1 (HCSPARAMS1) Structural Parameters 2 (HCSPARAMS2) Structural Parameters 3 (HCSPARAMS3) Capability Parameters (HCCPARAMS) Doorbell Offset (DBOFF) Runtime Register Space Offset (RTSOFF) USB Command (USBCMD) USB Status (USBSTS) Page Size (PAGESIZE) Device Notification Control (DNCTRL) Command Ring Low (CRCR_LO) Command Ring High (CRCR_HI) Device Context Base Address Array Pointer Low (DCBAAP_LO) Device Context Base Address Array Pointer High (DCBAAP_HI) Configure Reg (CONFIG) Port Status AndControl USB2 (PORTSC1) Port Power Management Status Aand Control USB2 (PORTPMSC1) Port X Hardware LPM Control Register (PORTHLPMC1) Port Status And Control USB3 (PORTSC11) Port Power Management Status And Control USB3 (PORTPMSC11) USB3 Port Link Info (PORTLI11) Microframe Index (RTMFINDEX) Interrupter Management (IMAN0) Interrupter Moderation (IMOD0) Event Ring Segment Table Size (ERSTSZ0) Event Ring Segment Table Base Address Low (ERSTBA_LO0) Event Ring Segment Table Base Address High (ERSTBA_HI0) Event Ring Dequeue Pointer Low (ERDP_LO0) Event Ring Dequeue Pointer High (ERDP_HI0) Door Bell (DB0) XECP SUPP USB2_1 (XECP_SUPP_USB2_1) XECP SUPP USB3_3 (XECP_SUPP_USB2_3) XECP SUPP USB2_4 Full Speed (XECP_SUPP_USB2_4) XECP_SUPP USB2_5 Low Speed (XECP_SUPP_USB2_5) XECP SUPP USB2_6 High Speed (XECP_SUPP_USB2_6) XECP SUPP USB3_0 (XECP_SUPP_USB3_0) XECP SUPP USB3_1 (XECP_SUPP_USB3_1) XECP SUPP USB3_2 (XECP_SUPP_USB3_2) XECP SUPP USB3_3 (XECP_SUPP_USB3_3) XECP SUPP USB3_4 (XECP_SUPP_USB3_4) XECP SUPP USB3_5 (XECP_SUPP_USB3_5) XECP SUPP USB3_6 (XECP_SUPP_USB3_6) XECP SUPP USB3_7 (XECP_SUPP_USB3_7) Host Control Scheduler (HOST_CTRL_SCH_REG) Power Management Control (PMCTRL_REG) Host Controller Misc Reg (HOST_CTRL_MISC_REG) Super Speed Port Enable (SSPE_REG) AUX Power Management Control (AUX_CTRL_REG1) SuperSpeed Port Link Control (HOST_CTRL_PORT_LINK_REG) USB2 Port Link Control 1 (USB2_LINK_MGR_CTRL_REG1) USB2 Port Link Control 2 (USB2_LINK_MGR_CTRL_REG2) USB2 Port Link Control 3 (USB2_LINK_MGR_CTRL_REG3) USB2 Port Link Control 4 (USB2_LINK_MGR_CTRL_REG4) Power Scheduler Control-0 (PWR_SCHED_CTRL0) Power Scheduler Control-1 (PWR_SCHED_CTRL2) AUX Power Management Control (AUX_CTRL_REG2) XHCI Aux Clock Control Register (XHCI_AUX_CCR) XHC Latency Tolerance Parameters LTV Control (XLTP_LTV1) XHC Latency Tolerance Parameters High Idle Time Control (XLTP_HITC) XHC Latency Tolerance Parameters Medium Idle Time Control (XLTP_MITC) XHC Latency Tolerance Parameters Low Idle Time Control (XLTP_LITC) LFPS On Count (LFPSONCOUNT_REG) USB2 Power Management Control (USB2PMCTRL_REG) USB Legacy Support Capability (USBLEGSUP) Port Disable Override Capability Register (PDO_CAPABILITY) Debug Capability ID Register (DCID) GLOBAL TIME SYNC CAP REG (GLOBAL_TIME_SYNC_CAP_REG) GLOBAL TIME SYNC CTRL REG (GLOBAL_TIME_SYNC_CTRL_REG) MICROFRAME TIME REG (MICROFRAME_TIME_REG) Global Time Value (Low Register) (GLOBAL_TIME_LOW_REG) Global Time High (GLOBAL_TIME_HI_REG) XHCI USB2 Overcurrent Pin Mapping (U2OCM1) XHCI USB2 Overcurrent Pin Mapping (U2OCM2) XHCI USB2 Overcurrent Pin Mapping (U2OCM3) XHCI USB2 Overcurrent Pin Mapping (U2OCM4) XHCI USB2 Overcurrent Pin Mapping (U2OCM5) XHCI USB2 Overcurrent Pin Mapping (U2OCM6) XHCI USB2 Overcurrent Pin Mapping (U2OCM7) XHCI USB2 Overcurrent Pin Mapping (U2OCM8) XHCI USB3 Overcurrent Pin Mapping (U3OCM1) XHCI USB3 Overcurrent Pin Mapping (U3OCM2) XHCI USB3 Overcurrent Pin Mapping (U3OCM3) XHCI USB3 Overcurrent Pin Mapping (U3OCM4) XHCI USB3 Overcurrent Pin Mapping (U3OCM5) XHCI USB3 Overcurrent Pin Mapping (U3OCM6) XHCI USB3 Overcurrent Pin Mapping (U3OCM7) XHCI USB3 Overcurrent Pin Mapping (U3OCM8)
Capability Registers Length (CAPLENGTH)
Host Controller Interface Version Number (HCIVERSION)
Structural Parameters 1 (HCSPARAMS1)
Structural Parameters 2 (HCSPARAMS2)
Structural Parameters 3 (HCSPARAMS3)
Capability Parameters (HCCPARAMS)
Doorbell Offset (DBOFF)
Runtime Register Space Offset (RTSOFF)
USB Command (USBCMD)
USB Status (USBSTS)
Page Size (PAGESIZE)
Device Notification Control (DNCTRL)
Command Ring Low (CRCR_LO)
Command Ring High (CRCR_HI)
Device Context Base Address Array Pointer Low (DCBAAP_LO)
Device Context Base Address Array Pointer High (DCBAAP_HI)
Configure Reg (CONFIG)
Port Status AndControl USB2 (PORTSC1)
Port Power Management Status Aand Control USB2 (PORTPMSC1)
Port X Hardware LPM Control Register (PORTHLPMC1)
Port Status And Control USB3 (PORTSC11)
Port Power Management Status And Control USB3 (PORTPMSC11)
USB3 Port Link Info (PORTLI11)
Microframe Index (RTMFINDEX)
Interrupter Management (IMAN0)
Interrupter Moderation (IMOD0)
Event Ring Segment Table Size (ERSTSZ0)
Event Ring Segment Table Base Address Low (ERSTBA_LO0)
Event Ring Segment Table Base Address High (ERSTBA_HI0)
Event Ring Dequeue Pointer Low (ERDP_LO0)
Event Ring Dequeue Pointer High (ERDP_HI0)
Door Bell (DB0)
XECP SUPP USB2_1 (XECP_SUPP_USB2_1)
XECP SUPP USB3_3 (XECP_SUPP_USB2_3)
XECP SUPP USB2_4 Full Speed (XECP_SUPP_USB2_4)
XECP_SUPP USB2_5 Low Speed (XECP_SUPP_USB2_5)
XECP SUPP USB2_6 High Speed (XECP_SUPP_USB2_6)
XECP SUPP USB3_0 (XECP_SUPP_USB3_0)
XECP SUPP USB3_1 (XECP_SUPP_USB3_1)
XECP SUPP USB3_2 (XECP_SUPP_USB3_2)
XECP SUPP USB3_3 (XECP_SUPP_USB3_3)
XECP SUPP USB3_4 (XECP_SUPP_USB3_4)
XECP SUPP USB3_5 (XECP_SUPP_USB3_5)
XECP SUPP USB3_6 (XECP_SUPP_USB3_6)
XECP SUPP USB3_7 (XECP_SUPP_USB3_7)
Host Control Scheduler (HOST_CTRL_SCH_REG)
Power Management Control (PMCTRL_REG)
Host Controller Misc Reg (HOST_CTRL_MISC_REG)
Super Speed Port Enable (SSPE_REG)
AUX Power Management Control (AUX_CTRL_REG1)
SuperSpeed Port Link Control (HOST_CTRL_PORT_LINK_REG)
USB2 Port Link Control 1 (USB2_LINK_MGR_CTRL_REG1)
USB2 Port Link Control 2 (USB2_LINK_MGR_CTRL_REG2)
USB2 Port Link Control 3 (USB2_LINK_MGR_CTRL_REG3)
USB2 Port Link Control 4 (USB2_LINK_MGR_CTRL_REG4)
Power Scheduler Control-0 (PWR_SCHED_CTRL0)
Power Scheduler Control-1 (PWR_SCHED_CTRL2)
AUX Power Management Control (AUX_CTRL_REG2)
XHCI Aux Clock Control Register (XHCI_AUX_CCR)
XHC Latency Tolerance Parameters LTV Control (XLTP_LTV1)
XHC Latency Tolerance Parameters High Idle Time Control (XLTP_HITC)
XHC Latency Tolerance Parameters Medium Idle Time Control (XLTP_MITC)
XHC Latency Tolerance Parameters Low Idle Time Control (XLTP_LITC)
LFPS On Count (LFPSONCOUNT_REG)
USB2 Power Management Control (USB2PMCTRL_REG)
USB Legacy Support Capability (USBLEGSUP)
Port Disable Override Capability Register (PDO_CAPABILITY)
Debug Capability ID Register (DCID)
GLOBAL TIME SYNC CAP REG (GLOBAL_TIME_SYNC_CAP_REG)
GLOBAL TIME SYNC CTRL REG (GLOBAL_TIME_SYNC_CTRL_REG)
MICROFRAME TIME REG (MICROFRAME_TIME_REG)
Global Time Value (Low Register) (GLOBAL_TIME_LOW_REG)
Global Time High (GLOBAL_TIME_HI_REG)
XHCI USB2 Overcurrent Pin Mapping (U2OCM1)
XHCI USB2 Overcurrent Pin Mapping (U2OCM2)
XHCI USB2 Overcurrent Pin Mapping (U2OCM3)
XHCI USB2 Overcurrent Pin Mapping (U2OCM4)
XHCI USB2 Overcurrent Pin Mapping (U2OCM5)
XHCI USB2 Overcurrent Pin Mapping (U2OCM6)
XHCI USB2 Overcurrent Pin Mapping (U2OCM7)
XHCI USB2 Overcurrent Pin Mapping (U2OCM8)
XHCI USB3 Overcurrent Pin Mapping (U3OCM1)
XHCI USB3 Overcurrent Pin Mapping (U3OCM2)
XHCI USB3 Overcurrent Pin Mapping (U3OCM3)
XHCI USB3 Overcurrent Pin Mapping (U3OCM4)
XHCI USB3 Overcurrent Pin Mapping (U3OCM5)
XHCI USB3 Overcurrent Pin Mapping (U3OCM6)
XHCI USB3 Overcurrent Pin Mapping (U3OCM7)
XHCI USB3 Overcurrent Pin Mapping (U3OCM8)
xHCI PCI Configuration (D20:F0)
xHCI PCI Configuration (D20:F0) Vendor ID (VID) Device ID (DID) Command Reg (CMD) Device Status (STS) Revision ID (RID) Programming Interface (PI) Sub Class Code (SCC) Base Class Code (BCC) Cache Line Size (CLS) Master Latency Timer (MLT) Header Type (HT) Memory Base Address (MBAR) USB Subsystem Vendor ID (SSVID) USB Subsystem ID (SSID) Capabilities Pointer (CAP_PTR) Interrupt Line (ILINE) Interrupt Pin (IPIN) XHC System Bus Configuration 1 (XHCC1) XHC System Bus Configuration 2 (XHCC2) Clock Gating (XHCLKGTEN) Audio Time Synchronization (AUDSYNC) Serial Bus Release Number (SBRN) Frame Length Adjustment (FLADJ) Best Effort Service Latency (BESL) PCI Power Management Capability ID (PM_CID) Next Item Pointer 1 (PM_NEXT) Power Management Capabilities (PM_CAP) Power Management Control/Status (PM_CS) Message Signaled Interrupt CID (MSI_CID) Next Item Pointer (MSI_NEXT) Message Signaled Interrupt Message Control (MSI_MCTL) Message Signaled Interrupt Message Address (MSI_MAD) Message Signaled Interrupt Upper Address (MSI_MUAD) Message Signaled Interrupt Message Data (MSI_MD) High Speed Configuration 2 (HSCFG2)
Vendor ID (VID)
Device ID (DID)
Command Reg (CMD)
Device Status (STS)
Revision ID (RID)
Programming Interface (PI)
Sub Class Code (SCC)
Base Class Code (BCC)
Cache Line Size (CLS)
Master Latency Timer (MLT)
Header Type (HT)
Memory Base Address (MBAR)
USB Subsystem Vendor ID (SSVID)
USB Subsystem ID (SSID)
Capabilities Pointer (CAP_PTR)
Interrupt Line (ILINE)
Interrupt Pin (IPIN)
XHC System Bus Configuration 1 (XHCC1)
XHC System Bus Configuration 2 (XHCC2)
Clock Gating (XHCLKGTEN)
Audio Time Synchronization (AUDSYNC)
Serial Bus Release Number (SBRN)
Frame Length Adjustment (FLADJ)
Best Effort Service Latency (BESL)
PCI Power Management Capability ID (PM_CID)
Next Item Pointer 1 (PM_NEXT)
Power Management Capabilities (PM_CAP)
Power Management Control/Status (PM_CS)
Message Signaled Interrupt CID (MSI_CID)
Next Item Pointer (MSI_NEXT)
Message Signaled Interrupt Message Control (MSI_MCTL)
Message Signaled Interrupt Message Address (MSI_MAD)
Message Signaled Interrupt Upper Address (MSI_MUAD)
Message Signaled Interrupt Message Data (MSI_MD)
High Speed Configuration 2 (HSCFG2)

Audio Memory Mapped I/O Registers

Summary of Bus: (), Device: (), Function: (), Type: (MEM)

Offset

Size (Bytes)

Register Name (Register Symbol)

Scope

Default Value

0h

2

Global Capabilities (GCAP)

Package

9B01h

2h

1

Minor Version (VMIN)

Package

00h

3h

1

Major Version (VMAJ)

Package

01h

4h

2

Output Payload Capability (OUTPAY)

Package

003Ch

6h

2

Input Payload Capability (INPAY)

Package

001Dh

8h

4

Global Control (GCTL)

Package

00000000h

ch

2

Wake Enable (WAKEEN)

Package

0000h

eh

2

Wake Status (WAKESTS)

Package

0000h

10h

2

Global Status (GSTS)

Package

0000h

12h

2

Global Capabilities 2 (GCAP2)

Package

0004h

14h

2

Linked List Capabilities Header (LLCH)

Package

0C00h

18h

2

Output Stream Payload Capability (OUTSTRMPAY)

Package

0030h

1ah

2

Input Stream Payload Capability (INSTRMPAY)

Package

0018h

20h

4

Interrupt Control (INTCTL)

Package

00000000h

24h

4

Interrupt Status (INTSTS)

Package

00000000h

30h

4

Wall Clock Counter (WALCLK)

Package

00000000h

38h

4

Stream Synchronization (SSYNC)

Package

00000000h

40h

4

CORB Lower Base Address (CORBLBASE)

Package

00000000h

44h

4

CORB Upper Base Address (CORBUBASE)

Package

00000000h

48h

2

CORB Write Pointer (CORBWP)

Package

0000h

4ah

2

CORB Read Pointer (CORBRP)

Package

0000h

4ch

1

CORB Control (CORBCTL)

Package

00h

4dh

1

CORB Status (CORBSTS)

Package

00h

4eh

1

CORB Size (CORBSIZE)

Package

42h

50h

4

RIRB Lower Base Address (RIRBLBASE)

Package

00000000h

54h

4

RIRB Upper Base Address (RIRBUBASE)

Package

00000000h

58h

2

RIRB Write Pointer (RIRBWP)

Package

0000h

5ah

2

Response Interrupt Count (RINTCNT)

Package

0000h

5ch

1

RIRB Control (RIRBCTL)

Package

00h

5dh

1

RIRB Status (RIRBSTS)

Package

00h

5eh

1

RIRB Size (RIRBSIZE)

Package

42h

60h

4

Immediate Command (IC)

Package

00000000h

64h

4

Immediate Response (IR)

Package

00000000h

68h

2

Immediate Command Status (ICS)

Package

0000h

70h

4

DMA Position Lower Base Address (DPLBASE)

Package

00000000h

74h

4

DMA Position Upper Base Address (DPUBASE)

Package

00000000h

80h

1

Input Stream Descriptor x Control (ISD0CTL_​B0)

Package

00h

82h

1

Input Stream Descriptor x Control (ISD0CTL_​B2)

Package

04h

83h

1

Input Stream Descriptor x Status (ISD0STS)

Package

00h

84h

4

Input Stream Descriptor x Link Position in Buffer (ISD0LPIB)

Package

00000000h

88h

4

Input Stream Descriptor x Cyclic Buffer Length (ISD0CBL)

Package

00000000h

8ch

2

Input Stream Descriptor x Last Valid Index (ISD0LVI)

Package

0000h

8eh

2

Input Stream Descriptor x FIFO Eviction Watermark (ISD0FIFOW)

Package

0004h

90h

2

Input Stream Descriptor x FIFO Size (ISD0FIFOS)

Package

0000h

92h

2

Input Stream Descriptor x Format (ISD0FMT)

Package

0000h

98h

4

Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD0BDLPLBA)

Package

00000000h

9ch

4

Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD0BDLPUBA)

Package

00000000h

a0h

1

Input Stream Descriptor x Control (ISD1CTL_​B0)

Package

00h

a2h

1

Input Stream Descriptor x Control (ISD1CTL_​B2)

Package

04h

a3h

1

Input Stream Descriptor x Status (ISD1STS)

Package

00h

a4h

4

Input Stream Descriptor x Link Position in Buffer (ISD1LPIB)

Package

00000000h

a8h

4

Input Stream Descriptor x Cyclic Buffer Length (ISD1CBL)

Package

00000000h

ach

2

Input Stream Descriptor x Last Valid Index (ISD1LVI)

Package

0000h

aeh

2

Input Stream Descriptor x FIFO Eviction Watermark (ISD1FIFOW)

Package

0004h

b0h

2

Input Stream Descriptor x FIFO Size (ISD1FIFOS)

Package

0000h

b2h

2

Input Stream Descriptor x Format (ISD1FMT)

Package

0000h

b8h

4

Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD1BDLPLBA)

Package

00000000h

bch

4

Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD1BDLPUBA)

Package

00000000h

c0h

1

Input Stream Descriptor x Control (ISD2CTL_​B0)

Package

00h

c2h

1

Input Stream Descriptor x Control (ISD2CTL_​B2)

Package

04h

c3h

1

Input Stream Descriptor x Status (ISD2STS)

Package

00h

c4h

4

Input Stream Descriptor x Link Position in Buffer (ISD2LPIB)

Package

00000000h

c8h

4

Input Stream Descriptor x Cyclic Buffer Length (ISD2CBL)

Package

00000000h

cch

2

Input Stream Descriptor x Last Valid Index (ISD2LVI)

Package

0000h

ceh

2

Input Stream Descriptor x FIFO Eviction Watermark (ISD2FIFOW)

Package

0004h

d0h

2

Input Stream Descriptor x FIFO Size (ISD2FIFOS)

Package

0000h

d2h

2

Input Stream Descriptor x Format (ISD2FMT)

Package

0000h

d8h

4

Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD2BDLPLBA)

Package

00000000h

dch

4

Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD2BDLPUBA)

Package

00000000h

e0h

1

Input Stream Descriptor x Control (ISD3CTL_​B0)

Package

00h

e2h

1

Input Stream Descriptor x Control (ISD3CTL_​B2)

Package

04h

e3h

1

Input Stream Descriptor x Status (ISD3STS)

Package

00h

e4h

4

Input Stream Descriptor x Link Position in Buffer (ISD3LPIB)

Package

00000000h

e8h

4

Input Stream Descriptor x Cyclic Buffer Length (ISD3CBL)

Package

00000000h

ech

2

Input Stream Descriptor x Last Valid Index (ISD3LVI)

Package

0000h

eeh

2

Input Stream Descriptor x FIFO Eviction Watermark (ISD3FIFOW)

Package

0004h

f0h

2

Input Stream Descriptor x FIFO Size (ISD3FIFOS)

Package

0000h

f2h

2

Input Stream Descriptor x Format (ISD3FMT)

Package

0000h

f8h

4

Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD3BDLPLBA)

Package

00000000h

fch

4

Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD3BDLPUBA)

Package

00000000h

100h

1

Input Stream Descriptor x Control (ISD4CTL_​B0)

Package

00h

102h

1

Input Stream Descriptor x Control (ISD4CTL_​B2)

Package

04h

103h

1

Input Stream Descriptor x Status (ISD4STS)

Package

00h

104h

4

Input Stream Descriptor x Link Position in Buffer (ISD4LPIB)

Package

00000000h

108h

4

Input Stream Descriptor x Cyclic Buffer Length (ISD4CBL)

Package

00000000h

10ch

2

Input Stream Descriptor x Last Valid Index (ISD4LVI)

Package

0000h

10eh

2

Input Stream Descriptor x FIFO Eviction Watermark (ISD4FIFOW)

Package

0004h

110h

2

Input Stream Descriptor x FIFO Size (ISD4FIFOS)

Package

0000h

112h

2

Input Stream Descriptor x Format (ISD4FMT)

Package

0000h

118h

4

Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD4BDLPLBA)

Package

00000000h

11ch

4

Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD4BDLPUBA)

Package

00000000h

120h

1

Input Stream Descriptor x Control (ISD5CTL_​B0)

Package

00h

122h

1

Input Stream Descriptor x Control (ISD5CTL_​B2)

Package

04h

123h

1

Input Stream Descriptor x Status (ISD5STS)

Package

00h

124h

4

Input Stream Descriptor x Link Position in Buffer (ISD5LPIB)

Package

00000000h

128h

4

Input Stream Descriptor x Cyclic Buffer Length (ISD5CBL)

Package

00000000h

12ch

2

Input Stream Descriptor x Last Valid Index (ISD5LVI)

Package

0000h

12eh

2

Input Stream Descriptor x FIFO Eviction Watermark (ISD5FIFOW)

Package

0004h

130h

2

Input Stream Descriptor x FIFO Size (ISD5FIFOS)

Package

0000h

132h

2

Input Stream Descriptor x Format (ISD5FMT)

Package

0000h

138h

4

Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD5BDLPLBA)

Package

00000000h

13ch

4

Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD5BDLPUBA)

Package

00000000h

140h

1

Input Stream Descriptor x Control (ISD6CTL_​B0)

Package

00h

142h

1

Input Stream Descriptor x Control (ISD6CTL_​B2)

Package

04h

143h

1

Input Stream Descriptor x Status (ISD6STS)

Package

00h

144h

4

Input Stream Descriptor x Link Position in Buffer (ISD6LPIB)

Package

00000000h

148h

4

Input Stream Descriptor x Cyclic Buffer Length (ISD6CBL)

Package

00000000h

14ch

2

Input Stream Descriptor x Last Valid Index (ISD6LVI)

Package

0000h

14eh

2

Input Stream Descriptor x FIFO Eviction Watermark (ISD6FIFOW)

Package

0004h

150h

2

Input Stream Descriptor x FIFO Size (ISD6FIFOS)

Package

0000h

152h

2

Input Stream Descriptor x Format (ISD6FMT)

Package

0000h

158h

4

Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD6BDLPLBA)

Package

00000000h

15ch

4

Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD6BDLPUBA)

Package

00000000h

160h

1

Input Stream Descriptor x Control (ISD7CTL_​B0)

Package

00h

162h

1

Input Stream Descriptor x Control (ISD7CTL_​B2)

Package

04h

163h

1

Input Stream Descriptor x Status (ISD7STS)

Package

00h

164h

4

Input Stream Descriptor x Link Position in Buffer (ISD7LPIB)

Package

00000000h

168h

4

Input Stream Descriptor x Cyclic Buffer Length (ISD7CBL)

Package

00000000h

16ch

2

Input Stream Descriptor x Last Valid Index (ISD7LVI)

Package

0000h

16eh

2

Input Stream Descriptor x FIFO Eviction Watermark (ISD7FIFOW)

Package

0004h

170h

2

Input Stream Descriptor x FIFO Size (ISD7FIFOS)

Package

0000h

172h

2

Input Stream Descriptor x Format (ISD7FMT)

Package

0000h

178h

4

Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD7BDLPLBA)

Package

00000000h

17ch

4

Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD7BDLPUBA)

Package

00000000h

180h

1

Input Stream Descriptor x Control (ISD8CTL_​B0)

Package

00h

182h

1

Input Stream Descriptor x Control (ISD8CTL_​B2)

Package

04h

183h

1

Input Stream Descriptor x Status (ISD8STS)

Package

00h

184h

4

Input Stream Descriptor x Link Position in Buffer (ISD8LPIB)

Package

00000000h

188h

4

Input Stream Descriptor x Cyclic Buffer Length (ISD8CBL)

Package

00000000h

18ch

2

Input Stream Descriptor x Last Valid Index (ISD8LVI)

Package

0000h

18eh

2

Input Stream Descriptor x FIFO Eviction Watermark (ISD8FIFOW)

Package

0004h

190h

2

Input Stream Descriptor x FIFO Size (ISD8FIFOS)

Package

0000h

192h

2

Input Stream Descriptor x Format (ISD8FMT)

Package

0000h

198h

4

Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD8BDLPLBA)

Package

00000000h

19ch

4

Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD8BDLPUBA)

Package

00000000h

1a0h

1

Input Stream Descriptor x Control (ISD9CTL_​B0)

Package

00h

1a2h

1

Input Stream Descriptor x Control (ISD9CTL_​B2)

Package

04h

1a3h

1

Input Stream Descriptor x Status (ISD9STS)

Package

00h

1a4h

4

Input Stream Descriptor x Link Position in Buffer (ISD9LPIB)

Package

00000000h

1a8h

4

Input Stream Descriptor x Cyclic Buffer Length (ISD9CBL)

Package

00000000h

1ach

2

Input Stream Descriptor x Last Valid Index (ISD9LVI)

Package

0000h

1aeh

2

Input Stream Descriptor x FIFO Eviction Watermark (ISD9FIFOW)

Package

0004h

1b0h

2

Input Stream Descriptor x FIFO Size (ISD9FIFOS)

Package

0000h

1b2h

2

Input Stream Descriptor x Format (ISD9FMT)

Package

0000h

1b8h

4

Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD9BDLPLBA)

Package

00000000h

1bch

4

Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD9BDLPUBA)

Package

00000000h

1c0h

1

Input Stream Descriptor x Control (ISD10CTL_​B0)

Package

00h

1c2h

1

Input Stream Descriptor x Control (ISD10CTL_​B2)

Package

04h

1c3h

1

Input Stream Descriptor x Status (ISD10STS)

Package

00h

1c4h

4

Input Stream Descriptor x Link Position in Buffer (ISD10LPIB)

Package

00000000h

1c8h

4

Input Stream Descriptor x Cyclic Buffer Length (ISD10CBL)

Package

00000000h

1cch

2

Input Stream Descriptor x Last Valid Index (ISD10LVI)

Package

0000h

1ceh

2

Input Stream Descriptor x FIFO Eviction Watermark (ISD10FIFOW)

Package

0004h

1d0h

2

Input Stream Descriptor x FIFO Size (ISD10FIFOS)

Package

0000h

1d2h

2

Input Stream Descriptor x Format (ISD10FMT)

Package

0000h

1d8h

4

Input Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (ISD10BDLPLBA)

Package

00000000h

1dch

4

Input Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (ISD10BDLPUBA)

Package

00000000h

1e0h

1

Output Stream Descriptor x Control (OSD0CTL_​B0)

Package

00h

1e2h

1

Output Stream Descriptor x Control (OSD0CTL_​B2)

Package

04h

1e3h

1

Output Stream Descriptor x Status (OSD0STS)

Package

00h

1e4h

4

Output Stream Descriptor x Link Position in Buffer (OSD0LPIB)

Package

00000000h

1e8h

4

Output Stream Descriptor x Cyclic Buffer Length (OSD0CBL)

Package

00000000h

1ech

2

Output Stream Descriptor x Last Valid Index (OSD0LVI)

Package

0000h

1eeh

2

Output Stream Descriptor x FIFO Eviction Watermark (OSD0FIFOW)

Package

0004h

1f0h

2

Output Stream Descriptor x FIFO Size (OSD0FIFOS)

Package

0000h

1f2h

2

Output Stream Descriptor x Format (OSD0FMT)

Package

0000h

1f8h

4

Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD0BDLPLBA)

Package

00000000h

1fch

4

Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD0BDLPUBA)

Package

00000000h

200h

1

Output Stream Descriptor x Control (OSD1CTL_​B0)

Package

00h

202h

1

Output Stream Descriptor x Control (OSD1CTL_​B2)

Package

04h

203h

1

Output Stream Descriptor x Status (OSD1STS)

Package

00h

204h

4

Output Stream Descriptor x Link Position in Buffer (OSD1LPIB)

Package

00000000h

208h

4

Output Stream Descriptor x Cyclic Buffer Length (OSD1CBL)

Package

00000000h

20ch

2

Output Stream Descriptor x Last Valid Index (OSD1LVI)

Package

0000h

20eh

2

Output Stream Descriptor x FIFO Eviction Watermark (OSD1FIFOW)

Package

0004h

210h

2

Output Stream Descriptor x FIFO Size (OSD1FIFOS)

Package

0000h

212h

2

Output Stream Descriptor x Format (OSD1FMT)

Package

0000h

218h

4

Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD1BDLPLBA)

Package

00000000h

21ch

4

Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD1BDLPUBA)

Package

00000000h

220h

1

Output Stream Descriptor x Control (OSD2CTL_​B0)

Package

00h

222h

1

Output Stream Descriptor x Control (OSD2CTL_​B2)

Package

04h

223h

1

Output Stream Descriptor x Status (OSD2STS)

Package

00h

224h

4

Output Stream Descriptor x Link Position in Buffer (OSD2LPIB)

Package

00000000h

228h

4

Output Stream Descriptor x Cyclic Buffer Length (OSD2CBL)

Package

00000000h

22ch

2

Output Stream Descriptor x Last Valid Index (OSD2LVI)

Package

0000h

22eh

2

Output Stream Descriptor x FIFO Eviction Watermark (OSD2FIFOW)

Package

0004h

230h

2

Output Stream Descriptor x FIFO Size (OSD2FIFOS)

Package

0000h

232h

2

Output Stream Descriptor x Format (OSD2FMT)

Package

0000h

238h

4

Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD2BDLPLBA)

Package

00000000h

23ch

4

Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD2BDLPUBA)

Package

00000000h

240h

1

Output Stream Descriptor x Control (OSD3CTL_​B0)

Package

00h

242h

1

Output Stream Descriptor x Control (OSD3CTL_​B2)

Package

04h

243h

1

Output Stream Descriptor x Status (OSD3STS)

Package

00h

244h

4

Output Stream Descriptor x Link Position in Buffer (OSD3LPIB)

Package

00000000h

248h

4

Output Stream Descriptor x Cyclic Buffer Length (OSD3CBL)

Package

00000000h

24ch

2

Output Stream Descriptor x Last Valid Index (OSD3LVI)

Package

0000h

24eh

2

Output Stream Descriptor x FIFO Eviction Watermark (OSD3FIFOW)

Package

0004h

250h

2

Output Stream Descriptor x FIFO Size (OSD3FIFOS)

Package

0000h

252h

2

Output Stream Descriptor x Format (OSD3FMT)

Package

0000h

258h

4

Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD3BDLPLBA)

Package

00000000h

25ch

4

Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD3BDLPUBA)

Package

00000000h

260h

1

Output Stream Descriptor x Control (OSD4CTL_​B0)

Package

00h

262h

1

Output Stream Descriptor x Control (OSD4CTL_​B2)

Package

04h

263h

1

Output Stream Descriptor x Status (OSD4STS)

Package

00h

264h

4

Output Stream Descriptor x Link Position in Buffer (OSD4LPIB)

Package

00000000h

268h

4

Output Stream Descriptor x Cyclic Buffer Length (OSD4CBL)

Package

00000000h

26ch

2

Output Stream Descriptor x Last Valid Index (OSD4LVI)

Package

0000h

26eh

2

Output Stream Descriptor x FIFO Eviction Watermark (OSD4FIFOW)

Package

0004h

270h

2

Output Stream Descriptor x FIFO Size (OSD4FIFOS)

Package

0000h

272h

2

Output Stream Descriptor x Format (OSD4FMT)

Package

0000h

278h

4

Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD4BDLPLBA)

Package

00000000h

27ch

4

Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD4BDLPUBA)

Package

00000000h

280h

1

Output Stream Descriptor x Control (OSD5CTL_​B0)

Package

00h

282h

1

Output Stream Descriptor x Control (OSD5CTL_​B2)

Package

04h

283h

1

Output Stream Descriptor x Status (OSD5STS)

Package

00h

284h

4

Output Stream Descriptor x Link Position in Buffer (OSD5LPIB)

Package

00000000h

288h

4

Output Stream Descriptor x Cyclic Buffer Length (OSD5CBL)

Package

00000000h

28ch

2

Output Stream Descriptor x Last Valid Index (OSD5LVI)

Package

0000h

28eh

2

Output Stream Descriptor x FIFO Eviction Watermark (OSD5FIFOW)

Package

0004h

290h

2

Output Stream Descriptor x FIFO Size (OSD5FIFOS)

Package

0000h

292h

2

Output Stream Descriptor x Format (OSD5FMT)

Package

0000h

298h

4

Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD5BDLPLBA)

Package

00000000h

29ch

4

Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD5BDLPUBA)

Package

00000000h

2a0h

1

Output Stream Descriptor x Control (OSD6CTL_​B0)

Package

00h

2a2h

1

Output Stream Descriptor x Control (OSD6CTL_​B2)

Package

04h

2a3h

1

Output Stream Descriptor x Status (OSD6STS)

Package

00h

2a4h

4

Output Stream Descriptor x Link Position in Buffer (OSD6LPIB)

Package

00000000h

2a8h

4

Output Stream Descriptor x Cyclic Buffer Length (OSD6CBL)

Package

00000000h

2ach

2

Output Stream Descriptor x Last Valid Index (OSD6LVI)

Package

0000h

2aeh

2

Output Stream Descriptor x FIFO Eviction Watermark (OSD6FIFOW)

Package

0004h

2b0h

2

Output Stream Descriptor x FIFO Size (OSD6FIFOS)

Package

0000h

2b2h

2

Output Stream Descriptor x Format (OSD6FMT)

Package

0000h

2b8h

4

Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD6BDLPLBA)

Package

00000000h

2bch

4

Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD6BDLPUBA)

Package

00000000h

2c0h

1

Output Stream Descriptor x Control (OSD7CTL_​B0)

Package

00h

2c2h

1

Output Stream Descriptor x Control (OSD7CTL_​B2)

Package

04h

2c3h

1

Output Stream Descriptor x Status (OSD7STS)

Package

00h

2c4h

4

Output Stream Descriptor x Link Position in Buffer (OSD7LPIB)

Package

00000000h

2c8h

4

Output Stream Descriptor x Cyclic Buffer Length (OSD7CBL)

Package

00000000h

2cch

2

Output Stream Descriptor x Last Valid Index (OSD7LVI)

Package

0000h

2ceh

2

Output Stream Descriptor x FIFO Eviction Watermark (OSD7FIFOW)

Package

0004h

2d0h

2

Output Stream Descriptor x FIFO Size (OSD7FIFOS)

Package

0000h

2d2h

2

Output Stream Descriptor x Format (OSD7FMT)

Package

0000h

2d8h

4

Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD7BDLPLBA)

Package

00000000h

2dch

4

Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD7BDLPUBA)

Package

00000000h

2e0h

1

Output Stream Descriptor x Control (OSD8CTL_​B0)

Package

00h

2e2h

1

Output Stream Descriptor x Control (OSD8CTL_​B2)

Package

04h

2e3h

1

Output Stream Descriptor x Status (OSD8STS)

Package

00h

2e4h

4

Output Stream Descriptor x Link Position in Buffer (OSD8LPIB)

Package

00000000h

2e8h

4

Output Stream Descriptor x Cyclic Buffer Length (OSD8CBL)

Package

00000000h

2ech

2

Output Stream Descriptor x Last Valid Index (OSD8LVI)

Package

0000h

2eeh

2

Output Stream Descriptor x FIFO Eviction Watermark (OSD8FIFOW)

Package

0004h

2f0h

2

Output Stream Descriptor x FIFO Size (OSD8FIFOS)

Package

0000h

2f2h

2

Output Stream Descriptor x Format (OSD8FMT)

Package

0000h

2f8h

4

Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address (OSD8BDLPLBA)

Package

00000000h

2fch

4

Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base Address (OSD8BDLPUBA)

Package

00000000h

500h

4

DMA Resume Capability Header (DRSMCH)

Package

00050700h

504h

4

DMA Resume Control (DRSMCTL)

Package

00000000h

508h

4

Input Stream Descriptor x DMA Position in Buffer Resume (ISD0DPIBR)

Package

00000000h

510h

4

Input Stream Descriptor x DMA Position in Buffer Resume (ISD1DPIBR)

Package

00000000h

518h

4

Input Stream Descriptor x DMA Position in Buffer Resume (ISD2DPIBR)

Package

00000000h

520h

4

Input Stream Descriptor x DMA Position in Buffer Resume (ISD3DPIBR)

Package

00000000h

528h

4

Input Stream Descriptor x DMA Position in Buffer Resume (ISD4DPIBR)

Package

00000000h

530h

4

Input Stream Descriptor x DMA Position in Buffer Resume (ISD5DPIBR)

Package

00000000h

538h

4

Input Stream Descriptor x DMA Position in Buffer Resume (ISD6DPIBR)

Package

00000000h

540h

4

Input Stream Descriptor x DMA Position in Buffer Resume (ISD7DPIBR)

Package

00000000h

548h

4

Input Stream Descriptor x DMA Position in Buffer Resume (ISD8DPIBR)

Package

00000000h

550h

4

Input Stream Descriptor x DMA Position in Buffer Resume (ISD9DPIBR)

Package

00000000h

558h

4

Input Stream Descriptor x DMA Position in Buffer Resume (ISD10DPIBR)

Package

00000000h

560h

4

Output Stream Descriptor x DMA Position in Buffer Resume (OSD0DPIBR)

Package

00000000h

568h

4

Output Stream Descriptor x DMA Position in Buffer Resume (OSD1DPIBR)

Package

00000000h

570h

4

Output Stream Descriptor x DMA Position in Buffer Resume (OSD2DPIBR)

Package

00000000h

578h

4

Output Stream Descriptor x DMA Position in Buffer Resume (OSD3DPIBR)

Package

00000000h

580h

4

Output Stream Descriptor x DMA Position in Buffer Resume (OSD4DPIBR)

Package

00000000h

588h

4

Output Stream Descriptor x DMA Position in Buffer Resume (OSD5DPIBR)

Package

00000000h

590h

4

Output Stream Descriptor x DMA Position in Buffer Resume (OSD6DPIBR)

Package

00000000h

598h

4

Output Stream Descriptor x DMA Position in Buffer Resume (OSD7DPIBR)

Package

00000000h

5a0h

4

Output Stream Descriptor x DMA Position in Buffer Resume (OSD8DPIBR)

Package

00000000h

700h

4

Software Position Based FIFO Capability Header (SPBFCH)

Package

00040800h

704h

4

Software Position Based FIFO Control (SPBFCTL)

Package

00000000h

708h

4

Input Stream Descriptor x Software Position in Buffer (ISD0SPIB)

Package

00000000h

70ch

4

Input Stream Descriptor x Max FIFO Size (ISD0MAXFIFOS)

Package

00000000h

710h

4

Input Stream Descriptor x Software Position in Buffer (ISD1SPIB)

Package

00000000h

714h

4

Input Stream Descriptor x Max FIFO Size (ISD1MAXFIFOS)

Package

00000000h

718h

4

Input Stream Descriptor x Software Position in Buffer (ISD2SPIB)

Package

00000000h

71ch

4

Input Stream Descriptor x Max FIFO Size (ISD2MAXFIFOS)

Package

00000000h

720h

4

Input Stream Descriptor x Software Position in Buffer (ISD3SPIB)

Package

00000000h

724h

4

Input Stream Descriptor x Max FIFO Size (ISD3MAXFIFOS)

Package

00000000h

728h

4

Input Stream Descriptor x Software Position in Buffer (ISD4SPIB)

Package

00000000h

72ch

4

Input Stream Descriptor x Max FIFO Size (ISD4MAXFIFOS)

Package

00000000h

730h

4

Input Stream Descriptor x Software Position in Buffer (ISD5SPIB)

Package

00000000h

734h

4

Input Stream Descriptor x Max FIFO Size (ISD5MAXFIFOS)

Package

00000000h

738h

4

Input Stream Descriptor x Software Position in Buffer (ISD6SPIB)

Package

00000000h

73ch

4

Input Stream Descriptor x Max FIFO Size (ISD6MAXFIFOS)

Package

00000000h

740h

4

Input Stream Descriptor x Software Position in Buffer (ISD7SPIB)

Package

00000000h

744h

4

Input Stream Descriptor x Max FIFO Size (ISD7MAXFIFOS)

Package

00000000h

748h

4

Input Stream Descriptor x Software Position in Buffer (ISD8SPIB)

Package

00000000h

74ch

4

Input Stream Descriptor x Max FIFO Size (ISD8MAXFIFOS)

Package

00000000h

750h

4

Input Stream Descriptor x Software Position in Buffer (ISD9SPIB)

Package

00000000h

754h

4

Input Stream Descriptor x Max FIFO Size (ISD9MAXFIFOS)

Package

00000000h

758h

4

Input Stream Descriptor x Software Position in Buffer (ISD10SPIB)

Package

00000000h

75ch

4

Input Stream Descriptor x Max FIFO Size (ISD10MAXFIFOS)

Package

00000000h

760h

4

Output Stream Descriptor x Software Position in Buffer (OSD0SPIB)

Package

00000000h

764h

4

Output Stream Descriptor x Max FIFO Size (OSD0MAXFIFOS)

Package

00000000h

768h

4

Output Stream Descriptor x Software Position in Buffer (OSD1SPIB)

Package

00000000h

76ch

4

Output Stream Descriptor x Max FIFO Size (OSD1MAXFIFOS)

Package

00000000h

770h

4

Output Stream Descriptor x Software Position in Buffer (OSD2SPIB)

Package

00000000h

774h

4

Output Stream Descriptor x Max FIFO Size (OSD2MAXFIFOS)

Package

00000000h

778h

4

Output Stream Descriptor x Software Position in Buffer (OSD3SPIB)

Package

00000000h

77ch

4

Output Stream Descriptor x Max FIFO Size (OSD3MAXFIFOS)

Package

00000000h

780h

4

Output Stream Descriptor x Software Position in Buffer (OSD4SPIB)

Package

00000000h

784h

4

Output Stream Descriptor x Max FIFO Size (OSD4MAXFIFOS)

Package

00000000h

788h

4

Output Stream Descriptor x Software Position in Buffer (OSD5SPIB)

Package

00000000h

78ch

4

Output Stream Descriptor x Max FIFO Size (OSD5MAXFIFOS)

Package

00000000h

790h

4

Output Stream Descriptor x Software Position in Buffer (OSD6SPIB)

Package

00000000h

794h

4

Output Stream Descriptor x Max FIFO Size (OSD6MAXFIFOS)

Package

00000000h

798h

4

Output Stream Descriptor x Software Position in Buffer (OSD7SPIB)

Package

00000000h

79ch

4

Output Stream Descriptor x Max FIFO Size (OSD7MAXFIFOS)

Package

00000000h

7a0h

4

Output Stream Descriptor x Software Position in Buffer (OSD8SPIB)

Package

00000000h

7a4h

4

Output Stream Descriptor x Max FIFO Size (OSD8MAXFIFOS)

Package

00000000h

800h

4

Processing Pipe Capability Header (PPCH)

Package

00030000h

804h

4

Processing Pipe Control (PPCTL)

Package

00000000h

808h

4

Processing Pipe Status (PPSTS)

Package

00000000h

810h

4

Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC0LLPL)

Package

00000000h

814h

4

Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC0LLPU)

Package

00000000h

818h

4

Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC0LDPL)

Package

00000000h

81ch

4

Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC0LDPU)

Package

00000000h

820h

4

Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC1LLPL)

Package

00000000h

824h

4

Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC1LLPU)

Package

00000000h

828h

4

Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC1LDPL)

Package

00000000h

82ch

4

Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC1LDPU)

Package

00000000h

830h

4

Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC2LLPL)

Package

00000000h

834h

4

Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC2LLPU)

Package

00000000h

838h

4

Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC2LDPL)

Package

00000000h

83ch

4

Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC2LDPU)

Package

00000000h

840h

4

Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC3LLPL)

Package

00000000h

844h

4

Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC3LLPU)

Package

00000000h

848h

4

Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC3LDPL)

Package

00000000h

84ch

4

Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC3LDPU)

Package

00000000h

850h

4

Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC4LLPL)

Package

00000000h

854h

4

Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC4LLPU)

Package

00000000h

858h

4

Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC4LDPL)

Package

00000000h

85ch

4

Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC4LDPU)

Package

00000000h

860h

4

Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC5LLPL)

Package

00000000h

864h

4

Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC5LLPU)

Package

00000000h

868h

4

Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC5LDPL)

Package

00000000h

86ch

4

Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC5LDPU)

Package

00000000h

870h

4

Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC6LLPL)

Package

00000000h

874h

4

Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC6LLPU)

Package

00000000h

878h

4

Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC6LDPL)

Package

00000000h

87ch

4

Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC6LDPU)

Package

00000000h

880h

4

Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC7LLPL)

Package

00000000h

884h

4

Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC7LLPU)

Package

00000000h

888h

4

Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC7LDPL)

Package

00000000h

88ch

4

Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC7LDPU)

Package

00000000h

890h

4

Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC8LLPL)

Package

00000000h

894h

4

Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC8LLPU)

Package

00000000h

898h

4

Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC8LDPL)

Package

00000000h

89ch

4

Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC8LDPU)

Package

00000000h

8a0h

4

Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC9LLPL)

Package

00000000h

8a4h

4

Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC9LLPU)

Package

00000000h

8a8h

4

Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC9LDPL)

Package

00000000h

8ach

4

Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC9LDPU)

Package

00000000h

8b0h

4

Input Processing Pipe Host Connection x Linear Link Position Lower (IPPHC10LLPL)

Package

00000000h

8b4h

4

Input Processing Pipe Host Connection x Linear Link Position Upper (IPPHC10LLPU)

Package

00000000h

8b8h

4

Input Processing Pipe Host Connection x Linear DMA Position Lower (IPPHC10LDPL)

Package

00000000h

8bch

4

Input Processing Pipe Host Connection x Linear DMA Position Upper (IPPHC10LDPU)

Package

00000000h

8c0h

4

Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC0LLPL)

Package

00000000h

8c4h

4

Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC0LLPU)

Package

00000000h

8c8h

4

Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC0LDPL)

Package

00000000h

8cch

4

Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC0LDPU)

Package

00000000h

8d0h

4

Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC1LLPL)

Package

00000000h

8d4h

4

Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC1LLPU)

Package

00000000h

8d8h

4

Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC1LDPL)

Package

00000000h

8dch

4

Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC1LDPU)

Package

00000000h

8e0h

4

Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC2LLPL)

Package

00000000h

8e4h

4

Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC2LLPU)

Package

00000000h

8e8h

4

Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC2LDPL)

Package

00000000h

8ech

4

Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC2LDPU)

Package

00000000h

8f0h

4

Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC3LLPL)

Package

00000000h

8f4h

4

Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC3LLPU)

Package

00000000h

8f8h

4

Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC3LDPL)

Package

00000000h

8fch

4

Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC3LDPU)

Package

00000000h

900h

4

Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC4LLPL)

Package

00000000h

904h

4

Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC4LLPU)

Package

00000000h

908h

4

Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC4LDPL)

Package

00000000h

90ch

4

Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC4LDPU)

Package

00000000h

910h

4

Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC5LLPL)

Package

00000000h

914h

4

Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC5LLPU)

Package

00000000h

918h

4

Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC5LDPL)

Package

00000000h

91ch

4

Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC5LDPU)

Package

00000000h

920h

4

Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC6LLPL)

Package

00000000h

924h

4

Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC6LLPU)

Package

00000000h

928h

4

Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC6LDPL)

Package

00000000h

92ch

4

Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC6LDPU)

Package

00000000h

930h

4

Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC7LLPL)

Package

00000000h

934h

4

Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC7LLPU)

Package

00000000h

938h

4

Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC7LDPL)

Package

00000000h

93ch

4

Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC7LDPU)

Package

00000000h

940h

4

Output Processing Pipe Host Connection x Linear Link Position Lower (OPPHC8LLPL)

Package

00000000h

944h

4

Output Processing Pipe Host Connection x Linear Link Position Upper (OPPHC8LLPU)

Package

00000000h

948h

4

Output Processing Pipe Host Connection x Linear DMA Position Lower (OPPHC8LDPL)

Package

00000000h

94ch

4

Output Processing Pipe Host Connection x Linear DMA Position Upper (OPPHC8LDPU)

Package

00000000h

950h

4

Input Processing Pipe Link Connection x Control (IPPLC0CTL)

Package

00000000h

954h

2

Input Processing Pipe Link Connection x Format (IPPLC0FMT)

Package

0000h

958h

4

Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC0LLPL)

Package

00000000h

95ch

4

Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC0LLPU)

Package

00000000h

960h

4

Input Processing Pipe Link Connection x Control (IPPLC1CTL)

Package

00000000h

964h

2

Input Processing Pipe Link Connection x Format (IPPLC1FMT)

Package

0000h

968h

4

Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC1LLPL)

Package

00000000h

96ch

4

Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC1LLPU)

Package

00000000h

970h

4

Input Processing Pipe Link Connection x Control (IPPLC2CTL)

Package

00000000h

974h

2

Input Processing Pipe Link Connection x Format (IPPLC2FMT)

Package

0000h

978h

4

Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC2LLPL)

Package

00000000h

97ch

4

Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC2LLPU)

Package

00000000h

980h

4

Input Processing Pipe Link Connection x Control (IPPLC3CTL)

Package

00000000h

984h

2

Input Processing Pipe Link Connection x Format (IPPLC3FMT)

Package

0000h

988h

4

Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC3LLPL)

Package

00000000h

98ch

4

Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC3LLPU)

Package

00000000h

990h

4

Input Processing Pipe Link Connection x Control (IPPLC4CTL)

Package

00000000h

994h

2

Input Processing Pipe Link Connection x Format (IPPLC4FMT)

Package

0000h

998h

4

Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC4LLPL)

Package

00000000h

99ch

4

Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC4LLPU)

Package

00000000h

9a0h

4

Input Processing Pipe Link Connection x Control (IPPLC5CTL)

Package

00000000h

9a4h

2

Input Processing Pipe Link Connection x Format (IPPLC5FMT)

Package

0000h

9a8h

4

Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC5LLPL)

Package

00000000h

9ach

4

Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC5LLPU)

Package

00000000h

9b0h

4

Input Processing Pipe Link Connection x Control (IPPLC6CTL)

Package

00000000h

9b4h

2

Input Processing Pipe Link Connection x Format (IPPLC6FMT)

Package

0000h

9b8h

4

Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC6LLPL)

Package

00000000h

9bch

4

Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC6LLPU)

Package

00000000h

9c0h

4

Input Processing Pipe Link Connection x Control (IPPLC7CTL)

Package

00000000h

9c4h

2

Input Processing Pipe Link Connection x Format (IPPLC7FMT)

Package

0000h

9c8h

4

Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC7LLPL)

Package

00000000h

9cch

4

Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC7LLPU)

Package

00000000h

9d0h

4

Input Processing Pipe Link Connection x Control (IPPLC8CTL)

Package

00000000h

9d4h

2

Input Processing Pipe Link Connection x Format (IPPLC8FMT)

Package

0000h

9d8h

4

Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC8LLPL)

Package

00000000h

9dch

4

Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC8LLPU)

Package

00000000h

9e0h

4

Input Processing Pipe Link Connection x Control (IPPLC9CTL)

Package

00000000h

9e4h

2

Input Processing Pipe Link Connection x Format (IPPLC9FMT)

Package

0000h

9e8h

4

Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC9LLPL)

Package

00000000h

9ech

4

Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC9LLPU)

Package

00000000h

9f0h

4

Input Processing Pipe Link Connection x Control (IPPLC10CTL)

Package

00000000h

9f4h

2

Input Processing Pipe Link Connection x Format (IPPLC10FMT)

Package

0000h

9f8h

4

Input Processing Pipe Link Connection x Linear Link Position Lower (IPPLC10LLPL)

Package

00000000h

9fch

4

Input Processing Pipe Link Connection x Linear Link Position Upper (IPPLC10LLPU)

Package

00000000h

a00h

4

Output Processing Pipe Link Connection x Control (OPPLC0CTL)

Package

00000000h

a04h

2

Output Processing Pipe Link Connection x Format (OPPLC0FMT)

Package

0000h

a08h

4

Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC0LLPL)

Package

00000000h

a0ch

4

Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC0LLPU)

Package

00000000h

a10h

4

Output Processing Pipe Link Connection x Control (OPPLC1CTL)

Package

00000000h

a14h

2

Output Processing Pipe Link Connection x Format (OPPLC1FMT)

Package

0000h

a18h

4

Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC1LLPL)

Package

00000000h

a1ch

4

Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC1LLPU)

Package

00000000h

a20h

4

Output Processing Pipe Link Connection x Control (OPPLC2CTL)

Package

00000000h

a24h

2

Output Processing Pipe Link Connection x Format (OPPLC2FMT)

Package

0000h

a28h

4

Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC2LLPL)

Package

00000000h

a2ch

4

Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC2LLPU)

Package

00000000h

a30h

4

Output Processing Pipe Link Connection x Control (OPPLC3CTL)

Package

00000000h

a34h

2

Output Processing Pipe Link Connection x Format (OPPLC3FMT)

Package

0000h

a38h

4

Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC3LLPL)

Package

00000000h

a3ch

4

Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC3LLPU)

Package

00000000h

a40h

4

Output Processing Pipe Link Connection x Control (OPPLC4CTL)

Package

00000000h

a44h

2

Output Processing Pipe Link Connection x Format (OPPLC4FMT)

Package

0000h

a48h

4

Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC4LLPL)

Package

00000000h

a4ch

4

Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC4LLPU)

Package

00000000h

a50h

4

Output Processing Pipe Link Connection x Control (OPPLC5CTL)

Package

00000000h

a54h

2

Output Processing Pipe Link Connection x Format (OPPLC5FMT)

Package

0000h

a58h

4

Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC5LLPL)

Package

00000000h

a5ch

4

Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC5LLPU)

Package

00000000h

a60h

4

Output Processing Pipe Link Connection x Control (OPPLC6CTL)

Package

00000000h

a64h

2

Output Processing Pipe Link Connection x Format (OPPLC6FMT)

Package

0000h

a68h

4

Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC6LLPL)

Package

00000000h

a6ch

4

Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC6LLPU)

Package

00000000h

a70h

4

Output Processing Pipe Link Connection x Control (OPPLC7CTL)

Package

00000000h

a74h

2

Output Processing Pipe Link Connection x Format (OPPLC7FMT)

Package

0000h

a78h

4

Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC7LLPL)

Package

00000000h

a7ch

4

Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC7LLPU)

Package

00000000h

a80h

4

Output Processing Pipe Link Connection x Control (OPPLC8CTL)

Package

00000000h

a84h

2

Output Processing Pipe Link Connection x Format (OPPLC8FMT)

Package

0000h

a88h

4

Output Processing Pipe Link Connection x Linear Link Position Lower (OPPLC8LLPL)

Package

00000000h

a8ch

4

Output Processing Pipe Link Connection x Linear Link Position Upper (OPPLC8LLPU)

Package

00000000h

c00h

4

Multiple Links Capability Header (MLCH)

Package

00020500h

c04h

4

Multiple Links Capability Declaration (MLCD)

Package

00000005h

c40h

4

HD-A Link Capabilities (HDALCAP)

Package

04000007h

c44h

4

HD-A Link Control (HDALCTL)

Package

00010002h

c48h

4

HD-A Link Output Stream ID Valid (HDALOSIDV)

Package

0000FFFEh

c4ch

2

HD-A Link SDI IDentifiers (HDALSDIID)

Package

0003h

c80h

4

iDisp-A Link Capabilities (IDALCAP)

Package

0400001Fh

c84h

4

iDisp-A Link Control (IDALCTL)

Package

00010004h

c88h

4

iDisp-A Link Output Stream ID Valid (IDALOSIDV)

Package

0000FFFEh

c8ch

2

iDisp-A Link SDI IDentifiers (IDALSDIID)

Package

0004h

c90h

1

iDisp-A Link Per Stream Output Overhead (IDALPSOO)

Package

02h

c92h

1

iDisp-A Link Per Stream Input Overhead (IDALPSIO)

Package

02h

c98h

4

iDisp-A Link Wall Frame Counter (IDALWALFC)

Package

00000000h

ca0h

2

iDisp-A Link 6 MHz Output Payload Capability (IDALOUTPAY6)

Package

0003h

ca2h

2

iDisp-A Link 12 MHz Output Payload Capability (IDALOUTPAY12)

Package

000Bh

ca4h

2

iDisp-A Link 24 MHz Output Payload Capability (IDALOUTPAY24)

Package

001Ah

ca6h

2

iDisp-A Link 48 MHz Output Payload Capability (IDALOUTPAY48)

Package

0038h

ca8h

2

iDisp-A Link 96 MHz Output Payload Capability (IDALOUTPAY96)

Package

0074h

cb0h

2

iDisp-A Link 6 MHz Input Payload Capability (IDALINPAY6)

Package

0000h

cb2h

2

iDisp-A Link 12 MHz Input Payload Capability (IDALINPAY12)

Package

0000h

cb4h

2

iDisp-A Link 24 MHz Input Payload Capability (IDALINPAY24)

Package

0000h

cb6h

2

iDisp-A Link 48 MHz Input Payload Capability (IDALINPAY48)

Package

0000h

cb8h

2

iDisp-A Link 96 MHz Input Payload Capability (IDALINPAY96)

Package

0000h

cc0h

4

DMIC Link Capabilities (DMICLCAP)

Package

1C800000h

cc4h

4

DMIC Link Control (DMICLCTL)

Package

00000000h

cc8h

4

DMIC Link Output Stream ID Valid (DMICLOSIDV)

Package

00000000h

ccch

2

DMIC Link SDI IDentifiers (DMICLSDIID)

Package

0000h

cdch

4

DMIC Link Synchronization (DMICLSYNC)

Package

00000000h

ce0h

4

DMIC Link Extension Pointer (DMICLEPTR)

Package

C1010000h

d00h

4

I2S / PCM Link Capabilities (I2SLCAP)

Package

1CA00000h

d04h

4

I2S / PCM Link Control (I2SLCTL)

Package

00000000h

d08h

4

I2S / PCM Link Output Stream ID Valid (I2SLOSIDV)

Package

00000000h

d0ch

2

I2S / PCM Link SDI IDentifiers (I2SLSDIID0)

Package

0000h

d1ch

4

I2S / PCM Link Synchronization (I2SLSYNC)

Package

00000000h

d20h

4

I2S / PCM Link Extension Pointer (I2SLEPTR)

Package

C0028000h

d40h

4

USB Audio Offload Link Capabilities (UAOLCAP)

Package

14000000h

d44h

4

USB Audio Offload Link Control (UAOLCTL)

Package

00000000h

d48h

4

USB Audio Offload Link Output Stream ID Valid (UAOLOSIDV)

Package

00000000h

d4ch

2

USB Audio Offload Link SDI IDentifiers (UAOLSDIID)

Package

0000h

d60h

4

USB Audio Offload Link Extension Pointer (UAOLEPTR)

Package

C200F000h

d80h

4

SoundWire Link Capabilities (SNDWLCAP)

Package

1CC00000h

d84h

4

SoundWire Link Control (SNDWLCTL)

Package

00000000h

d88h

4

SoundWire Link Output Stream ID Valid (SNDWLOSIDV)

Package

00000000h

d8ch

2

SoundWire Link SDI IDentifiers (SNDWLSDIID0)

Package

0000h

d8eh

2

SoundWire Link SDI IDentifiers (SNDWLSDIID1)

Package

0000h

d90h

2

SoundWire Link SDI IDentifiers (SNDWLSDIID2)

Package

0000h

d92h

2

SoundWire Link SDI IDentifiers (SNDWLSDIID3)

Package

0000h

d94h

2

SoundWire Link SDI IDentifiers (SNDWLSDIID4)

Package

0000h

d9ch

4

SoundWire Link Synchronization (SNDWLSYNC)

Package

00000000h

da0h

4

SoundWire Link Extension Pointer (SNDWLEPTR)

Package

00030000h

1c04h

4

IOSF Status (IOSFSTS)

Package

00000000h

1c10h

4

Traffic Class Assignments (TCA)

Package

00008000h

1c14h

4

Transfer Traffic Class Configuration (TTCCFG)

Package

00000020h

1c34h

2

Codec Configuration (CDCCFG)

Package

0000h

1c70h

2

Host PCI Configuration Control (HfPCICFGCTL)

Package

0080h

1c80h

4

Fuse Value (FUSVAL)

Package

00000000h

1c88h

4

Set ID Value (DW0) (SETIDVAL0)

Package

00000000h

1c8ch

4

Set ID Value (DW1) (SETIDVAL1)

Package

00000000h

1c90h

4

Hard Strap Value (HSTRVAL)

Package

00000000h

1c94h

4

Soft Strap Value (SSTRVAL)

Package

00000000h

1c98h

4

HD-A Hardware Initialization (DW0) (HDAHWI0)

Package

00000006h

1c9ch

4

HD-A Hardware Initialization (DW1) (HDAHWI1)

Package

003C001Dh

1ca0h

4

Host PCI Configuration Hardware Initialization (DW 0) (HfPCICFGHWI0)

Package

04030098h

1ca4h

4

Host PCI Configuration Hardware Initialization (DW 1) (HfPCICFGHWI1)

Package

00000000h

1ca8h

4

Host PCI Configuration Soft Strap Value (DW 0) (HfPCICFGSSV0)

Package

04030010h

1cach

4

Host PCI Configuration Soft Strap Value (DW 1) (HfPCICFGSSV1)

Package

00000000h

1cb0h

4

Host PCI Configuration Hardware Initialization Select (HfPCICFGHWIS)

Package

00000000h

1d00h

4

Power Management / Clock Capability (HfPMCCAP)

Package

05A300A2h

1d04h

4

Power Management / Clock Control (HST) Pointer (HfPMCCHPTR)

Package

00001D40h

1d10h

4

Clock Control (HfCLKCTL)

Package

000003FFh

1d14h

4

Clock Status (HfCLKSTS)

Package

00000000h

1d18h

2

Power Control (HfPWRCTL)

Package

0000h

1d1ch

2

Power Status (HfPWRSTS)

Package

0000h

1d20h

2

Power Control 2 (HfPWRCTL2)

Package

0000h

1d24h

2

Power Status 2 (HfPWRSTS2)

Package

0000h

1d4ah

1

D0i3 Control (D0I3C)

Package

08h

1e30h

4

Function Configuration (FNCFG)

Package

0000002Ah

2030h

4

Wall Clock Counter Alias (WALCLKA)

Package

00000000h

2084h

4

Input Stream Descriptor x Link Position in Buffer Alias (ISD0LPIBA)

Package

00000000h

20a4h

4

Input Stream Descriptor x Link Position in Buffer Alias (ISD1LPIBA)

Package

00000000h

20c4h

4

Input Stream Descriptor x Link Position in Buffer Alias (ISD2LPIBA)

Package

00000000h

20e4h

4

Input Stream Descriptor x Link Position in Buffer Alias (ISD3LPIBA)

Package

00000000h

2104h

4

Input Stream Descriptor x Link Position in Buffer Alias (ISD4LPIBA)

Package

00000000h

2124h

4

Input Stream Descriptor x Link Position in Buffer Alias (ISD5LPIBA)

Package

00000000h

2144h

4

Input Stream Descriptor x Link Position in Buffer Alias (ISD6LPIBA)

Package

00000000h

2164h

4

Input Stream Descriptor x Link Position in Buffer Alias (ISD7LPIBA)

Package

00000000h

2184h

4

Input Stream Descriptor x Link Position in Buffer Alias (ISD8LPIBA)

Package

00000000h

21a4h

4

Input Stream Descriptor x Link Position in Buffer Alias (ISD9LPIBA)

Package

00000000h

21c4h

4

Input Stream Descriptor x Link Position in Buffer Alias (ISD10LPIBA)

Package

00000000h

21e4h

4

Output Stream Descriptor x Link Position in Buffer Alias (OSD0LPIBA)

Package

00000000h

2204h

4

Output Stream Descriptor x Link Position in Buffer Alias (OSD1LPIBA)

Package

00000000h

2224h

4

Output Stream Descriptor x Link Position in Buffer Alias (OSD2LPIBA)

Package

00000000h

2244h

4

Output Stream Descriptor x Link Position in Buffer Alias (OSD3LPIBA)

Package

00000000h

2264h

4

Output Stream Descriptor x Link Position in Buffer Alias (OSD4LPIBA)

Package

00000000h

2284h

4

Output Stream Descriptor x Link Position in Buffer Alias (OSD5LPIBA)

Package

00000000h

22a4h

4

Output Stream Descriptor x Link Position in Buffer Alias (OSD6LPIBA)

Package

00000000h

22c4h

4

Output Stream Descriptor x Link Position in Buffer Alias (OSD7LPIBA)

Package

00000000h

22e4h

4

Output Stream Descriptor x Link Position in Buffer Alias (OSD8LPIBA)

Package

00000000h

f010h

2

USB Audio Offload Link x PCM Stream Capabilities (UAOL0PCMSCAP)

Package

0024h

f014h

2

USB Audio Offload Link x PCM Stream y Channel Count (UAOL0PCMS0CHC)

Package

0007h

f016h

2

USB Audio Offload Link x PCM Stream y Channel Map (UAOL0PCMS0CM)

Package

00F0h

f018h

2

USB Audio Offload Link x PCM Stream y Channel Count (UAOL0PCMS1CHC)

Package

0007h

f01ah

2

USB Audio Offload Link x PCM Stream y Channel Map (UAOL0PCMS1CM)

Package

00F0h

f01ch

2

USB Audio Offload Link x PCM Stream y Channel Count (UAOL0PCMS2CHC)

Package

0007h

f01eh

2

USB Audio Offload Link x PCM Stream y Channel Map (UAOL0PCMS2CM)

Package

00F0h

f020h

2

USB Audio Offload Link x PCM Stream y Channel Count (UAOL0PCMS3CHC)

Package

0007h

f022h

2

USB Audio Offload Link x PCM Stream y Channel Map (UAOL0PCMS3CM)

Package

00F0h

f024h

2

USB Audio Offload Link x PCM Stream y Channel Count (UAOL0PCMS4CHC)

Package

0007h

f026h

2

USB Audio Offload Link x PCM Stream y Channel Map (UAOL0PCMS4CM)

Package

00F0h

f028h

2

USB Audio Offload Link x PCM Stream y Channel Count (UAOL0PCMS5CHC)

Package

0007h

f02ah

2

USB Audio Offload Link x PCM Stream y Channel Map (UAOL0PCMS5CM)

Package

00F0h

f100h

2

USB Audio Offload Link x Target Bus / Device / Function (UAOL0TBDF)

Package

0000h

f104h

2

USB Audio Offload Link x Output Payload Capability (UAOL0OPC)

Package

0C00h

f106h

2

USB Audio Offload Link x Input Payload Capability (UAOL0IPC)

Package

0700h

f110h

4

USB Audio Offload Link x Frame Counter (UAOL0FC)

Package

00000000h

f114h

4

USB Audio Offload Link x Frame Adjustment (UAOL0FA)

Package

00000000h

f118h

4

USB Audio Offload Link x Immediate Command (UAOL0IC)

Package

00000000h

f11ch

4

USB Audio Offload Link x Immediate Response (UAOL0IR)

Package

00000000h

f120h

4

USB Audio Offload Link x Immediate Command Payload y (UAOL0ICP0)

Package

00000000h

f124h

4

USB Audio Offload Link x Immediate Command Payload y (UAOL0ICP1)

Package

00000000h

f128h

4

USB Audio Offload Link x Immediate Command Payload y (UAOL0ICP2)

Package

00000000h

f12ch

4

USB Audio Offload Link x Immediate Command Payload y (UAOL0ICP3)

Package

00000000h

f130h

4

USB Audio Offload Link x Immediate Response Payload y (UAOL0IRP0)

Package

00000000h

f134h

4

USB Audio Offload Link x Immediate Response Payload y (UAOL0IRP1)

Package

00000000h

f138h

4

USB Audio Offload Link x Immediate Response Payload y (UAOL0IRP2)

Package

00000000h

f13ch

4

USB Audio Offload Link x Immediate Response Payload y (UAOL0IRP3)

Package

00000000h

f140h

8

USB Audio Offload Link x PCM Stream y Format (UAOL0PCMS0CTL)

Package

0002000000000000h

f148h

4

USB Audio Offload Link x PCM Stream y Status (UAOL0PCMS0STS)

Package

00000000h

f14ch

4

USB Audio Offload Link x PCM Stream y Fractional Rate Adjustment (UAOL0PCMS0RA)

Package

00000000h

f150h

2

USB Audio Offload Link x PCM Stream y FIFO Address (UAOL0PCMS0FSA)

Package

0000h

f160h

8

USB Audio Offload Link x PCM Stream y Format (UAOL0PCMS1CTL)

Package

0002000000000000h

f168h

4

USB Audio Offload Link x PCM Stream y Status (UAOL0PCMS1STS)

Package

00000000h

f16ch

4

USB Audio Offload Link x PCM Stream y Fractional Rate Adjustment (UAOL0PCMS1RA)

Package

00000000h

f170h

2

USB Audio Offload Link x PCM Stream y FIFO Address (UAOL0PCMS1FSA)

Package

0000h

f180h

8

USB Audio Offload Link x PCM Stream y Format (UAOL0PCMS2CTL)

Package

0002000000000000h

f188h

4

USB Audio Offload Link x PCM Stream y Status (UAOL0PCMS2STS)

Package

00000000h

f18ch

4

USB Audio Offload Link x PCM Stream y Fractional Rate Adjustment (UAOL0PCMS2RA)

Package

00000000h

f190h

2

USB Audio Offload Link x PCM Stream y FIFO Address (UAOL0PCMS2FSA)

Package

0000h

f1a0h

8

USB Audio Offload Link x PCM Stream y Format (UAOL0PCMS3CTL)

Package

0002000000000000h

f1a8h

4

USB Audio Offload Link x PCM Stream y Status (UAOL0PCMS3STS)

Package

00000000h

f1ach

4

USB Audio Offload Link x PCM Stream y Fractional Rate Adjustment (UAOL0PCMS3RA)

Package

00000000h

f1b0h

2

USB Audio Offload Link x PCM Stream y FIFO Address (UAOL0PCMS3FSA)

Package

0000h

f1c0h

8

USB Audio Offload Link x PCM Stream y Format (UAOL0PCMS4CTL)

Package

0002000000000000h

f1c8h

4

USB Audio Offload Link x PCM Stream y Status (UAOL0PCMS4STS)

Package

00000000h

f1cch

4

USB Audio Offload Link x PCM Stream y Fractional Rate Adjustment (UAOL0PCMS4RA)

Package

00000000h

f1d0h

2

USB Audio Offload Link x PCM Stream y FIFO Address (UAOL0PCMS4FSA)

Package

0000h

f1e0h

8

USB Audio Offload Link x PCM Stream y Format (UAOL0PCMS5CTL)

Package

0002000000000000h

f1e8h

4

USB Audio Offload Link x PCM Stream y Status (UAOL0PCMS5STS)

Package

00000000h

f1ech

4

USB Audio Offload Link x PCM Stream y Fractional Rate Adjustment (UAOL0PCMS5RA)

Package

00000000h

f1f0h

2

USB Audio Offload Link x PCM Stream y FIFO Address (UAOL0PCMS5FSA)

Package

0000h

fc04h

4

USB Audio Offload Link x Vendor Specific Control (UAOL0VSCTL)

Package

00000000h

10010h

2

Digital Microphone x PCM Stream Capabilities (DMIC0PCMSCAP)

Package

0002h

10014h

2

Digital Microphone PCM Stream y Channel Count (DMIC0PCMS0CHC)

Package

0003h

10016h

2

Digital Microphone x PCM Stream y Channel Map (DMIC0PCMS0CM)

Package

00F0h

10018h

2

Digital Microphone PCM Stream y Channel Count (DMIC0PCMS1CHC)

Package

0003h

1001ah

2

Digital Microphone x PCM Stream y Channel Map (DMIC0PCMS1CM)

Package

00F0h

10100h

4

Microphone HiQ Output Control and Status Register (OUTCONTROL0)

Package

00400000h

10104h

4

Microphone HiQ Channel Status Register (OUTSTATUS0)

Package

00000000h

10108h

4

Microphone Data Readout and Test Registers (OUTDATA0)

Package

00000000h

10200h

4

Microphone HiQ Output Control and Status Register (OUTCONTROL1)

Package

00400000h

10204h

4

Microphone HiQ Channel Status Register (OUTSTATUS1)

Package

00000000h

10208h

4

Microphone Data Readout and Test Registers (OUTDATA1)

Package

00000000h

11100h

4

CIC Filter Control Register (PDMCTRL0_​CIC_​CONTROL)

Package

00010002h

11104h

4

CIC Filter Configuration Register (PDMCTRL0_​CIC_​CONFIG)

Package

01000800h

1110ch

4

Microphone Control Register (PDMCTRL0_​MIC_​CONTROL)

Package

00000600h

11120h

4

FIR Filter Control Register (PDMCTRL0_​FIR_​CONTROL_​A)

Package

70000010h

11124h

4

FIR Filter Configuration Register (PDMCTRL0_​FIR_​CONFIG_​A)

Package

000401FAh

11128h

4

DC Offset Control Register, left channel (PDMCTRL0_​DC_​OFFSET_​LEFT_​A)

Package

00000000h

1112ch

4

DC Offset Control Register, right channel (PDMCTRL0_​DC_​OFFSET_​RIGHT_​A)

Package

00000000h

11130h

4

Output Gain Control Register, left channel (PDMCTRL0_​OUT_​GAIN_​LEFT_​A)

Package

00000000h

11134h

4

Output Gain Control Register, right channel (PDMCTRL0_​OUT_​GAIN_​RIGHT_​A)

Package

00000000h

11140h

4

FIR Filter Control Register (PDMCTRL0_​FIR_​CONTROL_​B)

Package

70000010h

11144h

4

FIR Filter Configuration Register (PDMCTRL0_​FIR_​CONFIG_​B)

Package

000401FAh

11148h

4

DC Offset Control Register, left channel (PDMCTRL0_​DC_​OFFSET_​LEFT_​B)

Package

00000000h

1114ch

4

DC Offset Control Register, right channel (PDMCTRL0_​DC_​OFFSET_​RIGHT_​B)

Package

00000000h

11150h

4

Output Gain Control Register, left channel (PDMCTRL0_​OUT_​GAIN_​LEFT_​B)

Package

00000000h

11154h

4

Output Gain Control Register, right channel (PDMCTRL0_​OUT_​GAIN_​RIGHT_​B)

Package

00000000h

12100h

4

CIC Filter Control Register (PDMCTRL1_​CIC_​CONTROL)

Package

00010002h

12104h

4

CIC Filter Configuration Register (PDMCTRL1_​CIC_​CONFIG)

Package

01000800h

1210ch

4

Microphone Control Register (PDMCTRL1_​MIC_​CONTROL)

Package

00000600h

12120h

4

FIR Filter Control Register (PDMCTRL1_​FIR_​CONTROL_​A)

Package

70000010h

12124h

4

FIR Filter Configuration Register (PDMCTRL1_​FIR_​CONFIG_​A)

Package

000401FAh

12128h

4

DC Offset Control Register, left channel (PDMCTRL1_​DC_​OFFSET_​LEFT_​A)

Package

00000000h

1212ch

4

DC Offset Control Register, right channel (PDMCTRL1_​DC_​OFFSET_​RIGHT_​A)

Package

00000000h

12130h

4

Output Gain Control Register, left channel (PDMCTRL1_​OUT_​GAIN_​LEFT_​A)

Package

00000000h

12134h

4

Output Gain Control Register, right channel (PDMCTRL1_​OUT_​GAIN_​RIGHT_​A)

Package

00000000h

12140h

4

FIR Filter Control Register (PDMCTRL1_​FIR_​CONTROL_​B)

Package

70000010h

12144h

4

FIR Filter Configuration Register (PDMCTRL1_​FIR_​CONFIG_​B)

Package

000401FAh

12148h

4

DC Offset Control Register, left channel (PDMCTRL1_​DC_​OFFSET_​LEFT_​B)

Package

00000000h

1214ch

4

DC Offset Control Register, right channel (PDMCTRL1_​DC_​OFFSET_​RIGHT_​B)

Package

00000000h

12150h

4

Output Gain Control Register, left channel (PDMCTRL1_​OUT_​GAIN_​LEFT_​B)

Package

00000000h

12154h

4

Output Gain Control Register, right channel (PDMCTRL1_​OUT_​GAIN_​RIGHT_​B)

Package

00000000h

16004h

4

Digital Microphone x Link Vendor Specific Control (DMIC0LVSCTL)

Package

00000000h

16010h

2

Digital Microphone x Privacy Control & Status (DMIC0PVCCS)

Package

0000h

28010h

2

I2S x PCM Stream Capabilities (I2S0PCMSCAP)

Package

0088h

28014h

2

I2S x PCM Stream y Channel Count (I2S0PCMS0CHC)

Package

000Fh

28016h

2

I2S x PCM Stream y Channel Map (I2S0PCMS0CM)

Package

00F0h

28018h

2

I2S x PCM Stream y Channel Count (I2S0PCMS1CHC)

Package

000Fh

2801ah

2

I2S x PCM Stream y Channel Map (I2S0PCMS1CM)

Package

00F0h

2801ch

2

I2S x PCM Stream y Channel Count (I2S0PCMS2CHC)

Package

000Fh

2801eh

2

I2S x PCM Stream y Channel Map (I2S0PCMS2CM)

Package

00F0h

28020h

2

I2S x PCM Stream y Channel Count (I2S0PCMS3CHC)

Package

000Fh

28022h

2

I2S x PCM Stream y Channel Map (I2S0PCMS3CM)

Package

00F0h

28024h

2

I2S x PCM Stream y Channel Count (I2S0PCMS4CHC)

Package

000Fh

28026h

2

I2S x PCM Stream y Channel Map (I2S0PCMS4CM)

Package

00F0h

28028h

2

I2S x PCM Stream y Channel Count (I2S0PCMS5CHC)

Package

000Fh

2802ah

2

I2S x PCM Stream y Channel Map (I2S0PCMS5CM)

Package

00F0h

2802ch

2

I2S x PCM Stream y Channel Count (I2S0PCMS6CHC)

Package

000Fh

2802eh

2

I2S x PCM Stream y Channel Map (I2S0PCMS6CM)

Package

00F0h

28030h

2

I2S x PCM Stream y Channel Count (I2S0PCMS7CHC)

Package

000Fh

28032h

2

I2S x PCM Stream y Channel Map (I2S0PCMS7CM)

Package

00F0h

28034h

2

I2S x PCM Stream y Channel Count (I2S0PCMS8CHC)

Package

000Fh

28036h

2

I2S x PCM Stream y Channel Map (I2S0PCMS8CM)

Package

00F0h

28038h

2

I2S x PCM Stream y Channel Count (I2S0PCMS9CHC)

Package

000Fh

2803ah

2

I2S x PCM Stream y Channel Map (I2S0PCMS9CM)

Package

00F0h

2803ch

2

I2S x PCM Stream y Channel Count (I2S0PCMS10CHC)

Package

000Fh

2803eh

2

I2S x PCM Stream y Channel Map (I2S0PCMS10CM)

Package

00F0h

28040h

2

I2S x PCM Stream y Channel Count (I2S0PCMS11CHC)

Package

000Fh

28042h

2

I2S x PCM Stream y Channel Map (I2S0PCMS11CM)

Package

00F0h

28044h

2

I2S x PCM Stream y Channel Count (I2S0PCMS12CHC)

Package

000Fh

28046h

2

I2S x PCM Stream y Channel Map (I2S0PCMS12CM)

Package

00F0h

28048h

2

I2S x PCM Stream y Channel Count (I2S0PCMS13CHC)

Package

000Fh

2804ah

2

I2S x PCM Stream y Channel Map (I2S0PCMS13CM)

Package

00F0h

2804ch

2

I2S x PCM Stream y Channel Count (I2S0PCMS14CHC)

Package

000Fh

2804eh

2

I2S x PCM Stream y Channel Map (I2S0PCMS14CM)

Package

00F0h

28050h

2

I2S x PCM Stream y Channel Count (I2S0PCMS15CHC)

Package

000Fh

28052h

2

I2S x PCM Stream y Channel Map (I2S0PCMS15CM)

Package

00F0h

28100h

4

SSP x Control 0 (I2S0_​SSC0)

Package

80000070h

28104h

4

SSP x Control 1 (I2S0_​SSC1)

Package

00000000h

28108h

4

SSP x Status (I2S0_​SSS)

Package

00000000h

28128h

4

SSP x Time Out (I2S0_​SSTO)

Package

00000000h

2812ch

4

SSP x Programmable Serial Protocol (I2S0_​SSPSP)

Package

00000000h

28138h

4

SSP x Time Slot Status (I2S0_​SSTSS)

Package

00000000h

28140h

4

SSP x Command / Status 2 (I2S0_​SSC2)

Package

40000000h

28144h

4

SSP x Programmable Serial Protocol 2 (I2S0_​SSPSP2)

Package

00000000h

28148h

4

SSP x Reserved 2 (I2S0_​SSRSVD2)

Package

00000000h

2814ch

4

SSP x IO Control (I2S0_​SSIOC)

Package

00000000h

28150h

4

SSP x Global Frame Synchronization (I2S0_​SSGFS)

Package

00000000h

28160h

4

SSP x Multi Input DMA y Control / Status (I2S0_​SSMID0CS)

Package

00000000h

28164h

4

SSP x Multi Input DMA y Data (I2S0_​SSMID0D)

Package

00000000h

28168h

8

SSP x Multi Input DMA y Time Slot Active (I2S0_​SSMID0TSA)

Package

0000000000000000h

28170h

4

SSP x Multi Input DMA y Control / Status (I2S0_​SSMID1CS)

Package

00000000h

28174h

4

SSP x Multi Input DMA y Data (I2S0_​SSMID1D)

Package

00000000h

28178h

8

SSP x Multi Input DMA y Time Slot Active (I2S0_​SSMID1TSA)

Package

0000000000000000h

28180h

4

SSP x Multi Input DMA y Control / Status (I2S0_​SSMID2CS)

Package

00000000h

28184h

4

SSP x Multi Input DMA y Data (I2S0_​SSMID2D)

Package

00000000h

28188h

8

SSP x Multi Input DMA y Time Slot Active (I2S0_​SSMID2TSA)

Package

0000000000000000h

28190h

4

SSP x Multi Input DMA y Control / Status (I2S0_​SSMID3CS)

Package

00000000h

28194h

4

SSP x Multi Input DMA y Data (I2S0_​SSMID3D)

Package

00000000h

28198h

8

SSP x Multi Input DMA y Time Slot Active (I2S0_​SSMID3TSA)

Package

0000000000000000h

281a0h

4

SSP x Multi Input DMA y Control / Status (I2S0_​SSMID4CS)

Package

00000000h

281a4h

4

SSP x Multi Input DMA y Data (I2S0_​SSMID4D)

Package

00000000h

281a8h

8

SSP x Multi Input DMA y Time Slot Active (I2S0_​SSMID4TSA)

Package

0000000000000000h

281b0h

4

SSP x Multi Input DMA y Control / Status (I2S0_​SSMID5CS)

Package

00000000h

281b4h

4

SSP x Multi Input DMA y Data (I2S0_​SSMID5D)

Package

00000000h

281b8h

8

SSP x Multi Input DMA y Time Slot Active (I2S0_​SSMID5TSA)

Package

0000000000000000h

281c0h

4

SSP x Multi Input DMA y Control / Status (I2S0_​SSMID6CS)

Package

00000000h

281c4h

4

SSP x Multi Input DMA y Data (I2S0_​SSMID6D)

Package

00000000h

281c8h

8

SSP x Multi Input DMA y Time Slot Active (I2S0_​SSMID6TSA)

Package

0000000000000000h

281d0h

4

SSP x Multi Input DMA y Control / Status (I2S0_​SSMID7CS)

Package

00000000h

281d4h

4

SSP x Multi Input DMA y Data (I2S0_​SSMID7D)

Package

00000000h

281d8h

8

SSP x Multi Input DMA y Time Slot Active (I2S0_​SSMID7TSA)

Package

0000000000000000h

281e0h

4

SSP x Multi Output DMA y Control / Status (I2S0_​SSMOD0CS)

Package

04000000h

281e4h

4

SSP x Multi Output DMA y Data (I2S0_​SSMOD0D)

Package

00000000h

281e8h

8

SSP x Multi Output DMA y Time Slot Active (I2S0_​SSMOD0TSA)

Package

0000000000000000h

281f0h

4

SSP x Multi Output DMA y Control / Status (I2S0_​SSMOD1CS)

Package

04000000h

281f4h

4

SSP x Multi Output DMA y Data (I2S0_​SSMOD1D)

Package

00000000h

281f8h

8

SSP x Multi Output DMA y Time Slot Active (I2S0_​SSMOD1TSA)

Package

0000000000000000h

28200h

4

SSP x Multi Output DMA y Control / Status (I2S0_​SSMOD2CS)

Package

04000000h

28204h

4

SSP x Multi Output DMA y Data (I2S0_​SSMOD2D)

Package

00000000h

28208h

8

SSP x Multi Output DMA y Time Slot Active (I2S0_​SSMOD2TSA)

Package

0000000000000000h

28210h

4

SSP x Multi Output DMA y Control / Status (I2S0_​SSMOD3CS)

Package

04000000h

28214h

4

SSP x Multi Output DMA y Data (I2S0_​SSMOD3D)

Package

00000000h

28218h

8

SSP x Multi Output DMA y Time Slot Active (I2S0_​SSMOD3TSA)

Package

0000000000000000h

28220h

4

SSP x Multi Output DMA y Control / Status (I2S0_​SSMOD4CS)

Package

04000000h

28224h

4

SSP x Multi Output DMA y Data (I2S0_​SSMOD4D)

Package

00000000h

28228h

8

SSP x Multi Output DMA y Time Slot Active (I2S0_​SSMOD4TSA)

Package

0000000000000000h

28230h

4

SSP x Multi Output DMA y Control / Status (I2S0_​SSMOD5CS)

Package

04000000h

28234h

4

SSP x Multi Output DMA y Data (I2S0_​SSMOD5D)

Package

00000000h

28238h

8

SSP x Multi Output DMA y Time Slot Active (I2S0_​SSMOD5TSA)

Package

0000000000000000h

28240h

4

SSP x Multi Output DMA y Control / Status (I2S0_​SSMOD6CS)

Package

04000000h

28244h

4

SSP x Multi Output DMA y Data (I2S0_​SSMOD6D)

Package

00000000h

28248h

8

SSP x Multi Output DMA y Time Slot Active (I2S0_​SSMOD6TSA)

Package

0000000000000000h

28250h

4

SSP x Multi Output DMA y Control / Status (I2S0_​SSMOD7CS)

Package

04000000h

28254h

4

SSP x Multi Output DMA y Data (I2S0_​SSMOD7D)

Package

00000000h

28258h

8

SSP x Multi Output DMA y Time Slot Active (I2S0_​SSMOD7TSA)

Package

0000000000000000h

28c04h

4

I2S x Link Vendor Specific Control (I2S0LVSCTL)

Package

00000000h

29010h

2

I2S x PCM Stream Capabilities (I2S1PCMSCAP)

Package

0088h

29014h

2

I2S x PCM Stream y Channel Count (I2S1PCMS0CHC)

Package

000Fh

29016h

2

I2S x PCM Stream y Channel Map (I2S1PCMS0CM)

Package

00F0h

29018h

2

I2S x PCM Stream y Channel Count (I2S1PCMS1CHC)

Package

000Fh

2901ah

2

I2S x PCM Stream y Channel Map (I2S1PCMS1CM)

Package

00F0h

2901ch

2

I2S x PCM Stream y Channel Count (I2S1PCMS2CHC)

Package

000Fh

2901eh

2

I2S x PCM Stream y Channel Map (I2S1PCMS2CM)

Package

00F0h

29020h

2

I2S x PCM Stream y Channel Count (I2S1PCMS3CHC)

Package

000Fh

29022h

2

I2S x PCM Stream y Channel Map (I2S1PCMS3CM)

Package

00F0h

29024h

2

I2S x PCM Stream y Channel Count (I2S1PCMS4CHC)

Package

000Fh

29026h

2

I2S x PCM Stream y Channel Map (I2S1PCMS4CM)

Package

00F0h

29028h

2

I2S x PCM Stream y Channel Count (I2S1PCMS5CHC)

Package

000Fh

2902ah

2

I2S x PCM Stream y Channel Map (I2S1PCMS5CM)

Package

00F0h

2902ch

2

I2S x PCM Stream y Channel Count (I2S1PCMS6CHC)

Package

000Fh

2902eh

2

I2S x PCM Stream y Channel Map (I2S1PCMS6CM)

Package

00F0h

29030h

2

I2S x PCM Stream y Channel Count (I2S1PCMS7CHC)

Package

000Fh

29032h

2

I2S x PCM Stream y Channel Map (I2S1PCMS7CM)

Package

00F0h

29034h

2

I2S x PCM Stream y Channel Count (I2S1PCMS8CHC)

Package

000Fh

29036h

2

I2S x PCM Stream y Channel Map (I2S1PCMS8CM)

Package

00F0h

29038h

2

I2S x PCM Stream y Channel Count (I2S1PCMS9CHC)

Package

000Fh

2903ah

2

I2S x PCM Stream y Channel Map (I2S1PCMS9CM)

Package

00F0h

2903ch

2

I2S x PCM Stream y Channel Count (I2S1PCMS10CHC)

Package

000Fh

2903eh

2

I2S x PCM Stream y Channel Map (I2S1PCMS10CM)

Package

00F0h

29040h

2

I2S x PCM Stream y Channel Count (I2S1PCMS11CHC)

Package

000Fh

29042h

2

I2S x PCM Stream y Channel Map (I2S1PCMS11CM)

Package

00F0h

29044h

2

I2S x PCM Stream y Channel Count (I2S1PCMS12CHC)

Package

000Fh

29046h

2

I2S x PCM Stream y Channel Map (I2S1PCMS12CM)

Package

00F0h

29048h

2

I2S x PCM Stream y Channel Count (I2S1PCMS13CHC)

Package

000Fh

2904ah

2

I2S x PCM Stream y Channel Map (I2S1PCMS13CM)

Package

00F0h

2904ch

2

I2S x PCM Stream y Channel Count (I2S1PCMS14CHC)

Package

000Fh

2904eh

2

I2S x PCM Stream y Channel Map (I2S1PCMS14CM)

Package

00F0h

29050h

2

I2S x PCM Stream y Channel Count (I2S1PCMS15CHC)

Package

000Fh

29052h

2

I2S x PCM Stream y Channel Map (I2S1PCMS15CM)

Package

00F0h

29100h

4

SSP x Control 0 (I2S1_​SSC0)

Package

80000070h

29104h

4

SSP x Control 1 (I2S1_​SSC1)

Package

00000000h

29108h

4

SSP x Status (I2S1_​SSS)

Package

00000000h

29128h

4

SSP x Time Out (I2S1_​SSTO)

Package

00000000h

2912ch

4

SSP x Programmable Serial Protocol (I2S1_​SSPSP)

Package

00000000h

29138h

4

SSP x Time Slot Status (I2S1_​SSTSS)

Package

00000000h

29140h

4

SSP x Command / Status 2 (I2S1_​SSC2)

Package

40000000h

29144h

4

SSP x Programmable Serial Protocol 2 (I2S1_​SSPSP2)

Package

00000000h

2914ch

4

SSP x IO Control (I2S1_​SSIOC)

Package

00000000h

29150h

4

SSP x Global Frame Synchronization (I2S1_​SSGFS)

Package

00000000h

29160h

4

SSP x Multi Input DMA y Control / Status (I2S1_​SSMID0CS)

Package

00000000h

29164h

4

SSP x Multi Input DMA y Data (I2S1_​SSMID0D)

Package

00000000h

29168h

8

SSP x Multi Input DMA y Time Slot Active (I2S1_​SSMID0TSA)

Package

0000000000000000h

29170h

4

SSP x Multi Input DMA y Control / Status (I2S1_​SSMID1CS)

Package

00000000h

29174h

4

SSP x Multi Input DMA y Data (I2S1_​SSMID1D)

Package

00000000h

29178h

8

SSP x Multi Input DMA y Time Slot Active (I2S1_​SSMID1TSA)

Package

0000000000000000h

29180h

4

SSP x Multi Input DMA y Control / Status (I2S1_​SSMID2CS)

Package

00000000h

29184h

4

SSP x Multi Input DMA y Data (I2S1_​SSMID2D)

Package

00000000h

29188h

8

SSP x Multi Input DMA y Time Slot Active (I2S1_​SSMID2TSA)

Package

0000000000000000h

29190h

4

SSP x Multi Input DMA y Control / Status (I2S1_​SSMID3CS)

Package

00000000h

29194h

4

SSP x Multi Input DMA y Data (I2S1_​SSMID3D)

Package

00000000h

29198h

8

SSP x Multi Input DMA y Time Slot Active (I2S1_​SSMID3TSA)

Package

0000000000000000h

291a0h

4

SSP x Multi Input DMA y Control / Status (I2S1_​SSMID4CS)

Package

00000000h

291a4h

4

SSP x Multi Input DMA y Data (I2S1_​SSMID4D)

Package

00000000h

291a8h

8

SSP x Multi Input DMA y Time Slot Active (I2S1_​SSMID4TSA)

Package

0000000000000000h

291b0h

4

SSP x Multi Input DMA y Control / Status (I2S1_​SSMID5CS)

Package

00000000h

291b4h

4

SSP x Multi Input DMA y Data (I2S1_​SSMID5D)

Package

00000000h

291b8h

8

SSP x Multi Input DMA y Time Slot Active (I2S1_​SSMID5TSA)

Package

0000000000000000h

291c0h

4

SSP x Multi Input DMA y Control / Status (I2S1_​SSMID6CS)

Package

00000000h

291c4h

4

SSP x Multi Input DMA y Data (I2S1_​SSMID6D)

Package

00000000h

291c8h

8

SSP x Multi Input DMA y Time Slot Active (I2S1_​SSMID6TSA)

Package

0000000000000000h

291d0h

4

SSP x Multi Input DMA y Control / Status (I2S1_​SSMID7CS)

Package

00000000h

291d4h

4

SSP x Multi Input DMA y Data (I2S1_​SSMID7D)

Package

00000000h

291d8h

8

SSP x Multi Input DMA y Time Slot Active (I2S1_​SSMID7TSA)

Package

0000000000000000h

291e0h

4

SSP x Multi Output DMA y Control / Status (I2S1_​SSMOD0CS)

Package

04000000h

291e4h

4

SSP x Multi Output DMA y Data (I2S1_​SSMOD0D)

Package

00000000h

291e8h

8

SSP x Multi Output DMA y Time Slot Active (I2S1_​SSMOD0TSA)

Package

0000000000000000h

291f0h

4

SSP x Multi Output DMA y Control / Status (I2S1_​SSMOD1CS)

Package

04000000h

291f4h

4

SSP x Multi Output DMA y Data (I2S1_​SSMOD1D)

Package

00000000h

291f8h

8

SSP x Multi Output DMA y Time Slot Active (I2S1_​SSMOD1TSA)

Package

0000000000000000h

29200h

4

SSP x Multi Output DMA y Control / Status (I2S1_​SSMOD2CS)

Package

04000000h

29204h

4

SSP x Multi Output DMA y Data (I2S1_​SSMOD2D)

Package

00000000h

29208h

8

SSP x Multi Output DMA y Time Slot Active (I2S1_​SSMOD2TSA)

Package

0000000000000000h

29210h

4

SSP x Multi Output DMA y Control / Status (I2S1_​SSMOD3CS)

Package

04000000h

29214h

4

SSP x Multi Output DMA y Data (I2S1_​SSMOD3D)

Package

00000000h

29218h

8

SSP x Multi Output DMA y Time Slot Active (I2S1_​SSMOD3TSA)

Package

0000000000000000h

29220h

4

SSP x Multi Output DMA y Control / Status (I2S1_​SSMOD4CS)

Package

04000000h

29224h

4

SSP x Multi Output DMA y Data (I2S1_​SSMOD4D)

Package

00000000h

29228h

8

SSP x Multi Output DMA y Time Slot Active (I2S1_​SSMOD4TSA)

Package

0000000000000000h

29230h

4

SSP x Multi Output DMA y Control / Status (I2S1_​SSMOD5CS)

Package

04000000h

29234h

4

SSP x Multi Output DMA y Data (I2S1_​SSMOD5D)

Package

00000000h

29238h

8

SSP x Multi Output DMA y Time Slot Active (I2S1_​SSMOD5TSA)

Package

0000000000000000h

29240h

4

SSP x Multi Output DMA y Control / Status (I2S1_​SSMOD6CS)

Package

04000000h

29244h

4

SSP x Multi Output DMA y Data (I2S1_​SSMOD6D)

Package

00000000h

29248h

8

SSP x Multi Output DMA y Time Slot Active (I2S1_​SSMOD6TSA)

Package

0000000000000000h

29250h

4

SSP x Multi Output DMA y Control / Status (I2S1_​SSMOD7CS)

Package

04000000h

29254h

4

SSP x Multi Output DMA y Data (I2S1_​SSMOD7D)

Package

00000000h

29258h

8

SSP x Multi Output DMA y Time Slot Active (I2S1_​SSMOD7TSA)

Package

0000000000000000h

29c04h

4

I2S x Link Vendor Specific Control (I2S1LVSCTL)

Package

00000000h

2a010h

2

I2S x PCM Stream Capabilities (I2S2PCMSCAP)

Package

0088h

2a014h

2

I2S x PCM Stream y Channel Count (I2S2PCMS0CHC)

Package

000Fh

2a016h

2

I2S x PCM Stream y Channel Map (I2S2PCMS0CM)

Package

00F0h

2a018h

2

I2S x PCM Stream y Channel Count (I2S2PCMS1CHC)

Package

000Fh

2a01ah

2

I2S x PCM Stream y Channel Map (I2S2PCMS1CM)

Package

00F0h

2a01ch

2

I2S x PCM Stream y Channel Count (I2S2PCMS2CHC)

Package

000Fh

2a01eh

2

I2S x PCM Stream y Channel Map (I2S2PCMS2CM)

Package

00F0h

2a020h

2

I2S x PCM Stream y Channel Count (I2S2PCMS3CHC)

Package

000Fh

2a022h

2

I2S x PCM Stream y Channel Map (I2S2PCMS3CM)

Package

00F0h

2a024h

2

I2S x PCM Stream y Channel Count (I2S2PCMS4CHC)

Package

000Fh

2a026h

2

I2S x PCM Stream y Channel Map (I2S2PCMS4CM)

Package

00F0h

2a028h

2

I2S x PCM Stream y Channel Count (I2S2PCMS5CHC)

Package

000Fh

2a02ah

2

I2S x PCM Stream y Channel Map (I2S2PCMS5CM)

Package

00F0h

2a02ch

2

I2S x PCM Stream y Channel Count (I2S2PCMS6CHC)

Package

000Fh

2a02eh

2

I2S x PCM Stream y Channel Map (I2S2PCMS6CM)

Package

00F0h

2a030h

2

I2S x PCM Stream y Channel Count (I2S2PCMS7CHC)

Package

000Fh

2a032h

2

I2S x PCM Stream y Channel Map (I2S2PCMS7CM)

Package

00F0h

2a034h

2

I2S x PCM Stream y Channel Count (I2S2PCMS8CHC)

Package

000Fh

2a036h

2

I2S x PCM Stream y Channel Map (I2S2PCMS8CM)

Package

00F0h

2a038h

2

I2S x PCM Stream y Channel Count (I2S2PCMS9CHC)

Package

000Fh

2a03ah

2

I2S x PCM Stream y Channel Map (I2S2PCMS9CM)

Package

00F0h

2a03ch

2

I2S x PCM Stream y Channel Count (I2S2PCMS10CHC)

Package

000Fh

2a03eh

2

I2S x PCM Stream y Channel Map (I2S2PCMS10CM)

Package

00F0h

2a040h

2

I2S x PCM Stream y Channel Count (I2S2PCMS11CHC)

Package

000Fh

2a042h

2

I2S x PCM Stream y Channel Map (I2S2PCMS11CM)

Package

00F0h

2a044h

2

I2S x PCM Stream y Channel Count (I2S2PCMS12CHC)

Package

000Fh

2a046h

2

I2S x PCM Stream y Channel Map (I2S2PCMS12CM)

Package

00F0h

2a048h

2

I2S x PCM Stream y Channel Count (I2S2PCMS13CHC)

Package

000Fh

2a04ah

2

I2S x PCM Stream y Channel Map (I2S2PCMS13CM)

Package

00F0h

2a04ch

2

I2S x PCM Stream y Channel Count (I2S2PCMS14CHC)

Package

000Fh

2a04eh

2

I2S x PCM Stream y Channel Map (I2S2PCMS14CM)

Package

00F0h

2a050h

2

I2S x PCM Stream y Channel Count (I2S2PCMS15CHC)

Package

000Fh

2a052h

2

I2S x PCM Stream y Channel Map (I2S2PCMS15CM)

Package

00F0h

2a100h

4

SSP x Control 0 (I2S2_​SSC0)

Package

80000070h

2a104h

4

SSP x Control 1 (I2S2_​SSC1)

Package

00000000h

2a108h

4

SSP x Status (I2S2_​SSS)

Package

00000000h

2a128h

4

SSP x Time Out (I2S2_​SSTO)

Package

00000000h

2a12ch

4

SSP x Programmable Serial Protocol (I2S2_​SSPSP)

Package

00000000h

2a138h

4

SSP x Time Slot Status (I2S2_​SSTSS)

Package

00000000h

2a140h

4

SSP x Command / Status 2 (I2S2_​SSC2)

Package

40000000h

2a144h

4

SSP x Programmable Serial Protocol 2 (I2S2_​SSPSP2)

Package

00000000h

2a14ch

4

SSP x IO Control (I2S2_​SSIOC)

Package

00000000h

2a150h

4

SSP x Global Frame Synchronization (I2S2_​SSGFS)

Package

00000000h

2a160h

4

SSP x Multi Input DMA y Control / Status (I2S2_​SSMID0CS)

Package

00000000h

2a164h

4

SSP x Multi Input DMA y Data (I2S2_​SSMID0D)

Package

00000000h

2a168h

8

SSP x Multi Input DMA y Time Slot Active (I2S2_​SSMID0TSA)

Package

0000000000000000h

2a170h

4

SSP x Multi Input DMA y Control / Status (I2S2_​SSMID1CS)

Package

00000000h

2a174h

4

SSP x Multi Input DMA y Data (I2S2_​SSMID1D)

Package

00000000h

2a178h

8

SSP x Multi Input DMA y Time Slot Active (I2S2_​SSMID1TSA)

Package

0000000000000000h

2a180h

4

SSP x Multi Input DMA y Control / Status (I2S2_​SSMID2CS)

Package

00000000h

2a184h

4

SSP x Multi Input DMA y Data (I2S2_​SSMID2D)

Package

00000000h

2a188h

8

SSP x Multi Input DMA y Time Slot Active (I2S2_​SSMID2TSA)

Package

0000000000000000h

2a190h

4

SSP x Multi Input DMA y Control / Status (I2S2_​SSMID3CS)

Package

00000000h

2a194h

4

SSP x Multi Input DMA y Data (I2S2_​SSMID3D)

Package

00000000h

2a198h

8

SSP x Multi Input DMA y Time Slot Active (I2S2_​SSMID3TSA)

Package

0000000000000000h

2a1a0h

4

SSP x Multi Input DMA y Control / Status (I2S2_​SSMID4CS)

Package

00000000h

2a1a4h

4

SSP x Multi Input DMA y Data (I2S2_​SSMID4D)

Package

00000000h

2a1a8h

8

SSP x Multi Input DMA y Time Slot Active (I2S2_​SSMID4TSA)

Package

0000000000000000h

2a1b0h

4

SSP x Multi Input DMA y Control / Status (I2S2_​SSMID5CS)

Package

00000000h

2a1b4h

4

SSP x Multi Input DMA y Data (I2S2_​SSMID5D)

Package

00000000h

2a1b8h

8

SSP x Multi Input DMA y Time Slot Active (I2S2_​SSMID5TSA)

Package

0000000000000000h

2a1c0h

4

SSP x Multi Input DMA y Control / Status (I2S2_​SSMID6CS)

Package

00000000h

2a1c4h

4

SSP x Multi Input DMA y Data (I2S2_​SSMID6D)

Package

00000000h

2a1c8h

8

SSP x Multi Input DMA y Time Slot Active (I2S2_​SSMID6TSA)

Package

0000000000000000h

2a1d0h

4

SSP x Multi Input DMA y Control / Status (I2S2_​SSMID7CS)

Package

00000000h

2a1d4h

4

SSP x Multi Input DMA y Data (I2S2_​SSMID7D)

Package

00000000h

2a1d8h

8

SSP x Multi Input DMA y Time Slot Active (I2S2_​SSMID7TSA)

Package

0000000000000000h

2a1e0h

4

SSP x Multi Output DMA y Control / Status (I2S2_​SSMOD0CS)

Package

04000000h

2a1e4h

4

SSP x Multi Output DMA y Data (I2S2_​SSMOD0D)

Package

00000000h

2a1e8h

8

SSP x Multi Output DMA y Time Slot Active (I2S2_​SSMOD0TSA)

Package

0000000000000000h

2a1f0h

4

SSP x Multi Output DMA y Control / Status (I2S2_​SSMOD1CS)

Package

04000000h

2a1f4h

4

SSP x Multi Output DMA y Data (I2S2_​SSMOD1D)

Package

00000000h

2a1f8h

8

SSP x Multi Output DMA y Time Slot Active (I2S2_​SSMOD1TSA)

Package

0000000000000000h

2a200h

4

SSP x Multi Output DMA y Control / Status (I2S2_​SSMOD2CS)

Package

04000000h

2a204h

4

SSP x Multi Output DMA y Data (I2S2_​SSMOD2D)

Package

00000000h

2a208h

8

SSP x Multi Output DMA y Time Slot Active (I2S2_​SSMOD2TSA)

Package

0000000000000000h

2a210h

4

SSP x Multi Output DMA y Control / Status (I2S2_​SSMOD3CS)

Package

04000000h

2a214h

4

SSP x Multi Output DMA y Data (I2S2_​SSMOD3D)

Package

00000000h

2a218h

8

SSP x Multi Output DMA y Time Slot Active (I2S2_​SSMOD3TSA)

Package

0000000000000000h

2a220h

4

SSP x Multi Output DMA y Control / Status (I2S2_​SSMOD4CS)

Package

04000000h

2a224h

4

SSP x Multi Output DMA y Data (I2S2_​SSMOD4D)

Package

00000000h

2a228h

8

SSP x Multi Output DMA y Time Slot Active (I2S2_​SSMOD4TSA)

Package

0000000000000000h

2a230h

4

SSP x Multi Output DMA y Control / Status (I2S2_​SSMOD5CS)

Package

04000000h

2a234h

4

SSP x Multi Output DMA y Data (I2S2_​SSMOD5D)

Package

00000000h

2a238h

8

SSP x Multi Output DMA y Time Slot Active (I2S2_​SSMOD5TSA)

Package

0000000000000000h

2a240h

4

SSP x Multi Output DMA y Control / Status (I2S2_​SSMOD6CS)

Package

04000000h

2a244h

4

SSP x Multi Output DMA y Data (I2S2_​SSMOD6D)

Package

00000000h

2a248h

8

SSP x Multi Output DMA y Time Slot Active (I2S2_​SSMOD6TSA)

Package

0000000000000000h

2a250h

4

SSP x Multi Output DMA y Control / Status (I2S2_​SSMOD7CS)

Package

04000000h

2a254h

4

SSP x Multi Output DMA y Data (I2S2_​SSMOD7D)

Package

00000000h

2a258h

8

SSP x Multi Output DMA y Time Slot Active (I2S2_​SSMOD7TSA)

Package

0000000000000000h

2ac04h

4

I2S x Link Vendor Specific Control (I2S2LVSCTL)

Package

00000000h

30000h

4

SoundWire x Link Extended Capability (SNDW0LECAP)

Package

00000000h

30010h

2

SoundWire x PCM Stream Capabilities (SNDW0PCMSCAP)

Package

0F00h

30014h

2

SoundWire PCM Stream y Channel Count (SNDW0PCMS0CHC)

Package

0007h

30016h

2

SoundWire x PCM Stream y Channel Map (SNDW0PCMS0CM)

Package

00F0h

30018h

2

SoundWire PCM Stream y Channel Count (SNDW0PCMS1CHC)

Package

0007h

3001ah

2

SoundWire x PCM Stream y Channel Map (SNDW0PCMS1CM)

Package

00F0h

3001ch

2

SoundWire PCM Stream y Channel Count (SNDW0PCMS2CHC)

Package

0007h

3001eh

2

SoundWire x PCM Stream y Channel Map (SNDW0PCMS2CM)

Package

00F0h

30020h

2

SoundWire PCM Stream y Channel Count (SNDW0PCMS3CHC)

Package

0007h

30022h

2

SoundWire x PCM Stream y Channel Map (SNDW0PCMS3CM)

Package

00F0h

30024h

2

SoundWire PCM Stream y Channel Count (SNDW0PCMS4CHC)

Package

0007h

30026h

2

SoundWire x PCM Stream y Channel Map (SNDW0PCMS4CM)

Package

00F0h

30028h

2

SoundWire PCM Stream y Channel Count (SNDW0PCMS5CHC)

Package

0007h

3002ah

2

SoundWire x PCM Stream y Channel Map (SNDW0PCMS5CM)

Package

00F0h

3002ch

2

SoundWire PCM Stream y Channel Count (SNDW0PCMS6CHC)

Package

0007h

3002eh

2

SoundWire x PCM Stream y Channel Map (SNDW0PCMS6CM)

Package

00F0h

30030h

2

SoundWire PCM Stream y Channel Count (SNDW0PCMS7CHC)

Package

0007h

30032h

2

SoundWire x PCM Stream y Channel Map (SNDW0PCMS7CM)

Package

00F0h

30034h

2

SoundWire PCM Stream y Channel Count (SNDW0PCMS8CHC)

Package

0007h

30036h

2

SoundWire x PCM Stream y Channel Map (SNDW0PCMS8CM)

Package

00F0h

30038h

2

SoundWire PCM Stream y Channel Count (SNDW0PCMS9CHC)

Package

0007h

3003ah

2

SoundWire x PCM Stream y Channel Map (SNDW0PCMS9CM)

Package

00F0h

3003ch

2

SoundWire PCM Stream y Channel Count (SNDW0PCMS10CHC)

Package

0007h

3003eh

2

SoundWire x PCM Stream y Channel Map (SNDW0PCMS10CM)

Package

00F0h

30040h

2

SoundWire PCM Stream y Channel Count (SNDW0PCMS11CHC)

Package

0007h

30042h

2

SoundWire x PCM Stream y Channel Map (SNDW0PCMS11CM)

Package

00F0h

30044h

2

SoundWire PCM Stream y Channel Count (SNDW0PCMS12CHC)

Package

0007h

30046h

2

SoundWire x PCM Stream y Channel Map (SNDW0PCMS12CM)

Package

00F0h

30048h

2

SoundWire PCM Stream y Channel Count (SNDW0PCMS13CHC)

Package

0007h

3004ah

2

SoundWire x PCM Stream y Channel Map (SNDW0PCMS13CM)

Package

00F0h

3004ch

2

SoundWire PCM Stream y Channel Count (SNDW0PCMS14CHC)

Package

0007h

3004eh

2

SoundWire x PCM Stream y Channel Map (SNDW0PCMS14CM)

Package

00F0h

30050h

2

SoundWire PCM Stream y Channel Count (SNDW0PCMS15CHC)

Package

0007h

30052h

2

SoundWire x PCM Stream y Channel Map (SNDW0PCMS15CM)

Package

00F0h

30100h

4

MCP Config (MCP_​0_​Config)

Package

00000000h

30104h

4

MCP Control (MCP_​0_​Control)

Package

00000000h

3010ch

4

MCP SSPStat (MCP_​0_​SSPStat)

Package

00000000h

30110h

4

MCP FrameShape (MCP_​0_​FrameShape)

Package

00000000h

30114h

4

MCP FrameShapeInit (MCP_​0_​FrameShapeInit)

Package

00000000h

30118h

4

MCP ConfigUpdate (MCP_​0_​ConfigUpdate)

Package

00000000h

30120h

4

MCP SSPCtrl (MCP_​0_​B0_​SSPCtrl)

Package

00000000h

30128h

4

MCP SSPCtrl (MCP_​0_​B1_​SSPCtrl)

Package

00000000h

30130h

4

MCP ClockCtrl (MCP_​0_​B0_​ClockCtrl)

Package

00000000h

30138h

4

MCP ClockCtrl (MCP_​0_​B1_​ClockCtrl)

Package

00000000h

30140h

4

MCP Stat (MCP_​0_​Stat)

Package

00000002h

30144h

4

MCP IntStat (MCP_​0_​IntStat)

Package

00000000h

30148h

4

MCP IntMask (MCP_​0_​IntMask)

Package

00000000h

30150h

4

MCP PeripheryStat (MCP_​0_​PeripheryStat)

Package

00000000h

30154h

4

MCP PeripheryIntStat0 (MCP_​0_​PeripheryIntStat0)

Package

00000000h

30158h

4

MCP PeripheryIntStat1 (MCP_​0_​PeripheryIntStat1)

Package

00000000h

3015ch

4

MCP PeripheryIntMask0 (MCP_​0_​PeripheryIntMask0)

Package

00000000h

30160h

4

MCP PeripheryIntMask1 (MCP_​0_​PeripheryIntMask1)

Package

00000000h

30164h

4

MCP PortIntStat (MCP_​0_​PortIntStat)

Package

00000000h

3016ch

4

MCP PDIStat (MCP_​0_​PDIStat)

Package

00000000h

30178h

4

MCP FIFOLevel (MCP_​0_​FIFOLevel)

Package

00000002h

3017ch

4

MCP FIFOStat (MCP_​0_​FIFOStat)

Package

00000800h

30200h

4

DP Config (DP_​0_​0_​B0_​Config)

Package

00000000h

30204h

4

DP ChannelEn (DP_​0_​0_​B0_​ChannelEn)

Package

00000000h

30208h

4

DP SampleCtrl (DP_​0_​0_​B0_​SampleCtrl)

Package

00000000h

3020ch

4

DP OffsetCtrl (DP_​0_​0_​B0_​OffsetCtrl)

Package

00000000h

30210h

4

DP HCtrl (DP_​0_​0_​B0_​HCtrl)

Package

00000000h

30214h

4

DP AsyncCtrl (DP_​0_​0_​B0_​AsyncCtrl)

Package

00000000h

30218h

4

DP Config (DP_​0_​0_​B1_​Config)

Package

00000000h

3021ch

4

DP ChannelEn (DP_​0_​0_​B1_​ChannelEn)

Package

00000000h

30220h

4

DP SampleCtrl (DP_​0_​0_​B1_​SampleCtrl)

Package

00000000h

30224h

4

DP OffsetCtrl (DP_​0_​0_​B1_​OffsetCtrl)

Package

00000000h

30228h

4

DP HCtrl (DP_​0_​0_​B1_​HCtrl)

Package

00000000h

3022ch

4

DP AsyncCtrl (DP_​0_​0_​B1_​AsyncCtrl)

Package

00000000h

30230h

4

DP Port Ctrl (DP_​0_​0_​Port_​Ctrl)

Package

00000000h

30280h

4

DP Config (DP_​0_​1_​B0_​Config)

Package

00000000h

30284h

4

DP ChannelEn (DP_​0_​1_​B0_​ChannelEn)

Package

00000000h

30288h

4

DP SampleCtrl (DP_​0_​1_​B0_​SampleCtrl)

Package

00000000h

3028ch

4

DP OffsetCtrl (DP_​0_​1_​B0_​OffsetCtrl)

Package

00000000h

30290h

4

DP HCtrl (DP_​0_​1_​B0_​HCtrl)

Package

00000000h

30294h

4

DP AsyncCtrl (DP_​0_​1_​B0_​AsyncCtrl)

Package

00000000h

30298h

4

DP Config (DP_​0_​1_​B1_​Config)

Package

00000000h

3029ch

4

DP ChannelEn (DP_​0_​1_​B1_​ChannelEn)

Package

00000000h

302a0h

4

DP SampleCtrl (DP_​0_​1_​B1_​SampleCtrl)

Package

00000000h

302a4h

4

DP OffsetCtrl (DP_​0_​1_​B1_​OffsetCtrl)

Package

00000000h

302a8h

4

DP HCtrl (DP_​0_​1_​B1_​HCtrl)

Package

00000000h

302ach

4

DP AsyncCtrl (DP_​0_​1_​B1_​AsyncCtrl)

Package

00000000h

302b0h

4

DP Port Ctrl (DP_​0_​1_​Port_​Ctrl)

Package

00000000h

30300h

4

DP Config (DP_​0_​2_​B0_​Config)

Package

00000000h

30304h

4

DP ChannelEn (DP_​0_​2_​B0_​ChannelEn)

Package

00000000h

30308h

4

DP SampleCtrl (DP_​0_​2_​B0_​SampleCtrl)

Package

00000000h

3030ch

4

DP OffsetCtrl (DP_​0_​2_​B0_​OffsetCtrl)

Package

00000000h

30310h

4

DP HCtrl (DP_​0_​2_​B0_​HCtrl)

Package

00000000h

30314h

4

DP AsyncCtrl (DP_​0_​2_​B0_​AsyncCtrl)

Package

00000000h

30318h

4

DP Config (DP_​0_​2_​B1_​Config)

Package

00000000h

3031ch

4

DP ChannelEn (DP_​0_​2_​B1_​ChannelEn)

Package

00000000h

30320h

4

DP SampleCtrl (DP_​0_​2_​B1_​SampleCtrl)

Package

00000000h

30324h

4

DP OffsetCtrl (DP_​0_​2_​B1_​OffsetCtrl)

Package

00000000h

30328h

4

DP HCtrl (DP_​0_​2_​B1_​HCtrl)

Package

00000000h

3032ch

4

DP AsyncCtrl (DP_​0_​2_​B1_​AsyncCtrl)

Package

00000000h

30330h

4

DP Port Ctrl (DP_​0_​2_​Port_​Ctrl)

Package

00000000h

30380h

4

DP Config (DP_​0_​3_​B0_​Config)

Package

00000000h

30384h

4

DP ChannelEn (DP_​0_​3_​B0_​ChannelEn)

Package

00000000h

30388h

4

DP SampleCtrl (DP_​0_​3_​B0_​SampleCtrl)

Package

00000000h

3038ch

4

DP OffsetCtrl (DP_​0_​3_​B0_​OffsetCtrl)

Package

00000000h

30390h

4

DP HCtrl (DP_​0_​3_​B0_​HCtrl)

Package

00000000h

30394h

4

DP AsyncCtrl (DP_​0_​3_​B0_​AsyncCtrl)

Package

00000000h

30398h

4

DP Config (DP_​0_​3_​B1_​Config)

Package

00000000h

3039ch

4

DP ChannelEn (DP_​0_​3_​B1_​ChannelEn)

Package

00000000h

303a0h

4

DP SampleCtrl (DP_​0_​3_​B1_​SampleCtrl)

Package

00000000h

303a4h

4

DP OffsetCtrl (DP_​0_​3_​B1_​OffsetCtrl)

Package

00000000h

303a8h

4

DP HCtrl (DP_​0_​3_​B1_​HCtrl)

Package

00000000h

303ach

4

DP AsyncCtrl (DP_​0_​3_​B1_​AsyncCtrl)

Package

00000000h

303b0h

4

DP Port Ctrl (DP_​0_​3_​Port_​Ctrl)

Package

00000000h

30400h

4

DP Config (DP_​0_​4_​B0_​Config)

Package

00000000h

30404h

4

DP ChannelEn (DP_​0_​4_​B0_​ChannelEn)

Package

00000000h

30408h

4

DP SampleCtrl (DP_​0_​4_​B0_​SampleCtrl)

Package

00000000h

3040ch

4

DP OffsetCtrl (DP_​0_​4_​B0_​OffsetCtrl)

Package

00000000h

30410h

4

DP HCtrl (DP_​0_​4_​B0_​HCtrl)

Package

00000000h

30414h

4

DP AsyncCtrl (DP_​0_​4_​B0_​AsyncCtrl)

Package

00000000h

30418h

4

DP Config (DP_​0_​4_​B1_​Config)

Package

00000000h

3041ch

4

DP ChannelEn (DP_​0_​4_​B1_​ChannelEn)

Package

00000000h

30420h

4

DP SampleCtrl (DP_​0_​4_​B1_​SampleCtrl)

Package

00000000h

30424h

4

DP OffsetCtrl (DP_​0_​4_​B1_​OffsetCtrl)

Package

00000000h

30428h

4

DP HCtrl (DP_​0_​4_​B1_​HCtrl)

Package

00000000h

3042ch

4

DP AsyncCtrl (DP_​0_​4_​B1_​AsyncCtrl)

Package

00000000h

30430h

4

DP Port Ctrl (DP_​0_​4_​Port_​Ctrl)

Package

00000000h

30480h

4

DP Config (DP_​0_​5_​B0_​Config)

Package

00000000h

30484h

4

DP ChannelEn (DP_​0_​5_​B0_​ChannelEn)

Package

00000000h

30488h

4

DP SampleCtrl (DP_​0_​5_​B0_​SampleCtrl)

Package

00000000h

3048ch

4

DP OffsetCtrl (DP_​0_​5_​B0_​OffsetCtrl)

Package

00000000h

30490h

4

DP HCtrl (DP_​0_​5_​B0_​HCtrl)

Package

00000000h

30494h

4

DP AsyncCtrl (DP_​0_​5_​B0_​AsyncCtrl)

Package

00000000h

30498h

4

DP Config (DP_​0_​5_​B1_​Config)

Package

00000000h

3049ch

4

DP ChannelEn (DP_​0_​5_​B1_​ChannelEn)

Package

00000000h

304a0h

4

DP SampleCtrl (DP_​0_​5_​B1_​SampleCtrl)

Package

00000000h

304a4h

4

DP OffsetCtrl (DP_​0_​5_​B1_​OffsetCtrl)

Package

00000000h

304a8h

4

DP HCtrl (DP_​0_​5_​B1_​HCtrl)

Package

00000000h

304ach

4

DP AsyncCtrl (DP_​0_​5_​B1_​AsyncCtrl)

Package

00000000h

304b0h

4

DP Port Ctrl (DP_​0_​5_​Port_​Ctrl)

Package

00000000h

30500h

4

DP Config (DP_​0_​6_​B0_​Config)

Package

00000000h

30504h

4

DP ChannelEn (DP_​0_​6_​B0_​ChannelEn)

Package

00000000h

30508h

4

DP SampleCtrl (DP_​0_​6_​B0_​SampleCtrl)

Package

00000000h

3050ch

4

DP OffsetCtrl (DP_​0_​6_​B0_​OffsetCtrl)

Package

00000000h

30510h

4

DP HCtrl (DP_​0_​6_​B0_​HCtrl)

Package

00000000h

30514h

4

DP AsyncCtrl (DP_​0_​6_​B0_​AsyncCtrl)

Package

00000000h

30518h

4

DP Config (DP_​0_​6_​B1_​Config)

Package

00000000h

3051ch

4

DP ChannelEn (DP_​0_​6_​B1_​ChannelEn)

Package

00000000h

30520h

4

DP SampleCtrl (DP_​0_​6_​B1_​SampleCtrl)

Package

00000000h

30524h

4

DP OffsetCtrl (DP_​0_​6_​B1_​OffsetCtrl)

Package

00000000h

30528h

4

DP HCtrl (DP_​0_​6_​B1_​HCtrl)

Package

00000000h

3052ch

4

DP AsyncCtrl (DP_​0_​6_​B1_​AsyncCtrl)

Package

00000000h

30530h

4

DP Port Ctrl (DP_​0_​6_​Port_​Ctrl)

Package

00000000h

30580h

4

DP Config (DP_​0_​7_​B0_​Config)

Package

00000000h

30584h

4

DP ChannelEn (DP_​0_​7_​B0_​ChannelEn)

Package

00000000h

30588h

4

DP SampleCtrl (DP_​0_​7_​B0_​SampleCtrl)

Package

00000000h

3058ch

4

DP OffsetCtrl (DP_​0_​7_​B0_​OffsetCtrl)

Package

00000000h

30590h

4

DP HCtrl (DP_​0_​7_​B0_​HCtrl)

Package

00000000h

30594h

4

DP AsyncCtrl (DP_​0_​7_​B0_​AsyncCtrl)

Package

00000000h

30598h

4

DP Config (DP_​0_​7_​B1_​Config)

Package

00000000h

3059ch

4

DP ChannelEn (DP_​0_​7_​B1_​ChannelEn)

Package

00000000h

305a0h

4

DP SampleCtrl (DP_​0_​7_​B1_​SampleCtrl)

Package

00000000h

305a4h

4

DP OffsetCtrl (DP_​0_​7_​B1_​OffsetCtrl)

Package

00000000h

305a8h

4

DP HCtrl (DP_​0_​7_​B1_​HCtrl)

Package

00000000h

305ach

4

DP AsyncCtrl (DP_​0_​7_​B1_​AsyncCtrl)

Package

00000000h

305b0h

4

DP Port Ctrl (DP_​0_​7_​Port_​Ctrl)

Package

00000000h

30600h

4

DP Config (DP_​0_​8_​B0_​Config)

Package

00000000h

30604h

4

DP ChannelEn (DP_​0_​8_​B0_​ChannelEn)

Package

00000000h

30608h

4

DP SampleCtrl (DP_​0_​8_​B0_​SampleCtrl)

Package

00000000h

3060ch

4

DP OffsetCtrl (DP_​0_​8_​B0_​OffsetCtrl)

Package

00000000h

30610h

4

DP HCtrl (DP_​0_​8_​B0_​HCtrl)

Package

00000000h

30614h

4

DP AsyncCtrl (DP_​0_​8_​B0_​AsyncCtrl)

Package

00000000h

30618h

4

DP Config (DP_​0_​8_​B1_​Config)

Package

00000000h

3061ch

4

DP ChannelEn (DP_​0_​8_​B1_​ChannelEn)

Package

00000000h

30620h

4

DP SampleCtrl (DP_​0_​8_​B1_​SampleCtrl)

Package

00000000h

30624h

4

DP OffsetCtrl (DP_​0_​8_​B1_​OffsetCtrl)

Package

00000000h

30628h

4

DP HCtrl (DP_​0_​8_​B1_​HCtrl)

Package

00000000h

3062ch

4

DP AsyncCtrl (DP_​0_​8_​B1_​AsyncCtrl)

Package

00000000h

30630h

4

DP Port Ctrl (DP_​0_​8_​Port_​Ctrl)

Package

00000000h

30680h

4

DP Config (DP_​0_​9_​B0_​Config)

Package

00000000h

30684h

4

DP ChannelEn (DP_​0_​9_​B0_​ChannelEn)

Package

00000000h

30688h

4

DP SampleCtrl (DP_​0_​9_​B0_​SampleCtrl)

Package

00000000h

3068ch

4

DP OffsetCtrl (DP_​0_​9_​B0_​OffsetCtrl)

Package

00000000h

30690h

4

DP HCtrl (DP_​0_​9_​B0_​HCtrl)

Package

00000000h

30694h

4

DP AsyncCtrl (DP_​0_​9_​B0_​AsyncCtrl)

Package

00000000h

30698h

4

DP Config (DP_​0_​9_​B1_​Config)

Package

00000000h

3069ch

4

DP ChannelEn (DP_​0_​9_​B1_​ChannelEn)

Package

00000000h

306a0h

4

DP SampleCtrl (DP_​0_​9_​B1_​SampleCtrl)

Package

00000000h

306a4h

4

DP OffsetCtrl (DP_​0_​9_​B1_​OffsetCtrl)

Package

00000000h

306a8h

4

DP HCtrl (DP_​0_​9_​B1_​HCtrl)

Package

00000000h

306ach

4

DP AsyncCtrl (DP_​0_​9_​B1_​AsyncCtrl)

Package

00000000h

306b0h

4

DP Port Ctrl (DP_​0_​9_​Port_​Ctrl)

Package

00000000h

30700h

4

DP Config (DP_​0_​10_​B0_​Config)

Package

00000000h

30704h

4

DP ChannelEn (DP_​0_​10_​B0_​ChannelEn)

Package

00000000h

30708h

4

DP SampleCtrl (DP_​0_​10_​B0_​SampleCtrl)

Package

00000000h

3070ch

4

DP OffsetCtrl (DP_​0_​10_​B0_​OffsetCtrl)

Package

00000000h

30710h

4

DP HCtrl (DP_​0_​10_​B0_​HCtrl)

Package

00000000h

30714h

4

DP AsyncCtrl (DP_​0_​10_​B0_​AsyncCtrl)

Package

00000000h

30718h

4

DP Config (DP_​0_​10_​B1_​Config)

Package

00000000h

3071ch

4

DP ChannelEn (DP_​0_​10_​B1_​ChannelEn)

Package

00000000h

30720h

4

DP SampleCtrl (DP_​0_​10_​B1_​SampleCtrl)

Package

00000000h

30724h

4

DP OffsetCtrl (DP_​0_​10_​B1_​OffsetCtrl)

Package

00000000h

30728h

4

DP HCtrl (DP_​0_​10_​B1_​HCtrl)

Package

00000000h

3072ch

4

DP AsyncCtrl (DP_​0_​10_​B1_​AsyncCtrl)

Package

00000000h

30730h

4

DP Port Ctrl (DP_​0_​10_​Port_​Ctrl)

Package

00000000h

30780h

4

DP Config (DP_​0_​11_​B0_​Config)

Package

00000000h

30784h

4

DP ChannelEn (DP_​0_​11_​B0_​ChannelEn)

Package

00000000h

30788h

4

DP SampleCtrl (DP_​0_​11_​B0_​SampleCtrl)

Package

00000000h

3078ch

4

DP OffsetCtrl (DP_​0_​11_​B0_​OffsetCtrl)

Package

00000000h

30790h

4

DP HCtrl (DP_​0_​11_​B0_​HCtrl)

Package

00000000h

30794h

4

DP AsyncCtrl (DP_​0_​11_​B0_​AsyncCtrl)

Package

00000000h

30798h

4

DP Config (DP_​0_​11_​B1_​Config)

Package

00000000h

3079ch

4

DP ChannelEn (DP_​0_​11_​B1_​ChannelEn)

Package

00000000h

307a0h

4

DP SampleCtrl (DP_​0_​11_​B1_​SampleCtrl)

Package

00000000h

307a4h

4

DP OffsetCtrl (DP_​0_​11_​B1_​OffsetCtrl)

Package

00000000h

307a8h

4

DP HCtrl (DP_​0_​11_​B1_​HCtrl)

Package

00000000h

307ach

4

DP AsyncCtrl (DP_​0_​11_​B1_​AsyncCtrl)

Package

00000000h

307b0h

4

DP Port Ctrl (DP_​0_​11_​Port_​Ctrl)

Package

00000000h

30800h

4

DP Config (DP_​0_​12_​B0_​Config)

Package

00000000h

30804h

4

DP ChannelEn (DP_​0_​12_​B0_​ChannelEn)

Package

00000000h

30808h

4

DP SampleCtrl (DP_​0_​12_​B0_​SampleCtrl)

Package

00000000h

3080ch

4

DP OffsetCtrl (DP_​0_​12_​B0_​OffsetCtrl)

Package

00000000h

30810h

4

DP HCtrl (DP_​0_​12_​B0_​HCtrl)

Package

00000000h

30814h

4

DP AsyncCtrl (DP_​0_​12_​B0_​AsyncCtrl)

Package

00000000h

30818h

4

DP Config (DP_​0_​12_​B1_​Config)

Package

00000000h

3081ch

4

DP ChannelEn (DP_​0_​12_​B1_​ChannelEn)

Package

00000000h

30820h

4

DP SampleCtrl (DP_​0_​12_​B1_​SampleCtrl)

Package

00000000h

30824h

4

DP OffsetCtrl (DP_​0_​12_​B1_​OffsetCtrl)

Package

00000000h

30828h

4

DP HCtrl (DP_​0_​12_​B1_​HCtrl)

Package

00000000h

3082ch

4

DP AsyncCtrl (DP_​0_​12_​B1_​AsyncCtrl)

Package

00000000h

30830h

4

DP Port Ctrl (DP_​0_​12_​Port_​Ctrl)

Package

00000000h

30880h

4

DP Config (DP_​0_​13_​B0_​Config)

Package

00000000h

30884h

4

DP ChannelEn (DP_​0_​13_​B0_​ChannelEn)

Package

00000000h

30888h

4

DP SampleCtrl (DP_​0_​13_​B0_​SampleCtrl)

Package

00000000h

3088ch

4

DP OffsetCtrl (DP_​0_​13_​B0_​OffsetCtrl)

Package

00000000h

30890h

4

DP HCtrl (DP_​0_​13_​B0_​HCtrl)

Package

00000000h

30894h

4

DP AsyncCtrl (DP_​0_​13_​B0_​AsyncCtrl)

Package

00000000h

30898h

4

DP Config (DP_​0_​13_​B1_​Config)

Package

00000000h

3089ch

4

DP ChannelEn (DP_​0_​13_​B1_​ChannelEn)

Package

00000000h

308a0h

4

DP SampleCtrl (DP_​0_​13_​B1_​SampleCtrl)

Package

00000000h

308a4h

4

DP OffsetCtrl (DP_​0_​13_​B1_​OffsetCtrl)

Package

00000000h

308a8h

4

DP HCtrl (DP_​0_​13_​B1_​HCtrl)

Package

00000000h

308ach

4

DP AsyncCtrl (DP_​0_​13_​B1_​AsyncCtrl)

Package

00000000h

308b0h

4

DP Port Ctrl (DP_​0_​13_​Port_​Ctrl)

Package

00000000h

30900h

4

DP Config (DP_​0_​14_​B0_​Config)

Package

00000000h

30904h

4

DP ChannelEn (DP_​0_​14_​B0_​ChannelEn)

Package

00000000h

30908h

4

DP SampleCtrl (DP_​0_​14_​B0_​SampleCtrl)

Package

00000000h

3090ch

4

DP OffsetCtrl (DP_​0_​14_​B0_​OffsetCtrl)

Package

00000000h

30910h

4

DP HCtrl (DP_​0_​14_​B0_​HCtrl)

Package

00000000h

30914h

4

DP AsyncCtrl (DP_​0_​14_​B0_​AsyncCtrl)

Package

00000000h

30918h

4

DP Config (DP_​0_​14_​B1_​Config)

Package

00000000h

3091ch

4

DP ChannelEn (DP_​0_​14_​B1_​ChannelEn)

Package

00000000h

30920h

4

DP SampleCtrl (DP_​0_​14_​B1_​SampleCtrl)

Package

00000000h

30924h

4

DP OffsetCtrl (DP_​0_​14_​B1_​OffsetCtrl)

Package

00000000h

30928h

4

DP HCtrl (DP_​0_​14_​B1_​HCtrl)

Package

00000000h

3092ch

4

DP AsyncCtrl (DP_​0_​14_​B1_​AsyncCtrl)

Package

00000000h

30930h

4

DP Port Ctrl (DP_​0_​14_​Port_​Ctrl)

Package

00000000h

31200h

4

PDI Config (PDI_​0_​0_​Config)

Package

00000000h

31210h

4

PDI Config (PDI_​0_​1_​Config)

Package

00000000h

31220h

4

PDI Config (PDI_​0_​2_​Config)

Package

00000000h

31230h

4

PDI Config (PDI_​0_​3_​Config)

Package

00000000h

31240h

4

PDI Config (PDI_​0_​4_​Config)

Package

00000000h

31250h

4

PDI Config (PDI_​0_​5_​Config)

Package

00000000h

31260h

4

PDI Config (PDI_​0_​6_​Config)

Package

00000000h

31270h

4

PDI Config (PDI_​0_​7_​Config)

Package

00000000h

31280h

4

PDI Config (PDI_​0_​8_​Config)

Package

00000000h

31290h

4

PDI Config (PDI_​0_​9_​Config)

Package

00000000h

312a0h

4

PDI Config (PDI_​0_​10_​Config)

Package

00000000h

312b0h

4

PDI Config (PDI_​0_​11_​Config)

Package

00000000h

312c0h

4

PDI Config (PDI_​0_​12_​Config)

Package

00000000h

312d0h

4

PDI Config (PDI_​0_​13_​Config)

Package

00000000h

312e0h

4

PDI Config (PDI_​0_​14_​Config)

Package

00000000h

312f0h

4

PDI Config (PDI_​0_​15_​Config)

Package

00000000h

34100h

4

IP MCP Config (IP_​MCP_​0_​Config)

Package

001F0005h

34104h

4

IP MCP Control (IP_​MCP_​0_​Control)

Package

00000000h

34108h

4

IP MCP CmdCtrl (IP_​MCP_​0_​CmdCtrl)

Package

00000000h

3411ch

4

IP MCP PHYCtrl (IP_​MCP_​0_​PHYCtrl)

Package

00000000h

34130h

4

IP MCP B0_​ClockCtrl (IP_​MCP_​0_​B0_​ClockCtrl)

Package

00000000h

34140h

4

IP MCP Stat (IP_​MCP_​0_​Stat)

Package

00000000h

3414ch

4

IP MCP IntSet (IP_​MCP_​0_​IntSet)

Package

00000000h

34180h

4

IP MCP Command (IP_​MCP_​0_​Command)

Package

00000000h

36004h

4

SoundWire x Link Vendor Specific Control (SNDW0LVSCTL)

Package

00000000h

36008h

2

SoundWire x Wake Enable (SNDW0WAKEEN)

Package

0000h

3600ah

2

SoundWire x Wake Status (SNDW0WAKESTS)

Package

0000h

3600ch

2

SoundWire x I/O Control (SNDW0IOCTL)

Package

0004h

3600eh

2

SoundWire x AC Timing Control (SNDW0ACTMCTL)

Package

003Ah

36010h

2

SoundWire x Microphone Privacy Control & Status (SNDW0PVCCS)

Package

0000h

38000h

4

SoundWire x Link Extended Capability (SNDW1LECAP)

Package

00000000h

38010h

2

SoundWire x PCM Stream Capabilities (SNDW1PCMSCAP)

Package

0F00h

38014h

2

SoundWire PCM Stream y Channel Count (SNDW1PCMS0CHC)

Package

0007h

38016h

2

SoundWire x PCM Stream y Channel Map (SNDW1PCMS0CM)

Package

00F0h

38018h

2

SoundWire PCM Stream y Channel Count (SNDW1PCMS1CHC)

Package

0007h

3801ah

2

SoundWire x PCM Stream y Channel Map (SNDW1PCMS1CM)

Package

00F0h

3801ch

2

SoundWire PCM Stream y Channel Count (SNDW1PCMS2CHC)

Package

0007h

3801eh

2

SoundWire x PCM Stream y Channel Map (SNDW1PCMS2CM)

Package

00F0h

38020h

2

SoundWire PCM Stream y Channel Count (SNDW1PCMS3CHC)

Package

0007h

38022h

2

SoundWire x PCM Stream y Channel Map (SNDW1PCMS3CM)

Package

00F0h

38024h

2

SoundWire PCM Stream y Channel Count (SNDW1PCMS4CHC)

Package

0007h

38026h

2

SoundWire x PCM Stream y Channel Map (SNDW1PCMS4CM)

Package

00F0h

38028h

2

SoundWire PCM Stream y Channel Count (SNDW1PCMS5CHC)

Package

0007h

3802ah

2

SoundWire x PCM Stream y Channel Map (SNDW1PCMS5CM)

Package

00F0h

3802ch

2

SoundWire PCM Stream y Channel Count (SNDW1PCMS6CHC)

Package

0007h

3802eh

2

SoundWire x PCM Stream y Channel Map (SNDW1PCMS6CM)

Package

00F0h

38030h

2

SoundWire PCM Stream y Channel Count (SNDW1PCMS7CHC)

Package

0007h

38032h

2

SoundWire x PCM Stream y Channel Map (SNDW1PCMS7CM)

Package

00F0h

38034h

2

SoundWire PCM Stream y Channel Count (SNDW1PCMS8CHC)

Package

0007h

38036h

2

SoundWire x PCM Stream y Channel Map (SNDW1PCMS8CM)

Package

00F0h

38038h

2

SoundWire PCM Stream y Channel Count (SNDW1PCMS9CHC)

Package

0007h

3803ah

2

SoundWire x PCM Stream y Channel Map (SNDW1PCMS9CM)

Package

00F0h

3803ch

2

SoundWire PCM Stream y Channel Count (SNDW1PCMS10CHC)

Package

0007h

3803eh

2

SoundWire x PCM Stream y Channel Map (SNDW1PCMS10CM)

Package

00F0h

38040h

2

SoundWire PCM Stream y Channel Count (SNDW1PCMS11CHC)

Package

0007h

38042h

2

SoundWire x PCM Stream y Channel Map (SNDW1PCMS11CM)

Package

00F0h

38044h

2

SoundWire PCM Stream y Channel Count (SNDW1PCMS12CHC)

Package

0007h

38046h

2

SoundWire x PCM Stream y Channel Map (SNDW1PCMS12CM)

Package

00F0h

38048h

2

SoundWire PCM Stream y Channel Count (SNDW1PCMS13CHC)

Package

0007h

3804ah

2

SoundWire x PCM Stream y Channel Map (SNDW1PCMS13CM)

Package

00F0h

3804ch

2

SoundWire PCM Stream y Channel Count (SNDW1PCMS14CHC)

Package

0007h

3804eh

2

SoundWire x PCM Stream y Channel Map (SNDW1PCMS14CM)

Package

00F0h

38050h

2

SoundWire PCM Stream y Channel Count (SNDW1PCMS15CHC)

Package

0007h

38052h

2

SoundWire x PCM Stream y Channel Map (SNDW1PCMS15CM)

Package

00F0h

38100h

4

MCP Config (MCP_​1_​Config)

Package

00000000h

38104h

4

MCP Control (MCP_​1_​Control)

Package

00000000h

3810ch

4

MCP SSPStat (MCP_​1_​SSPStat)

Package

00000000h

38110h

4

MCP FrameShape (MCP_​1_​FrameShape)

Package

00000000h

38114h

4

MCP FrameShapeInit (MCP_​1_​FrameShapeInit)

Package

00000000h

38118h

4

MCP ConfigUpdate (MCP_​1_​ConfigUpdate)

Package

00000000h

38120h

4

MCP SSPCtrl (MCP_​1_​B0_​SSPCtrl)

Package

00000000h

38128h

4

MCP SSPCtrl (MCP_​1_​B1_​SSPCtrl)

Package

00000000h

38130h

4

MCP ClockCtrl (MCP_​1_​B0_​ClockCtrl)

Package

00000000h

38138h

4

MCP ClockCtrl (MCP_​1_​B1_​ClockCtrl)

Package

00000000h

38140h

4

MCP Stat (MCP_​1_​Stat)

Package

00000002h

38144h

4

MCP IntStat (MCP_​1_​IntStat)

Package

00000000h

38148h

4

MCP IntMask (MCP_​1_​IntMask)

Package

00000000h

38150h

4

MCP PeripheryStat (MCP_​1_​PeripheryStat)

Package

00000000h

38154h

4

MCP PeripheryIntStat0 (MCP_​1_​PeripheryIntStat0)

Package

00000000h

38158h

4

MCP PeripheryIntStat1 (MCP_​1_​PeripheryIntStat1)

Package

00000000h

3815ch

4

MCP PeripheryIntMask0 (MCP_​1_​PeripheryIntMask0)

Package

00000000h

38160h

4

MCP PeripheryIntMask1 (MCP_​1_​PeripheryIntMask1)

Package

00000000h

38164h

4

MCP PortIntStat (MCP_​1_​PortIntStat)

Package

00000000h

3816ch

4

MCP PDIStat (MCP_​1_​PDIStat)

Package

00000000h

38178h

4

MCP FIFOLevel (MCP_​1_​FIFOLevel)

Package

00000002h

3817ch

4

MCP FIFOStat (MCP_​1_​FIFOStat)

Package

00000800h

38200h

4

DP Config (DP_​1_​0_​B0_​Config)

Package

00000000h

38204h

4

DP ChannelEn (DP_​1_​0_​B0_​ChannelEn)

Package

00000000h

38208h

4

DP SampleCtrl (DP_​1_​0_​B0_​SampleCtrl)

Package

00000000h

3820ch

4

DP OffsetCtrl (DP_​1_​0_​B0_​OffsetCtrl)

Package

00000000h

38210h

4

DP HCtrl (DP_​1_​0_​B0_​HCtrl)

Package

00000000h

38214h

4

DP AsyncCtrl (DP_​1_​0_​B0_​AsyncCtrl)

Package

00000000h

38218h

4

DP Config (DP_​1_​0_​B1_​Config)

Package

00000000h

3821ch

4

DP ChannelEn (DP_​1_​0_​B1_​ChannelEn)

Package

00000000h

38220h

4

DP SampleCtrl (DP_​1_​0_​B1_​SampleCtrl)

Package

00000000h

38224h

4

DP OffsetCtrl (DP_​1_​0_​B1_​OffsetCtrl)

Package

00000000h

38228h

4

DP HCtrl (DP_​1_​0_​B1_​HCtrl)

Package

00000000h

3822ch

4

DP AsyncCtrl (DP_​1_​0_​B1_​AsyncCtrl)

Package

00000000h

38230h

4

DP Port Ctrl (DP_​1_​0_​Port_​Ctrl)

Package

00000000h

38280h

4

DP Config (DP_​1_​1_​B0_​Config)

Package

00000000h

38284h

4

DP ChannelEn (DP_​1_​1_​B0_​ChannelEn)

Package

00000000h

38288h

4

DP SampleCtrl (DP_​1_​1_​B0_​SampleCtrl)

Package

00000000h

3828ch

4

DP OffsetCtrl (DP_​1_​1_​B0_​OffsetCtrl)

Package

00000000h

38290h

4

DP HCtrl (DP_​1_​1_​B0_​HCtrl)

Package

00000000h

38294h

4

DP AsyncCtrl (DP_​1_​1_​B0_​AsyncCtrl)

Package

00000000h

38298h

4

DP Config (DP_​1_​1_​B1_​Config)

Package

00000000h

3829ch

4

DP ChannelEn (DP_​1_​1_​B1_​ChannelEn)

Package

00000000h

382a0h

4

DP SampleCtrl (DP_​1_​1_​B1_​SampleCtrl)

Package

00000000h

382a4h

4

DP OffsetCtrl (DP_​1_​1_​B1_​OffsetCtrl)

Package

00000000h

382a8h

4

DP HCtrl (DP_​1_​1_​B1_​HCtrl)

Package

00000000h

382ach

4

DP AsyncCtrl (DP_​1_​1_​B1_​AsyncCtrl)

Package

00000000h

382b0h

4

DP Port Ctrl (DP_​1_​1_​Port_​Ctrl)

Package

00000000h

38300h

4

DP Config (DP_​1_​2_​B0_​Config)

Package

00000000h

38304h

4

DP ChannelEn (DP_​1_​2_​B0_​ChannelEn)

Package

00000000h

38308h

4

DP SampleCtrl (DP_​1_​2_​B0_​SampleCtrl)

Package

00000000h

3830ch

4

DP OffsetCtrl (DP_​1_​2_​B0_​OffsetCtrl)

Package

00000000h

38310h

4

DP HCtrl (DP_​1_​2_​B0_​HCtrl)

Package

00000000h

38314h

4

DP AsyncCtrl (DP_​1_​2_​B0_​AsyncCtrl)

Package

00000000h

38318h

4

DP Config (DP_​1_​2_​B1_​Config)

Package

00000000h

3831ch

4

DP ChannelEn (DP_​1_​2_​B1_​ChannelEn)

Package

00000000h

38320h

4

DP SampleCtrl (DP_​1_​2_​B1_​SampleCtrl)

Package

00000000h

38324h

4

DP OffsetCtrl (DP_​1_​2_​B1_​OffsetCtrl)

Package

00000000h

38328h

4

DP HCtrl (DP_​1_​2_​B1_​HCtrl)

Package

00000000h

3832ch

4

DP AsyncCtrl (DP_​1_​2_​B1_​AsyncCtrl)

Package

00000000h

38330h

4

DP Port Ctrl (DP_​1_​2_​Port_​Ctrl)

Package

00000000h

38380h

4

DP Config (DP_​1_​3_​B0_​Config)

Package

00000000h

38384h

4

DP ChannelEn (DP_​1_​3_​B0_​ChannelEn)

Package

00000000h

38388h

4

DP SampleCtrl (DP_​1_​3_​B0_​SampleCtrl)

Package

00000000h

3838ch

4

DP OffsetCtrl (DP_​1_​3_​B0_​OffsetCtrl)

Package

00000000h

38390h

4

DP HCtrl (DP_​1_​3_​B0_​HCtrl)

Package

00000000h

38394h

4

DP AsyncCtrl (DP_​1_​3_​B0_​AsyncCtrl)

Package

00000000h

38398h

4

DP Config (DP_​1_​3_​B1_​Config)

Package

00000000h

3839ch

4

DP ChannelEn (DP_​1_​3_​B1_​ChannelEn)

Package

00000000h

383a0h

4

DP SampleCtrl (DP_​1_​3_​B1_​SampleCtrl)

Package

00000000h

383a4h

4

DP OffsetCtrl (DP_​1_​3_​B1_​OffsetCtrl)

Package

00000000h

383a8h

4

DP HCtrl (DP_​1_​3_​B1_​HCtrl)

Package

00000000h

383ach

4

DP AsyncCtrl (DP_​1_​3_​B1_​AsyncCtrl)

Package

00000000h

383b0h

4

DP Port Ctrl (DP_​1_​3_​Port_​Ctrl)

Package

00000000h

38400h

4

DP Config (DP_​1_​4_​B0_​Config)

Package

00000000h

38404h

4

DP ChannelEn (DP_​1_​4_​B0_​ChannelEn)

Package

00000000h

38408h

4

DP SampleCtrl (DP_​1_​4_​B0_​SampleCtrl)

Package

00000000h

3840ch

4

DP OffsetCtrl (DP_​1_​4_​B0_​OffsetCtrl)

Package

00000000h

38410h

4

DP HCtrl (DP_​1_​4_​B0_​HCtrl)

Package

00000000h

38414h

4

DP AsyncCtrl (DP_​1_​4_​B0_​AsyncCtrl)

Package

00000000h

38418h

4

DP Config (DP_​1_​4_​B1_​Config)

Package

00000000h

3841ch

4

DP ChannelEn (DP_​1_​4_​B1_​ChannelEn)

Package

00000000h

38420h

4

DP SampleCtrl (DP_​1_​4_​B1_​SampleCtrl)

Package

00000000h

38424h

4

DP OffsetCtrl (DP_​1_​4_​B1_​OffsetCtrl)

Package

00000000h

38428h

4

DP HCtrl (DP_​1_​4_​B1_​HCtrl)

Package

00000000h

3842ch

4

DP AsyncCtrl (DP_​1_​4_​B1_​AsyncCtrl)

Package

00000000h

38430h

4

DP Port Ctrl (DP_​1_​4_​Port_​Ctrl)

Package

00000000h

38480h

4

DP Config (DP_​1_​5_​B0_​Config)

Package

00000000h

38484h

4

DP ChannelEn (DP_​1_​5_​B0_​ChannelEn)

Package

00000000h

38488h

4

DP SampleCtrl (DP_​1_​5_​B0_​SampleCtrl)

Package

00000000h

3848ch

4

DP OffsetCtrl (DP_​1_​5_​B0_​OffsetCtrl)

Package

00000000h

38490h

4

DP HCtrl (DP_​1_​5_​B0_​HCtrl)

Package

00000000h

38494h

4

DP AsyncCtrl (DP_​1_​5_​B0_​AsyncCtrl)

Package

00000000h

38498h

4

DP Config (DP_​1_​5_​B1_​Config)

Package

00000000h

3849ch

4

DP ChannelEn (DP_​1_​5_​B1_​ChannelEn)

Package

00000000h

384a0h

4

DP SampleCtrl (DP_​1_​5_​B1_​SampleCtrl)

Package

00000000h

384a4h

4

DP OffsetCtrl (DP_​1_​5_​B1_​OffsetCtrl)

Package

00000000h

384a8h

4

DP HCtrl (DP_​1_​5_​B1_​HCtrl)

Package

00000000h

384ach

4

DP AsyncCtrl (DP_​1_​5_​B1_​AsyncCtrl)

Package

00000000h

384b0h

4

DP Port Ctrl (DP_​1_​5_​Port_​Ctrl)

Package

00000000h

38500h

4

DP Config (DP_​1_​6_​B0_​Config)

Package

00000000h

38504h

4

DP ChannelEn (DP_​1_​6_​B0_​ChannelEn)

Package

00000000h

38508h

4

DP SampleCtrl (DP_​1_​6_​B0_​SampleCtrl)

Package

00000000h

3850ch

4

DP OffsetCtrl (DP_​1_​6_​B0_​OffsetCtrl)

Package

00000000h

38510h

4

DP HCtrl (DP_​1_​6_​B0_​HCtrl)

Package

00000000h

38514h

4

DP AsyncCtrl (DP_​1_​6_​B0_​AsyncCtrl)

Package

00000000h

38518h

4

DP Config (DP_​1_​6_​B1_​Config)

Package

00000000h

3851ch

4

DP ChannelEn (DP_​1_​6_​B1_​ChannelEn)

Package

00000000h

38520h

4

DP SampleCtrl (DP_​1_​6_​B1_​SampleCtrl)

Package

00000000h

38524h

4

DP OffsetCtrl (DP_​1_​6_​B1_​OffsetCtrl)

Package

00000000h

38528h

4

DP HCtrl (DP_​1_​6_​B1_​HCtrl)

Package

00000000h

3852ch

4

DP AsyncCtrl (DP_​1_​6_​B1_​AsyncCtrl)

Package

00000000h

38530h

4

DP Port Ctrl (DP_​1_​6_​Port_​Ctrl)

Package

00000000h

38580h

4

DP Config (DP_​1_​7_​B0_​Config)

Package

00000000h

38584h

4

DP ChannelEn (DP_​1_​7_​B0_​ChannelEn)

Package

00000000h

38588h

4

DP SampleCtrl (DP_​1_​7_​B0_​SampleCtrl)

Package

00000000h

3858ch

4

DP OffsetCtrl (DP_​1_​7_​B0_​OffsetCtrl)

Package

00000000h

38590h

4

DP HCtrl (DP_​1_​7_​B0_​HCtrl)

Package

00000000h

38594h

4

DP AsyncCtrl (DP_​1_​7_​B0_​AsyncCtrl)

Package

00000000h

38598h

4

DP Config (DP_​1_​7_​B1_​Config)

Package

00000000h

3859ch

4

DP ChannelEn (DP_​1_​7_​B1_​ChannelEn)

Package

00000000h

385a0h

4

DP SampleCtrl (DP_​1_​7_​B1_​SampleCtrl)

Package

00000000h

385a4h

4

DP OffsetCtrl (DP_​1_​7_​B1_​OffsetCtrl)

Package

00000000h

385a8h

4

DP HCtrl (DP_​1_​7_​B1_​HCtrl)

Package

00000000h

385ach

4

DP AsyncCtrl (DP_​1_​7_​B1_​AsyncCtrl)

Package

00000000h

385b0h

4

DP Port Ctrl (DP_​1_​7_​Port_​Ctrl)

Package

00000000h

38600h

4

DP Config (DP_​1_​8_​B0_​Config)

Package

00000000h

38604h

4

DP ChannelEn (DP_​1_​8_​B0_​ChannelEn)

Package

00000000h

38608h

4

DP SampleCtrl (DP_​1_​8_​B0_​SampleCtrl)

Package

00000000h

3860ch

4

DP OffsetCtrl (DP_​1_​8_​B0_​OffsetCtrl)

Package

00000000h

38610h

4

DP HCtrl (DP_​1_​8_​B0_​HCtrl)

Package

00000000h

38614h

4

DP AsyncCtrl (DP_​1_​8_​B0_​AsyncCtrl)

Package

00000000h

38618h

4

DP Config (DP_​1_​8_​B1_​Config)

Package

00000000h

3861ch

4

DP ChannelEn (DP_​1_​8_​B1_​ChannelEn)

Package

00000000h

38620h

4

DP SampleCtrl (DP_​1_​8_​B1_​SampleCtrl)

Package

00000000h

38624h

4

DP OffsetCtrl (DP_​1_​8_​B1_​OffsetCtrl)

Package

00000000h

38628h

4

DP HCtrl (DP_​1_​8_​B1_​HCtrl)

Package

00000000h

3862ch

4

DP AsyncCtrl (DP_​1_​8_​B1_​AsyncCtrl)

Package

00000000h

38630h

4

DP Port Ctrl (DP_​1_​8_​Port_​Ctrl)

Package

00000000h

38680h

4

DP Config (DP_​1_​9_​B0_​Config)

Package

00000000h

38684h

4

DP ChannelEn (DP_​1_​9_​B0_​ChannelEn)

Package

00000000h

38688h

4

DP SampleCtrl (DP_​1_​9_​B0_​SampleCtrl)

Package

00000000h

3868ch

4

DP OffsetCtrl (DP_​1_​9_​B0_​OffsetCtrl)

Package

00000000h

38690h

4

DP HCtrl (DP_​1_​9_​B0_​HCtrl)

Package

00000000h

38694h

4

DP AsyncCtrl (DP_​1_​9_​B0_​AsyncCtrl)

Package

00000000h

38698h

4

DP Config (DP_​1_​9_​B1_​Config)

Package

00000000h

3869ch

4

DP ChannelEn (DP_​1_​9_​B1_​ChannelEn)

Package

00000000h

386a0h

4

DP SampleCtrl (DP_​1_​9_​B1_​SampleCtrl)

Package

00000000h

386a4h

4

DP OffsetCtrl (DP_​1_​9_​B1_​OffsetCtrl)

Package

00000000h

386a8h

4

DP HCtrl (DP_​1_​9_​B1_​HCtrl)

Package

00000000h

386ach

4

DP AsyncCtrl (DP_​1_​9_​B1_​AsyncCtrl)

Package

00000000h

386b0h

4

DP Port Ctrl (DP_​1_​9_​Port_​Ctrl)

Package

00000000h

38700h

4

DP Config (DP_​1_​10_​B0_​Config)

Package

00000000h

38704h

4

DP ChannelEn (DP_​1_​10_​B0_​ChannelEn)

Package

00000000h

38708h

4

DP SampleCtrl (DP_​1_​10_​B0_​SampleCtrl)

Package

00000000h

3870ch

4

DP OffsetCtrl (DP_​1_​10_​B0_​OffsetCtrl)

Package

00000000h

38710h

4

DP HCtrl (DP_​1_​10_​B0_​HCtrl)

Package

00000000h

38714h

4

DP AsyncCtrl (DP_​1_​10_​B0_​AsyncCtrl)

Package

00000000h

38718h

4

DP Config (DP_​1_​10_​B1_​Config)

Package

00000000h

3871ch

4

DP ChannelEn (DP_​1_​10_​B1_​ChannelEn)

Package

00000000h

38720h

4

DP SampleCtrl (DP_​1_​10_​B1_​SampleCtrl)

Package

00000000h

38724h

4

DP OffsetCtrl (DP_​1_​10_​B1_​OffsetCtrl)

Package

00000000h

38728h

4

DP HCtrl (DP_​1_​10_​B1_​HCtrl)

Package

00000000h

3872ch

4

DP AsyncCtrl (DP_​1_​10_​B1_​AsyncCtrl)

Package

00000000h

38730h

4

DP Port Ctrl (DP_​1_​10_​Port_​Ctrl)

Package

00000000h

38780h

4

DP Config (DP_​1_​11_​B0_​Config)

Package

00000000h

38784h

4

DP ChannelEn (DP_​1_​11_​B0_​ChannelEn)

Package

00000000h

38788h

4

DP SampleCtrl (DP_​1_​11_​B0_​SampleCtrl)

Package

00000000h

3878ch

4

DP OffsetCtrl (DP_​1_​11_​B0_​OffsetCtrl)

Package

00000000h

38790h

4

DP HCtrl (DP_​1_​11_​B0_​HCtrl)

Package

00000000h

38794h

4

DP AsyncCtrl (DP_​1_​11_​B0_​AsyncCtrl)

Package

00000000h

38798h

4

DP Config (DP_​1_​11_​B1_​Config)

Package

00000000h

3879ch

4

DP ChannelEn (DP_​1_​11_​B1_​ChannelEn)

Package

00000000h

387a0h

4

DP SampleCtrl (DP_​1_​11_​B1_​SampleCtrl)

Package

00000000h

387a4h

4

DP OffsetCtrl (DP_​1_​11_​B1_​OffsetCtrl)

Package

00000000h

387a8h

4

DP HCtrl (DP_​1_​11_​B1_​HCtrl)

Package

00000000h

387ach

4

DP AsyncCtrl (DP_​1_​11_​B1_​AsyncCtrl)

Package

00000000h

387b0h

4

DP Port Ctrl (DP_​1_​11_​Port_​Ctrl)

Package

00000000h

38800h

4

DP Config (DP_​1_​12_​B0_​Config)

Package

00000000h

38804h

4

DP ChannelEn (DP_​1_​12_​B0_​ChannelEn)

Package

00000000h

38808h

4

DP SampleCtrl (DP_​1_​12_​B0_​SampleCtrl)

Package

00000000h

3880ch

4

DP OffsetCtrl (DP_​1_​12_​B0_​OffsetCtrl)

Package

00000000h

38810h

4

DP HCtrl (DP_​1_​12_​B0_​HCtrl)

Package

00000000h

38814h

4

DP AsyncCtrl (DP_​1_​12_​B0_​AsyncCtrl)

Package

00000000h

38818h

4

DP Config (DP_​1_​12_​B1_​Config)

Package

00000000h

3881ch

4

DP ChannelEn (DP_​1_​12_​B1_​ChannelEn)

Package

00000000h

38820h

4

DP SampleCtrl (DP_​1_​12_​B1_​SampleCtrl)

Package

00000000h

38824h

4

DP OffsetCtrl (DP_​1_​12_​B1_​OffsetCtrl)

Package

00000000h

38828h

4

DP HCtrl (DP_​1_​12_​B1_​HCtrl)

Package

00000000h

3882ch

4

DP AsyncCtrl (DP_​1_​12_​B1_​AsyncCtrl)

Package

00000000h

38830h

4

DP Port Ctrl (DP_​1_​12_​Port_​Ctrl)

Package

00000000h

38880h

4

DP Config (DP_​1_​13_​B0_​Config)

Package

00000000h

38884h

4

DP ChannelEn (DP_​1_​13_​B0_​ChannelEn)

Package

00000000h

38888h

4

DP SampleCtrl (DP_​1_​13_​B0_​SampleCtrl)

Package

00000000h

3888ch

4

DP OffsetCtrl (DP_​1_​13_​B0_​OffsetCtrl)

Package

00000000h

38890h

4

DP HCtrl (DP_​1_​13_​B0_​HCtrl)

Package

00000000h

38894h

4

DP AsyncCtrl (DP_​1_​13_​B0_​AsyncCtrl)

Package

00000000h

38898h

4

DP Config (DP_​1_​13_​B1_​Config)

Package

00000000h

3889ch

4

DP ChannelEn (DP_​1_​13_​B1_​ChannelEn)

Package

00000000h

388a0h

4

DP SampleCtrl (DP_​1_​13_​B1_​SampleCtrl)

Package

00000000h

388a4h

4

DP OffsetCtrl (DP_​1_​13_​B1_​OffsetCtrl)

Package

00000000h

388a8h

4

DP HCtrl (DP_​1_​13_​B1_​HCtrl)

Package

00000000h

388ach

4

DP AsyncCtrl (DP_​1_​13_​B1_​AsyncCtrl)

Package

00000000h

388b0h

4

DP Port Ctrl (DP_​1_​13_​Port_​Ctrl)

Package

00000000h

38900h

4

DP Config (DP_​1_​14_​B0_​Config)

Package

00000000h

38904h

4

DP ChannelEn (DP_​1_​14_​B0_​ChannelEn)

Package

00000000h

38908h

4

DP SampleCtrl (DP_​1_​14_​B0_​SampleCtrl)

Package

00000000h

3890ch

4

DP OffsetCtrl (DP_​1_​14_​B0_​OffsetCtrl)

Package

00000000h

38910h

4

DP HCtrl (DP_​1_​14_​B0_​HCtrl)

Package

00000000h

38914h

4

DP AsyncCtrl (DP_​1_​14_​B0_​AsyncCtrl)

Package

00000000h

38918h

4

DP Config (DP_​1_​14_​B1_​Config)

Package

00000000h

3891ch

4

DP ChannelEn (DP_​1_​14_​B1_​ChannelEn)

Package

00000000h

38920h

4

DP SampleCtrl (DP_​1_​14_​B1_​SampleCtrl)

Package

00000000h

38924h

4

DP OffsetCtrl (DP_​1_​14_​B1_​OffsetCtrl)

Package

00000000h

38928h

4

DP HCtrl (DP_​1_​14_​B1_​HCtrl)

Package

00000000h

3892ch

4

DP AsyncCtrl (DP_​1_​14_​B1_​AsyncCtrl)

Package

00000000h

38930h

4

DP Port Ctrl (DP_​1_​14_​Port_​Ctrl)

Package

00000000h

39200h

4

PDI Config (PDI_​1_​0_​Config)

Package

00000000h

39210h

4

PDI Config (PDI_​1_​1_​Config)

Package

00000000h

39220h

4

PDI Config (PDI_​1_​2_​Config)

Package

00000000h

39230h

4

PDI Config (PDI_​1_​3_​Config)

Package

00000000h

39240h

4

PDI Config (PDI_​1_​4_​Config)

Package

00000000h

39250h

4

PDI Config (PDI_​1_​5_​Config)

Package

00000000h

39260h

4

PDI Config (PDI_​1_​6_​Config)

Package

00000000h

39270h

4

PDI Config (PDI_​1_​7_​Config)

Package

00000000h

39280h

4

PDI Config (PDI_​1_​8_​Config)

Package

00000000h

39290h

4

PDI Config (PDI_​1_​9_​Config)

Package

00000000h

392a0h

4

PDI Config (PDI_​1_​10_​Config)

Package

00000000h

392b0h

4

PDI Config (PDI_​1_​11_​Config)

Package

00000000h

392c0h

4

PDI Config (PDI_​1_​12_​Config)

Package

00000000h

392d0h

4

PDI Config (PDI_​1_​13_​Config)

Package

00000000h

392e0h

4

PDI Config (PDI_​1_​14_​Config)

Package

00000000h

392f0h

4

PDI Config (PDI_​1_​15_​Config)

Package

00000000h

3c100h

4

IP MCP Config (IP_​MCP_​1_​Config)

Package

001F0005h

3c104h

4

IP MCP Control (IP_​MCP_​1_​Control)

Package

00000000h

3c108h

4

IP MCP CmdCtrl (IP_​MCP_​1_​CmdCtrl)

Package

00000000h

3c11ch

4

IP MCP PHYCtrl (IP_​MCP_​1_​PHYCtrl)

Package

00000000h

3c130h

4

IP MCP B0_​ClockCtrl (IP_​MCP_​1_​B0_​ClockCtrl)

Package

00000000h

3c140h

4

IP MCP Stat (IP_​MCP_​1_​Stat)

Package

00000000h

3c14ch

4

IP MCP IntSet (IP_​MCP_​1_​IntSet)

Package

00000000h

3c180h

4

IP MCP Command (IP_​MCP_​1_​Command)

Package

00000000h

3e004h

4

SoundWire x Link Vendor Specific Control (SNDW1LVSCTL)

Package

00000000h

3e008h

2

SoundWire x Wake Enable (SNDW1WAKEEN)

Package

0000h

3e00ah

2

SoundWire x Wake Status (SNDW1WAKESTS)

Package

0000h

3e00ch

2

SoundWire x I/O Control (SNDW1IOCTL)

Package

0004h

3e00eh

2

SoundWire x AC Timing Control (SNDW1ACTMCTL)

Package

003Ah

3e010h

2

SoundWire x Microphone Privacy Control & Status (SNDW1PVCCS)

Package

0000h

40000h

4

SoundWire x Link Extended Capability (SNDW2LECAP)

Package

00000006h

40010h

2

SoundWire x PCM Stream Capabilities (SNDW2PCMSCAP)

Package

0F00h

40014h

2

SoundWire PCM Stream y Channel Count (SNDW2PCMS0CHC)

Package

0007h

40016h

2

SoundWire x PCM Stream y Channel Map (SNDW2PCMS0CM)

Package

00F0h

40018h

2

SoundWire PCM Stream y Channel Count (SNDW2PCMS1CHC)

Package

0007h

4001ah

2

SoundWire x PCM Stream y Channel Map (SNDW2PCMS1CM)

Package

00F0h

4001ch

2

SoundWire PCM Stream y Channel Count (SNDW2PCMS2CHC)

Package

0007h

4001eh

2

SoundWire x PCM Stream y Channel Map (SNDW2PCMS2CM)

Package

00F0h

40020h

2

SoundWire PCM Stream y Channel Count (SNDW2PCMS3CHC)

Package

0007h

40022h

2

SoundWire x PCM Stream y Channel Map (SNDW2PCMS3CM)

Package

00F0h

40024h

2

SoundWire PCM Stream y Channel Count (SNDW2PCMS4CHC)

Package

0007h

40026h

2

SoundWire x PCM Stream y Channel Map (SNDW2PCMS4CM)

Package

00F0h

40028h

2

SoundWire PCM Stream y Channel Count (SNDW2PCMS5CHC)

Package

0007h

4002ah

2

SoundWire x PCM Stream y Channel Map (SNDW2PCMS5CM)

Package

00F0h

4002ch

2

SoundWire PCM Stream y Channel Count (SNDW2PCMS6CHC)

Package

0007h

4002eh

2

SoundWire x PCM Stream y Channel Map (SNDW2PCMS6CM)

Package

00F0h

40030h

2

SoundWire PCM Stream y Channel Count (SNDW2PCMS7CHC)

Package

0007h

40032h

2

SoundWire x PCM Stream y Channel Map (SNDW2PCMS7CM)

Package

00F0h

40034h

2

SoundWire PCM Stream y Channel Count (SNDW2PCMS8CHC)

Package

0007h

40036h

2

SoundWire x PCM Stream y Channel Map (SNDW2PCMS8CM)

Package

00F0h

40038h

2

SoundWire PCM Stream y Channel Count (SNDW2PCMS9CHC)

Package

0007h

4003ah

2

SoundWire x PCM Stream y Channel Map (SNDW2PCMS9CM)

Package

00F0h

4003ch

2

SoundWire PCM Stream y Channel Count (SNDW2PCMS10CHC)

Package

0007h

4003eh

2

SoundWire x PCM Stream y Channel Map (SNDW2PCMS10CM)

Package

00F0h

40040h

2

SoundWire PCM Stream y Channel Count (SNDW2PCMS11CHC)

Package

0007h

40042h

2

SoundWire x PCM Stream y Channel Map (SNDW2PCMS11CM)

Package

00F0h

40044h

2

SoundWire PCM Stream y Channel Count (SNDW2PCMS12CHC)

Package

0007h

40046h

2

SoundWire x PCM Stream y Channel Map (SNDW2PCMS12CM)

Package

00F0h

40048h

2

SoundWire PCM Stream y Channel Count (SNDW2PCMS13CHC)

Package

0007h

4004ah

2

SoundWire x PCM Stream y Channel Map (SNDW2PCMS13CM)

Package

00F0h

4004ch

2

SoundWire PCM Stream y Channel Count (SNDW2PCMS14CHC)

Package

0007h

4004eh

2

SoundWire x PCM Stream y Channel Map (SNDW2PCMS14CM)

Package

00F0h

40050h

2

SoundWire PCM Stream y Channel Count (SNDW2PCMS15CHC)

Package

0007h

40052h

2

SoundWire x PCM Stream y Channel Map (SNDW2PCMS15CM)

Package

00F0h

40100h

4

MCP Config (MCP_​2_​Config)

Package

00000000h

40104h

4

MCP Control (MCP_​2_​Control)

Package

00000000h

4010ch

4

MCP SSPStat (MCP_​2_​SSPStat)

Package

00000000h

40110h

4

MCP FrameShape (MCP_​2_​FrameShape)

Package

00000000h

40114h

4

MCP FrameShapeInit (MCP_​2_​FrameShapeInit)

Package

00000000h

40118h

4

MCP ConfigUpdate (MCP_​2_​ConfigUpdate)

Package

00000000h

40120h

4

MCP SSPCtrl (MCP_​2_​B0_​SSPCtrl)

Package

00000000h

40128h

4

MCP SSPCtrl (MCP_​2_​B1_​SSPCtrl)

Package

00000000h

40130h

4

MCP ClockCtrl (MCP_​2_​B0_​ClockCtrl)

Package

00000000h

40138h

4

MCP ClockCtrl (MCP_​2_​B1_​ClockCtrl)

Package

00000000h

40140h

4

MCP Stat (MCP_​2_​Stat)

Package

00000002h

40144h

4

MCP IntStat (MCP_​2_​IntStat)

Package

00000000h

40148h

4

MCP IntMask (MCP_​2_​IntMask)

Package

00000000h

40150h

4

MCP PeripheryStat (MCP_​2_​PeripheryStat)

Package

00000000h

40154h

4

MCP PeripheryIntStat0 (MCP_​2_​PeripheryIntStat0)

Package

00000000h

40158h

4

MCP PeripheryIntStat1 (MCP_​2_​PeripheryIntStat1)

Package

00000000h

4015ch

4

MCP PeripheryIntMask0 (MCP_​2_​PeripheryIntMask0)

Package

00000000h

40160h

4

MCP PeripheryIntMask1 (MCP_​2_​PeripheryIntMask1)

Package

00000000h

40164h

4

MCP PortIntStat (MCP_​2_​PortIntStat)

Package

00000000h

4016ch

4

MCP PDIStat (MCP_​2_​PDIStat)

Package

00000000h

40178h

4

MCP FIFOLevel (MCP_​2_​FIFOLevel)

Package

00000002h

4017ch

4

MCP FIFOStat (MCP_​2_​FIFOStat)

Package

00000800h

40200h

4

DP Config (DP_​2_​0_​B0_​Config)

Package

00000000h

40204h

4

DP ChannelEn (DP_​2_​0_​B0_​ChannelEn)

Package

00000000h

40208h

4

DP SampleCtrl (DP_​2_​0_​B0_​SampleCtrl)

Package

00000000h

4020ch

4

DP OffsetCtrl (DP_​2_​0_​B0_​OffsetCtrl)

Package

00000000h

40210h

4

DP HCtrl (DP_​2_​0_​B0_​HCtrl)

Package

00000000h

40214h

4

DP AsyncCtrl (DP_​2_​0_​B0_​AsyncCtrl)

Package

00000000h

40218h

4

DP Config (DP_​2_​0_​B1_​Config)

Package

00000000h

4021ch

4

DP ChannelEn (DP_​2_​0_​B1_​ChannelEn)

Package

00000000h

40220h

4

DP SampleCtrl (DP_​2_​0_​B1_​SampleCtrl)

Package

00000000h

40224h

4

DP OffsetCtrl (DP_​2_​0_​B1_​OffsetCtrl)

Package

00000000h

40228h

4

DP HCtrl (DP_​2_​0_​B1_​HCtrl)

Package

00000000h

4022ch

4

DP AsyncCtrl (DP_​2_​0_​B1_​AsyncCtrl)

Package

00000000h

40230h

4

DP Port Ctrl (DP_​2_​0_​Port_​Ctrl)

Package

00000000h

40280h

4

DP Config (DP_​2_​1_​B0_​Config)

Package

00000000h

40284h

4

DP ChannelEn (DP_​2_​1_​B0_​ChannelEn)

Package

00000000h

40288h

4

DP SampleCtrl (DP_​2_​1_​B0_​SampleCtrl)

Package

00000000h

4028ch

4

DP OffsetCtrl (DP_​2_​1_​B0_​OffsetCtrl)

Package

00000000h

40290h

4

DP HCtrl (DP_​2_​1_​B0_​HCtrl)

Package

00000000h

40294h

4

DP AsyncCtrl (DP_​2_​1_​B0_​AsyncCtrl)

Package

00000000h

40298h

4

DP Config (DP_​2_​1_​B1_​Config)

Package

00000000h

4029ch

4

DP ChannelEn (DP_​2_​1_​B1_​ChannelEn)

Package

00000000h

402a0h

4

DP SampleCtrl (DP_​2_​1_​B1_​SampleCtrl)

Package

00000000h

402a4h

4

DP OffsetCtrl (DP_​2_​1_​B1_​OffsetCtrl)

Package

00000000h

402a8h

4

DP HCtrl (DP_​2_​1_​B1_​HCtrl)

Package

00000000h

402ach

4

DP AsyncCtrl (DP_​2_​1_​B1_​AsyncCtrl)

Package

00000000h

402b0h

4

DP Port Ctrl (DP_​2_​1_​Port_​Ctrl)

Package

00000000h

40300h

4

DP Config (DP_​2_​2_​B0_​Config)

Package

00000000h

40304h

4

DP ChannelEn (DP_​2_​2_​B0_​ChannelEn)

Package

00000000h

40308h

4

DP SampleCtrl (DP_​2_​2_​B0_​SampleCtrl)

Package

00000000h

4030ch

4

DP OffsetCtrl (DP_​2_​2_​B0_​OffsetCtrl)

Package

00000000h

40310h

4

DP HCtrl (DP_​2_​2_​B0_​HCtrl)

Package

00000000h

40314h

4

DP AsyncCtrl (DP_​2_​2_​B0_​AsyncCtrl)

Package

00000000h

40318h

4

DP Config (DP_​2_​2_​B1_​Config)

Package

00000000h

4031ch

4

DP ChannelEn (DP_​2_​2_​B1_​ChannelEn)

Package

00000000h

40320h

4

DP SampleCtrl (DP_​2_​2_​B1_​SampleCtrl)

Package

00000000h

40324h

4

DP OffsetCtrl (DP_​2_​2_​B1_​OffsetCtrl)

Package

00000000h

40328h

4

DP HCtrl (DP_​2_​2_​B1_​HCtrl)

Package

00000000h

4032ch

4

DP AsyncCtrl (DP_​2_​2_​B1_​AsyncCtrl)

Package

00000000h

40330h

4

DP Port Ctrl (DP_​2_​2_​Port_​Ctrl)

Package

00000000h

40380h

4

DP Config (DP_​2_​3_​B0_​Config)

Package

00000000h

40384h

4

DP ChannelEn (DP_​2_​3_​B0_​ChannelEn)

Package

00000000h

40388h

4

DP SampleCtrl (DP_​2_​3_​B0_​SampleCtrl)

Package

00000000h

4038ch

4

DP OffsetCtrl (DP_​2_​3_​B0_​OffsetCtrl)

Package

00000000h

40390h

4

DP HCtrl (DP_​2_​3_​B0_​HCtrl)

Package

00000000h

40394h

4

DP AsyncCtrl (DP_​2_​3_​B0_​AsyncCtrl)

Package

00000000h

40398h

4

DP Config (DP_​2_​3_​B1_​Config)

Package

00000000h

4039ch

4

DP ChannelEn (DP_​2_​3_​B1_​ChannelEn)

Package

00000000h

403a0h

4

DP SampleCtrl (DP_​2_​3_​B1_​SampleCtrl)

Package

00000000h

403a4h

4

DP OffsetCtrl (DP_​2_​3_​B1_​OffsetCtrl)

Package

00000000h

403a8h

4

DP HCtrl (DP_​2_​3_​B1_​HCtrl)

Package

00000000h

403ach

4

DP AsyncCtrl (DP_​2_​3_​B1_​AsyncCtrl)

Package

00000000h

403b0h

4

DP Port Ctrl (DP_​2_​3_​Port_​Ctrl)

Package

00000000h

40400h

4

DP Config (DP_​2_​4_​B0_​Config)

Package

00000000h

40404h

4

DP ChannelEn (DP_​2_​4_​B0_​ChannelEn)

Package

00000000h

40408h

4

DP SampleCtrl (DP_​2_​4_​B0_​SampleCtrl)

Package

00000000h

4040ch

4

DP OffsetCtrl (DP_​2_​4_​B0_​OffsetCtrl)

Package

00000000h

40410h

4

DP HCtrl (DP_​2_​4_​B0_​HCtrl)

Package

00000000h

40414h

4

DP AsyncCtrl (DP_​2_​4_​B0_​AsyncCtrl)

Package

00000000h

40418h

4

DP Config (DP_​2_​4_​B1_​Config)

Package

00000000h

4041ch

4

DP ChannelEn (DP_​2_​4_​B1_​ChannelEn)

Package

00000000h

40420h

4

DP SampleCtrl (DP_​2_​4_​B1_​SampleCtrl)

Package

00000000h

40424h

4

DP OffsetCtrl (DP_​2_​4_​B1_​OffsetCtrl)

Package

00000000h

40428h

4

DP HCtrl (DP_​2_​4_​B1_​HCtrl)

Package

00000000h

4042ch

4

DP AsyncCtrl (DP_​2_​4_​B1_​AsyncCtrl)

Package

00000000h

40430h

4

DP Port Ctrl (DP_​2_​4_​Port_​Ctrl)

Package

00000000h

40480h

4

DP Config (DP_​2_​5_​B0_​Config)

Package

00000000h

40484h

4

DP ChannelEn (DP_​2_​5_​B0_​ChannelEn)

Package

00000000h

40488h

4

DP SampleCtrl (DP_​2_​5_​B0_​SampleCtrl)

Package

00000000h

4048ch

4

DP OffsetCtrl (DP_​2_​5_​B0_​OffsetCtrl)

Package

00000000h

40490h

4

DP HCtrl (DP_​2_​5_​B0_​HCtrl)

Package

00000000h

40494h

4

DP AsyncCtrl (DP_​2_​5_​B0_​AsyncCtrl)

Package

00000000h

40498h

4

DP Config (DP_​2_​5_​B1_​Config)

Package

00000000h

4049ch

4

DP ChannelEn (DP_​2_​5_​B1_​ChannelEn)

Package

00000000h

404a0h

4

DP SampleCtrl (DP_​2_​5_​B1_​SampleCtrl)

Package

00000000h

404a4h

4

DP OffsetCtrl (DP_​2_​5_​B1_​OffsetCtrl)

Package

00000000h

404a8h

4

DP HCtrl (DP_​2_​5_​B1_​HCtrl)

Package

00000000h

404ach

4

DP AsyncCtrl (DP_​2_​5_​B1_​AsyncCtrl)

Package

00000000h

404b0h

4

DP Port Ctrl (DP_​2_​5_​Port_​Ctrl)

Package

00000000h

40500h

4

DP Config (DP_​2_​6_​B0_​Config)

Package

00000000h

40504h

4

DP ChannelEn (DP_​2_​6_​B0_​ChannelEn)

Package

00000000h

40508h

4

DP SampleCtrl (DP_​2_​6_​B0_​SampleCtrl)

Package

00000000h

4050ch

4

DP OffsetCtrl (DP_​2_​6_​B0_​OffsetCtrl)

Package

00000000h

40510h

4

DP HCtrl (DP_​2_​6_​B0_​HCtrl)

Package

00000000h

40514h

4

DP AsyncCtrl (DP_​2_​6_​B0_​AsyncCtrl)

Package

00000000h

40518h

4

DP Config (DP_​2_​6_​B1_​Config)

Package

00000000h

4051ch

4

DP ChannelEn (DP_​2_​6_​B1_​ChannelEn)

Package

00000000h

40520h

4

DP SampleCtrl (DP_​2_​6_​B1_​SampleCtrl)

Package

00000000h

40524h

4

DP OffsetCtrl (DP_​2_​6_​B1_​OffsetCtrl)

Package

00000000h

40528h

4

DP HCtrl (DP_​2_​6_​B1_​HCtrl)

Package

00000000h

4052ch

4

DP AsyncCtrl (DP_​2_​6_​B1_​AsyncCtrl)

Package

00000000h

40530h

4

DP Port Ctrl (DP_​2_​6_​Port_​Ctrl)

Package

00000000h

40580h

4

DP Config (DP_​2_​7_​B0_​Config)

Package

00000000h

40584h

4

DP ChannelEn (DP_​2_​7_​B0_​ChannelEn)

Package

00000000h

40588h

4

DP SampleCtrl (DP_​2_​7_​B0_​SampleCtrl)

Package

00000000h

4058ch

4

DP OffsetCtrl (DP_​2_​7_​B0_​OffsetCtrl)

Package

00000000h

40590h

4

DP HCtrl (DP_​2_​7_​B0_​HCtrl)

Package

00000000h

40594h

4

DP AsyncCtrl (DP_​2_​7_​B0_​AsyncCtrl)

Package

00000000h

40598h

4

DP Config (DP_​2_​7_​B1_​Config)

Package

00000000h

4059ch

4

DP ChannelEn (DP_​2_​7_​B1_​ChannelEn)

Package

00000000h

405a0h

4

DP SampleCtrl (DP_​2_​7_​B1_​SampleCtrl)

Package

00000000h

405a4h

4

DP OffsetCtrl (DP_​2_​7_​B1_​OffsetCtrl)

Package

00000000h

405a8h

4

DP HCtrl (DP_​2_​7_​B1_​HCtrl)

Package

00000000h

405ach

4

DP AsyncCtrl (DP_​2_​7_​B1_​AsyncCtrl)

Package

00000000h

405b0h

4

DP Port Ctrl (DP_​2_​7_​Port_​Ctrl)

Package

00000000h

40600h

4

DP Config (DP_​2_​8_​B0_​Config)

Package

00000000h

40604h

4

DP ChannelEn (DP_​2_​8_​B0_​ChannelEn)

Package

00000000h

40608h

4

DP SampleCtrl (DP_​2_​8_​B0_​SampleCtrl)

Package

00000000h

4060ch

4

DP OffsetCtrl (DP_​2_​8_​B0_​OffsetCtrl)

Package

00000000h

40610h

4

DP HCtrl (DP_​2_​8_​B0_​HCtrl)

Package

00000000h

40614h

4

DP AsyncCtrl (DP_​2_​8_​B0_​AsyncCtrl)

Package

00000000h

40618h

4

DP Config (DP_​2_​8_​B1_​Config)

Package

00000000h

4061ch

4

DP ChannelEn (DP_​2_​8_​B1_​ChannelEn)

Package

00000000h

40620h

4

DP SampleCtrl (DP_​2_​8_​B1_​SampleCtrl)

Package

00000000h

40624h

4

DP OffsetCtrl (DP_​2_​8_​B1_​OffsetCtrl)

Package

00000000h

40628h

4

DP HCtrl (DP_​2_​8_​B1_​HCtrl)

Package

00000000h

4062ch

4

DP AsyncCtrl (DP_​2_​8_​B1_​AsyncCtrl)

Package

00000000h

40630h

4

DP Port Ctrl (DP_​2_​8_​Port_​Ctrl)

Package

00000000h

40680h

4

DP Config (DP_​2_​9_​B0_​Config)

Package

00000000h

40684h

4

DP ChannelEn (DP_​2_​9_​B0_​ChannelEn)

Package

00000000h

40688h

4

DP SampleCtrl (DP_​2_​9_​B0_​SampleCtrl)

Package

00000000h

4068ch

4

DP OffsetCtrl (DP_​2_​9_​B0_​OffsetCtrl)

Package

00000000h

40690h

4

DP HCtrl (DP_​2_​9_​B0_​HCtrl)

Package

00000000h

40694h

4

DP AsyncCtrl (DP_​2_​9_​B0_​AsyncCtrl)

Package

00000000h

40698h

4

DP Config (DP_​2_​9_​B1_​Config)

Package

00000000h

4069ch

4

DP ChannelEn (DP_​2_​9_​B1_​ChannelEn)

Package

00000000h

406a0h

4

DP SampleCtrl (DP_​2_​9_​B1_​SampleCtrl)

Package

00000000h

406a4h

4

DP OffsetCtrl (DP_​2_​9_​B1_​OffsetCtrl)

Package

00000000h

406a8h

4

DP HCtrl (DP_​2_​9_​B1_​HCtrl)

Package

00000000h

406ach

4

DP AsyncCtrl (DP_​2_​9_​B1_​AsyncCtrl)

Package

00000000h

406b0h

4

DP Port Ctrl (DP_​2_​9_​Port_​Ctrl)

Package

00000000h

40700h

4

DP Config (DP_​2_​10_​B0_​Config)

Package

00000000h

40704h

4

DP ChannelEn (DP_​2_​10_​B0_​ChannelEn)

Package

00000000h

40708h

4

DP SampleCtrl (DP_​2_​10_​B0_​SampleCtrl)

Package

00000000h

4070ch

4

DP OffsetCtrl (DP_​2_​10_​B0_​OffsetCtrl)

Package

00000000h

40710h

4

DP HCtrl (DP_​2_​10_​B0_​HCtrl)

Package

00000000h

40714h

4

DP AsyncCtrl (DP_​2_​10_​B0_​AsyncCtrl)

Package

00000000h

40718h

4

DP Config (DP_​2_​10_​B1_​Config)

Package

00000000h

4071ch

4

DP ChannelEn (DP_​2_​10_​B1_​ChannelEn)

Package

00000000h

40720h

4

DP SampleCtrl (DP_​2_​10_​B1_​SampleCtrl)

Package

00000000h

40724h

4

DP OffsetCtrl (DP_​2_​10_​B1_​OffsetCtrl)

Package

00000000h

40728h

4

DP HCtrl (DP_​2_​10_​B1_​HCtrl)

Package

00000000h

4072ch

4

DP AsyncCtrl (DP_​2_​10_​B1_​AsyncCtrl)

Package

00000000h

40730h

4

DP Port Ctrl (DP_​2_​10_​Port_​Ctrl)

Package

00000000h

40780h

4

DP Config (DP_​2_​11_​B0_​Config)

Package

00000000h

40784h

4

DP ChannelEn (DP_​2_​11_​B0_​ChannelEn)

Package

00000000h

40788h

4

DP SampleCtrl (DP_​2_​11_​B0_​SampleCtrl)

Package

00000000h

4078ch

4

DP OffsetCtrl (DP_​2_​11_​B0_​OffsetCtrl)

Package

00000000h

40790h

4

DP HCtrl (DP_​2_​11_​B0_​HCtrl)

Package

00000000h

40794h

4

DP AsyncCtrl (DP_​2_​11_​B0_​AsyncCtrl)

Package

00000000h

40798h

4

DP Config (DP_​2_​11_​B1_​Config)

Package

00000000h

4079ch

4

DP ChannelEn (DP_​2_​11_​B1_​ChannelEn)

Package

00000000h

407a0h

4

DP SampleCtrl (DP_​2_​11_​B1_​SampleCtrl)

Package

00000000h

407a4h

4

DP OffsetCtrl (DP_​2_​11_​B1_​OffsetCtrl)

Package

00000000h

407a8h

4

DP HCtrl (DP_​2_​11_​B1_​HCtrl)

Package

00000000h

407ach

4

DP AsyncCtrl (DP_​2_​11_​B1_​AsyncCtrl)

Package

00000000h

407b0h

4

DP Port Ctrl (DP_​2_​11_​Port_​Ctrl)

Package

00000000h

40800h

4

DP Config (DP_​2_​12_​B0_​Config)

Package

00000000h

40804h

4

DP ChannelEn (DP_​2_​12_​B0_​ChannelEn)

Package

00000000h

40808h

4

DP SampleCtrl (DP_​2_​12_​B0_​SampleCtrl)

Package

00000000h

4080ch

4

DP OffsetCtrl (DP_​2_​12_​B0_​OffsetCtrl)

Package

00000000h

40810h

4

DP HCtrl (DP_​2_​12_​B0_​HCtrl)

Package

00000000h

40814h

4

DP AsyncCtrl (DP_​2_​12_​B0_​AsyncCtrl)

Package

00000000h

40818h

4

DP Config (DP_​2_​12_​B1_​Config)

Package

00000000h

4081ch

4

DP ChannelEn (DP_​2_​12_​B1_​ChannelEn)

Package

00000000h

40820h

4

DP SampleCtrl (DP_​2_​12_​B1_​SampleCtrl)

Package

00000000h

40824h

4

DP OffsetCtrl (DP_​2_​12_​B1_​OffsetCtrl)

Package

00000000h

40828h

4

DP HCtrl (DP_​2_​12_​B1_​HCtrl)

Package

00000000h

4082ch

4

DP AsyncCtrl (DP_​2_​12_​B1_​AsyncCtrl)

Package

00000000h

40830h

4

DP Port Ctrl (DP_​2_​12_​Port_​Ctrl)

Package

00000000h

40880h

4

DP Config (DP_​2_​13_​B0_​Config)

Package

00000000h

40884h

4

DP ChannelEn (DP_​2_​13_​B0_​ChannelEn)

Package

00000000h

40888h

4

DP SampleCtrl (DP_​2_​13_​B0_​SampleCtrl)

Package

00000000h

4088ch

4

DP OffsetCtrl (DP_​2_​13_​B0_​OffsetCtrl)

Package

00000000h

40890h

4

DP HCtrl (DP_​2_​13_​B0_​HCtrl)

Package

00000000h

40894h

4

DP AsyncCtrl (DP_​2_​13_​B0_​AsyncCtrl)

Package

00000000h

40898h

4

DP Config (DP_​2_​13_​B1_​Config)

Package

00000000h

4089ch

4

DP ChannelEn (DP_​2_​13_​B1_​ChannelEn)

Package

00000000h

408a0h

4

DP SampleCtrl (DP_​2_​13_​B1_​SampleCtrl)

Package

00000000h

408a4h

4

DP OffsetCtrl (DP_​2_​13_​B1_​OffsetCtrl)

Package

00000000h

408a8h

4

DP HCtrl (DP_​2_​13_​B1_​HCtrl)

Package

00000000h

408ach

4

DP AsyncCtrl (DP_​2_​13_​B1_​AsyncCtrl)

Package

00000000h

408b0h

4

DP Port Ctrl (DP_​2_​13_​Port_​Ctrl)

Package

00000000h

40900h

4

DP Config (DP_​2_​14_​B0_​Config)

Package

00000000h

40904h

4

DP ChannelEn (DP_​2_​14_​B0_​ChannelEn)

Package

00000000h

40908h

4

DP SampleCtrl (DP_​2_​14_​B0_​SampleCtrl)

Package

00000000h

4090ch

4

DP OffsetCtrl (DP_​2_​14_​B0_​OffsetCtrl)

Package

00000000h

40910h

4

DP HCtrl (DP_​2_​14_​B0_​HCtrl)

Package

00000000h

40914h

4

DP AsyncCtrl (DP_​2_​14_​B0_​AsyncCtrl)

Package

00000000h

40918h

4

DP Config (DP_​2_​14_​B1_​Config)

Package

00000000h

4091ch

4

DP ChannelEn (DP_​2_​14_​B1_​ChannelEn)

Package

00000000h

40920h

4

DP SampleCtrl (DP_​2_​14_​B1_​SampleCtrl)

Package

00000000h

40924h

4

DP OffsetCtrl (DP_​2_​14_​B1_​OffsetCtrl)

Package

00000000h

40928h

4

DP HCtrl (DP_​2_​14_​B1_​HCtrl)

Package

00000000h

4092ch

4

DP AsyncCtrl (DP_​2_​14_​B1_​AsyncCtrl)

Package

00000000h

40930h

4

DP Port Ctrl (DP_​2_​14_​Port_​Ctrl)

Package

00000000h

41200h

4

PDI Config (PDI_​2_​0_​Config)

Package

00000000h

41210h

4

PDI Config (PDI_​2_​1_​Config)

Package

00000000h

41220h

4

PDI Config (PDI_​2_​2_​Config)

Package

00000000h

41230h

4

PDI Config (PDI_​2_​3_​Config)

Package

00000000h

41240h

4

PDI Config (PDI_​2_​4_​Config)

Package

00000000h

41250h

4

PDI Config (PDI_​2_​5_​Config)

Package

00000000h

41260h

4

PDI Config (PDI_​2_​6_​Config)

Package

00000000h

41270h

4

PDI Config (PDI_​2_​7_​Config)

Package

00000000h

41280h

4

PDI Config (PDI_​2_​8_​Config)

Package

00000000h

41290h

4

PDI Config (PDI_​2_​9_​Config)

Package

00000000h

412a0h

4

PDI Config (PDI_​2_​10_​Config)

Package

00000000h

412b0h

4

PDI Config (PDI_​2_​11_​Config)

Package

00000000h

412c0h

4

PDI Config (PDI_​2_​12_​Config)

Package

00000000h

412d0h

4

PDI Config (PDI_​2_​13_​Config)

Package

00000000h

412e0h

4

PDI Config (PDI_​2_​14_​Config)

Package

00000000h

412f0h

4

PDI Config (PDI_​2_​15_​Config)

Package

00000000h

44100h

4

IP MCP Config (IP_​MCP_​2_​Config)

Package

001F0005h

44104h

4

IP MCP Control (IP_​MCP_​2_​Control)

Package

00000000h

44108h

4

IP MCP CmdCtrl (IP_​MCP_​2_​CmdCtrl)

Package

00000000h

4411ch

4

IP MCP PHYCtrl (IP_​MCP_​2_​PHYCtrl)

Package

00000000h

44130h

4

IP MCP B0_​ClockCtrl (IP_​MCP_​2_​B0_​ClockCtrl)

Package

00000000h

44140h

4

IP MCP Stat (IP_​MCP_​2_​Stat)

Package

00000000h

4414ch

4

IP MCP IntSet (IP_​MCP_​2_​IntSet)

Package

00000000h

44180h

4

IP MCP Command (IP_​MCP_​2_​Command)

Package

00000000h

46004h

4

SoundWire x Link Vendor Specific Control (SNDW2LVSCTL)

Package

00000000h

46008h

2

SoundWire x Wake Enable (SNDW2WAKEEN)

Package

0000h

4600ah

2

SoundWire x Wake Status (SNDW2WAKESTS)

Package

0000h

4600ch

2

SoundWire x I/O Control (SNDW2IOCTL)

Package

0004h

4600eh

2

SoundWire x AC Timing Control (SNDW2ACTMCTL)

Package

003Ah

46010h

2

SoundWire x Microphone Privacy Control & Status (SNDW2PVCCS)

Package

0000h

48000h

4

SoundWire x Link Extended Capability (SNDW3LECAP)

Package

00000006h

48010h

2

SoundWire x PCM Stream Capabilities (SNDW3PCMSCAP)

Package

0F00h

48014h

2

SoundWire PCM Stream y Channel Count (SNDW3PCMS0CHC)

Package

0007h

48016h

2

SoundWire x PCM Stream y Channel Map (SNDW3PCMS0CM)

Package

00F0h

48018h

2

SoundWire PCM Stream y Channel Count (SNDW3PCMS1CHC)

Package

0007h

4801ah

2

SoundWire x PCM Stream y Channel Map (SNDW3PCMS1CM)

Package

00F0h

4801ch

2

SoundWire PCM Stream y Channel Count (SNDW3PCMS2CHC)

Package

0007h

4801eh

2

SoundWire x PCM Stream y Channel Map (SNDW3PCMS2CM)

Package

00F0h

48020h

2

SoundWire PCM Stream y Channel Count (SNDW3PCMS3CHC)

Package

0007h

48022h

2

SoundWire x PCM Stream y Channel Map (SNDW3PCMS3CM)

Package

00F0h

48024h

2

SoundWire PCM Stream y Channel Count (SNDW3PCMS4CHC)

Package

0007h

48026h

2

SoundWire x PCM Stream y Channel Map (SNDW3PCMS4CM)

Package

00F0h

48028h

2

SoundWire PCM Stream y Channel Count (SNDW3PCMS5CHC)

Package

0007h

4802ah

2

SoundWire x PCM Stream y Channel Map (SNDW3PCMS5CM)

Package

00F0h

4802ch

2

SoundWire PCM Stream y Channel Count (SNDW3PCMS6CHC)

Package

0007h

4802eh

2

SoundWire x PCM Stream y Channel Map (SNDW3PCMS6CM)

Package

00F0h

48030h

2

SoundWire PCM Stream y Channel Count (SNDW3PCMS7CHC)

Package

0007h

48032h

2

SoundWire x PCM Stream y Channel Map (SNDW3PCMS7CM)

Package

00F0h

48034h

2

SoundWire PCM Stream y Channel Count (SNDW3PCMS8CHC)

Package

0007h

48036h

2

SoundWire x PCM Stream y Channel Map (SNDW3PCMS8CM)

Package

00F0h

48038h

2

SoundWire PCM Stream y Channel Count (SNDW3PCMS9CHC)

Package

0007h

4803ah

2

SoundWire x PCM Stream y Channel Map (SNDW3PCMS9CM)

Package

00F0h

4803ch

2

SoundWire PCM Stream y Channel Count (SNDW3PCMS10CHC)

Package

0007h

4803eh

2

SoundWire x PCM Stream y Channel Map (SNDW3PCMS10CM)

Package

00F0h

48040h

2

SoundWire PCM Stream y Channel Count (SNDW3PCMS11CHC)

Package

0007h

48042h

2

SoundWire x PCM Stream y Channel Map (SNDW3PCMS11CM)

Package

00F0h

48044h

2

SoundWire PCM Stream y Channel Count (SNDW3PCMS12CHC)

Package

0007h

48046h

2

SoundWire x PCM Stream y Channel Map (SNDW3PCMS12CM)

Package

00F0h

48048h

2

SoundWire PCM Stream y Channel Count (SNDW3PCMS13CHC)

Package

0007h

4804ah

2

SoundWire x PCM Stream y Channel Map (SNDW3PCMS13CM)

Package

00F0h

4804ch

2

SoundWire PCM Stream y Channel Count (SNDW3PCMS14CHC)

Package

0007h

4804eh

2

SoundWire x PCM Stream y Channel Map (SNDW3PCMS14CM)

Package

00F0h

48050h

2

SoundWire PCM Stream y Channel Count (SNDW3PCMS15CHC)

Package

0007h

48052h

2

SoundWire x PCM Stream y Channel Map (SNDW3PCMS15CM)

Package

00F0h

48100h

4

MCP Config (MCP_​3_​Config)

Package

00000000h

48104h

4

MCP Control (MCP_​3_​Control)

Package

00000000h

4810ch

4

MCP SSPStat (MCP_​3_​SSPStat)

Package

00000000h

48110h

4

MCP FrameShape (MCP_​3_​FrameShape)

Package

00000000h

48114h

4

MCP FrameShapeInit (MCP_​3_​FrameShapeInit)

Package

00000000h

48118h

4

MCP ConfigUpdate (MCP_​3_​ConfigUpdate)

Package

00000000h

48120h

4

MCP SSPCtrl (MCP_​3_​B0_​SSPCtrl)

Package

00000000h

48128h

4

MCP SSPCtrl (MCP_​3_​B1_​SSPCtrl)

Package

00000000h

48130h

4

MCP ClockCtrl (MCP_​3_​B0_​ClockCtrl)

Package

00000000h

48138h

4

MCP ClockCtrl (MCP_​3_​B1_​ClockCtrl)

Package

00000000h

48140h

4

MCP Stat (MCP_​3_​Stat)

Package

00000002h

48144h

4

MCP IntStat (MCP_​3_​IntStat)

Package

00000000h

48148h

4

MCP IntMask (MCP_​3_​IntMask)

Package

00000000h

48150h

4

MCP PeripheryStat (MCP_​3_​PeripheryStat)

Package

00000000h

48154h

4

MCP PeripheryIntStat0 (MCP_​3_​PeripheryIntStat0)

Package

00000000h

48158h

4

MCP PeripheryIntStat1 (MCP_​3_​PeripheryIntStat1)

Package

00000000h

4815ch

4

MCP PeripheryIntMask0 (MCP_​3_​PeripheryIntMask0)

Package

00000000h

48160h

4

MCP PeripheryIntMask1 (MCP_​3_​PeripheryIntMask1)

Package

00000000h

48164h

4

MCP PortIntStat (MCP_​3_​PortIntStat)

Package

00000000h

4816ch

4

MCP PDIStat (MCP_​3_​PDIStat)

Package

00000000h

48178h

4

MCP FIFOLevel (MCP_​3_​FIFOLevel)

Package

00000002h

4817ch

4

MCP FIFOStat (MCP_​3_​FIFOStat)

Package

00000800h

48200h

4

DP Config (DP_​3_​0_​B0_​Config)

Package

00000000h

48204h

4

DP ChannelEn (DP_​3_​0_​B0_​ChannelEn)

Package

00000000h

48208h

4

DP SampleCtrl (DP_​3_​0_​B0_​SampleCtrl)

Package

00000000h

4820ch

4

DP OffsetCtrl (DP_​3_​0_​B0_​OffsetCtrl)

Package

00000000h

48210h

4

DP HCtrl (DP_​3_​0_​B0_​HCtrl)

Package

00000000h

48214h

4

DP AsyncCtrl (DP_​3_​0_​B0_​AsyncCtrl)

Package

00000000h

48218h

4

DP Config (DP_​3_​0_​B1_​Config)

Package

00000000h

4821ch

4

DP ChannelEn (DP_​3_​0_​B1_​ChannelEn)

Package

00000000h

48220h

4

DP SampleCtrl (DP_​3_​0_​B1_​SampleCtrl)

Package

00000000h

48224h

4

DP OffsetCtrl (DP_​3_​0_​B1_​OffsetCtrl)

Package

00000000h

48228h

4

DP HCtrl (DP_​3_​0_​B1_​HCtrl)

Package

00000000h

4822ch

4

DP AsyncCtrl (DP_​3_​0_​B1_​AsyncCtrl)

Package

00000000h

48230h

4

DP Port Ctrl (DP_​3_​0_​Port_​Ctrl)

Package

00000000h

48280h

4

DP Config (DP_​3_​1_​B0_​Config)

Package

00000000h

48284h

4

DP ChannelEn (DP_​3_​1_​B0_​ChannelEn)

Package

00000000h

48288h

4

DP SampleCtrl (DP_​3_​1_​B0_​SampleCtrl)

Package

00000000h

4828ch

4

DP OffsetCtrl (DP_​3_​1_​B0_​OffsetCtrl)

Package

00000000h

48290h

4

DP HCtrl (DP_​3_​1_​B0_​HCtrl)

Package

00000000h

48294h

4

DP AsyncCtrl (DP_​3_​1_​B0_​AsyncCtrl)

Package

00000000h

48298h

4

DP Config (DP_​3_​1_​B1_​Config)

Package

00000000h

4829ch

4

DP ChannelEn (DP_​3_​1_​B1_​ChannelEn)

Package

00000000h

482a0h

4

DP SampleCtrl (DP_​3_​1_​B1_​SampleCtrl)

Package

00000000h

482a4h

4

DP OffsetCtrl (DP_​3_​1_​B1_​OffsetCtrl)

Package

00000000h

482a8h

4

DP HCtrl (DP_​3_​1_​B1_​HCtrl)

Package

00000000h

482ach

4

DP AsyncCtrl (DP_​3_​1_​B1_​AsyncCtrl)

Package

00000000h

482b0h

4

DP Port Ctrl (DP_​3_​1_​Port_​Ctrl)

Package

00000000h

48300h

4

DP Config (DP_​3_​2_​B0_​Config)

Package

00000000h

48304h

4

DP ChannelEn (DP_​3_​2_​B0_​ChannelEn)

Package

00000000h

48308h

4

DP SampleCtrl (DP_​3_​2_​B0_​SampleCtrl)

Package

00000000h

4830ch

4

DP OffsetCtrl (DP_​3_​2_​B0_​OffsetCtrl)

Package

00000000h

48310h

4

DP HCtrl (DP_​3_​2_​B0_​HCtrl)

Package

00000000h

48314h

4

DP AsyncCtrl (DP_​3_​2_​B0_​AsyncCtrl)

Package

00000000h

48318h

4

DP Config (DP_​3_​2_​B1_​Config)

Package

00000000h

4831ch

4

DP ChannelEn (DP_​3_​2_​B1_​ChannelEn)

Package

00000000h

48320h

4

DP SampleCtrl (DP_​3_​2_​B1_​SampleCtrl)

Package

00000000h

48324h

4

DP OffsetCtrl (DP_​3_​2_​B1_​OffsetCtrl)

Package

00000000h

48328h

4

DP HCtrl (DP_​3_​2_​B1_​HCtrl)

Package

00000000h

4832ch

4

DP AsyncCtrl (DP_​3_​2_​B1_​AsyncCtrl)

Package

00000000h

48330h

4

DP Port Ctrl (DP_​3_​2_​Port_​Ctrl)

Package

00000000h

48380h

4

DP Config (DP_​3_​3_​B0_​Config)

Package

00000000h

48384h

4

DP ChannelEn (DP_​3_​3_​B0_​ChannelEn)

Package

00000000h

48388h

4

DP SampleCtrl (DP_​3_​3_​B0_​SampleCtrl)

Package

00000000h

4838ch

4

DP OffsetCtrl (DP_​3_​3_​B0_​OffsetCtrl)

Package

00000000h

48390h

4

DP HCtrl (DP_​3_​3_​B0_​HCtrl)

Package

00000000h

48394h

4

DP AsyncCtrl (DP_​3_​3_​B0_​AsyncCtrl)

Package

00000000h

48398h

4

DP Config (DP_​3_​3_​B1_​Config)

Package

00000000h

4839ch

4

DP ChannelEn (DP_​3_​3_​B1_​ChannelEn)

Package

00000000h

483a0h

4

DP SampleCtrl (DP_​3_​3_​B1_​SampleCtrl)

Package

00000000h

483a4h

4

DP OffsetCtrl (DP_​3_​3_​B1_​OffsetCtrl)

Package

00000000h

483a8h

4

DP HCtrl (DP_​3_​3_​B1_​HCtrl)

Package

00000000h

483ach

4

DP AsyncCtrl (DP_​3_​3_​B1_​AsyncCtrl)

Package

00000000h

483b0h

4

DP Port Ctrl (DP_​3_​3_​Port_​Ctrl)

Package

00000000h

48400h

4

DP Config (DP_​3_​4_​B0_​Config)

Package

00000000h

48404h

4

DP ChannelEn (DP_​3_​4_​B0_​ChannelEn)

Package

00000000h

48408h

4

DP SampleCtrl (DP_​3_​4_​B0_​SampleCtrl)

Package

00000000h

4840ch

4

DP OffsetCtrl (DP_​3_​4_​B0_​OffsetCtrl)

Package

00000000h

48410h

4

DP HCtrl (DP_​3_​4_​B0_​HCtrl)

Package

00000000h

48414h

4

DP AsyncCtrl (DP_​3_​4_​B0_​AsyncCtrl)

Package

00000000h

48418h

4

DP Config (DP_​3_​4_​B1_​Config)

Package

00000000h

4841ch

4

DP ChannelEn (DP_​3_​4_​B1_​ChannelEn)

Package

00000000h

48420h

4

DP SampleCtrl (DP_​3_​4_​B1_​SampleCtrl)

Package

00000000h

48424h

4

DP OffsetCtrl (DP_​3_​4_​B1_​OffsetCtrl)

Package

00000000h

48428h

4

DP HCtrl (DP_​3_​4_​B1_​HCtrl)

Package

00000000h

4842ch

4

DP AsyncCtrl (DP_​3_​4_​B1_​AsyncCtrl)

Package

00000000h

48430h

4

DP Port Ctrl (DP_​3_​4_​Port_​Ctrl)

Package

00000000h

48480h

4

DP Config (DP_​3_​5_​B0_​Config)

Package

00000000h

48484h

4

DP ChannelEn (DP_​3_​5_​B0_​ChannelEn)

Package

00000000h

48488h

4

DP SampleCtrl (DP_​3_​5_​B0_​SampleCtrl)

Package

00000000h

4848ch

4

DP OffsetCtrl (DP_​3_​5_​B0_​OffsetCtrl)

Package

00000000h

48490h

4

DP HCtrl (DP_​3_​5_​B0_​HCtrl)

Package

00000000h

48494h

4

DP AsyncCtrl (DP_​3_​5_​B0_​AsyncCtrl)

Package

00000000h

48498h

4

DP Config (DP_​3_​5_​B1_​Config)

Package

00000000h

4849ch

4

DP ChannelEn (DP_​3_​5_​B1_​ChannelEn)

Package

00000000h

484a0h

4

DP SampleCtrl (DP_​3_​5_​B1_​SampleCtrl)

Package

00000000h

484a4h

4

DP OffsetCtrl (DP_​3_​5_​B1_​OffsetCtrl)

Package

00000000h

484a8h

4

DP HCtrl (DP_​3_​5_​B1_​HCtrl)

Package

00000000h

484ach

4

DP AsyncCtrl (DP_​3_​5_​B1_​AsyncCtrl)

Package

00000000h

484b0h

4

DP Port Ctrl (DP_​3_​5_​Port_​Ctrl)

Package

00000000h

48500h

4

DP Config (DP_​3_​6_​B0_​Config)

Package

00000000h

48504h

4

DP ChannelEn (DP_​3_​6_​B0_​ChannelEn)

Package

00000000h

48508h

4

DP SampleCtrl (DP_​3_​6_​B0_​SampleCtrl)

Package

00000000h

4850ch

4

DP OffsetCtrl (DP_​3_​6_​B0_​OffsetCtrl)

Package

00000000h

48510h

4

DP HCtrl (DP_​3_​6_​B0_​HCtrl)

Package

00000000h

48514h

4

DP AsyncCtrl (DP_​3_​6_​B0_​AsyncCtrl)

Package

00000000h

48518h

4

DP Config (DP_​3_​6_​B1_​Config)

Package

00000000h

4851ch

4

DP ChannelEn (DP_​3_​6_​B1_​ChannelEn)

Package

00000000h

48520h

4

DP SampleCtrl (DP_​3_​6_​B1_​SampleCtrl)

Package

00000000h

48524h

4

DP OffsetCtrl (DP_​3_​6_​B1_​OffsetCtrl)

Package

00000000h

48528h

4

DP HCtrl (DP_​3_​6_​B1_​HCtrl)

Package

00000000h

4852ch

4

DP AsyncCtrl (DP_​3_​6_​B1_​AsyncCtrl)

Package

00000000h

48530h

4

DP Port Ctrl (DP_​3_​6_​Port_​Ctrl)

Package

00000000h

48580h

4

DP Config (DP_​3_​7_​B0_​Config)

Package

00000000h

48584h

4

DP ChannelEn (DP_​3_​7_​B0_​ChannelEn)

Package

00000000h

48588h

4

DP SampleCtrl (DP_​3_​7_​B0_​SampleCtrl)

Package

00000000h

4858ch

4

DP OffsetCtrl (DP_​3_​7_​B0_​OffsetCtrl)

Package

00000000h

48590h

4

DP HCtrl (DP_​3_​7_​B0_​HCtrl)

Package

00000000h

48594h

4

DP AsyncCtrl (DP_​3_​7_​B0_​AsyncCtrl)

Package

00000000h

48598h

4

DP Config (DP_​3_​7_​B1_​Config)

Package

00000000h

4859ch

4

DP ChannelEn (DP_​3_​7_​B1_​ChannelEn)

Package

00000000h

485a0h

4

DP SampleCtrl (DP_​3_​7_​B1_​SampleCtrl)

Package

00000000h

485a4h

4

DP OffsetCtrl (DP_​3_​7_​B1_​OffsetCtrl)

Package

00000000h

485a8h

4

DP HCtrl (DP_​3_​7_​B1_​HCtrl)

Package

00000000h

485ach

4

DP AsyncCtrl (DP_​3_​7_​B1_​AsyncCtrl)

Package

00000000h

485b0h

4

DP Port Ctrl (DP_​3_​7_​Port_​Ctrl)

Package

00000000h

48600h

4

DP Config (DP_​3_​8_​B0_​Config)

Package

00000000h

48604h

4

DP ChannelEn (DP_​3_​8_​B0_​ChannelEn)

Package

00000000h

48608h

4

DP SampleCtrl (DP_​3_​8_​B0_​SampleCtrl)

Package

00000000h

4860ch

4

DP OffsetCtrl (DP_​3_​8_​B0_​OffsetCtrl)

Package

00000000h

48610h

4

DP HCtrl (DP_​3_​8_​B0_​HCtrl)

Package

00000000h

48614h

4

DP AsyncCtrl (DP_​3_​8_​B0_​AsyncCtrl)

Package

00000000h

48618h

4

DP Config (DP_​3_​8_​B1_​Config)

Package

00000000h

4861ch

4

DP ChannelEn (DP_​3_​8_​B1_​ChannelEn)

Package

00000000h

48620h

4

DP SampleCtrl (DP_​3_​8_​B1_​SampleCtrl)

Package

00000000h

48624h

4

DP OffsetCtrl (DP_​3_​8_​B1_​OffsetCtrl)

Package

00000000h

48628h

4

DP HCtrl (DP_​3_​8_​B1_​HCtrl)

Package

00000000h

4862ch

4

DP AsyncCtrl (DP_​3_​8_​B1_​AsyncCtrl)

Package

00000000h

48630h

4

DP Port Ctrl (DP_​3_​8_​Port_​Ctrl)

Package

00000000h

48680h

4

DP Config (DP_​3_​9_​B0_​Config)

Package

00000000h

48684h

4

DP ChannelEn (DP_​3_​9_​B0_​ChannelEn)

Package

00000000h

48688h

4

DP SampleCtrl (DP_​3_​9_​B0_​SampleCtrl)

Package

00000000h

4868ch

4

DP OffsetCtrl (DP_​3_​9_​B0_​OffsetCtrl)

Package

00000000h

48690h

4

DP HCtrl (DP_​3_​9_​B0_​HCtrl)

Package

00000000h

48694h

4

DP AsyncCtrl (DP_​3_​9_​B0_​AsyncCtrl)

Package

00000000h

48698h

4

DP Config (DP_​3_​9_​B1_​Config)

Package

00000000h

4869ch

4

DP ChannelEn (DP_​3_​9_​B1_​ChannelEn)

Package

00000000h

486a0h

4

DP SampleCtrl (DP_​3_​9_​B1_​SampleCtrl)

Package

00000000h

486a4h

4

DP OffsetCtrl (DP_​3_​9_​B1_​OffsetCtrl)

Package

00000000h

486a8h

4

DP HCtrl (DP_​3_​9_​B1_​HCtrl)

Package

00000000h

486ach

4

DP AsyncCtrl (DP_​3_​9_​B1_​AsyncCtrl)

Package

00000000h

486b0h

4

DP Port Ctrl (DP_​3_​9_​Port_​Ctrl)

Package

00000000h

48700h

4

DP Config (DP_​3_​10_​B0_​Config)

Package

00000000h

48704h

4

DP ChannelEn (DP_​3_​10_​B0_​ChannelEn)

Package

00000000h

48708h

4

DP SampleCtrl (DP_​3_​10_​B0_​SampleCtrl)

Package

00000000h

4870ch

4

DP OffsetCtrl (DP_​3_​10_​B0_​OffsetCtrl)

Package

00000000h

48710h

4

DP HCtrl (DP_​3_​10_​B0_​HCtrl)

Package

00000000h

48714h

4

DP AsyncCtrl (DP_​3_​10_​B0_​AsyncCtrl)

Package

00000000h

48718h

4

DP Config (DP_​3_​10_​B1_​Config)

Package

00000000h

4871ch

4

DP ChannelEn (DP_​3_​10_​B1_​ChannelEn)

Package

00000000h

48720h

4

DP SampleCtrl (DP_​3_​10_​B1_​SampleCtrl)

Package

00000000h

48724h

4

DP OffsetCtrl (DP_​3_​10_​B1_​OffsetCtrl)

Package

00000000h

48728h

4

DP HCtrl (DP_​3_​10_​B1_​HCtrl)

Package

00000000h

4872ch

4

DP AsyncCtrl (DP_​3_​10_​B1_​AsyncCtrl)

Package

00000000h

48730h

4

DP Port Ctrl (DP_​3_​10_​Port_​Ctrl)

Package

00000000h

48780h

4

DP Config (DP_​3_​11_​B0_​Config)

Package

00000000h

48784h

4

DP ChannelEn (DP_​3_​11_​B0_​ChannelEn)

Package

00000000h

48788h

4

DP SampleCtrl (DP_​3_​11_​B0_​SampleCtrl)

Package

00000000h

4878ch

4

DP OffsetCtrl (DP_​3_​11_​B0_​OffsetCtrl)

Package

00000000h

48790h

4

DP HCtrl (DP_​3_​11_​B0_​HCtrl)

Package

00000000h

48794h

4

DP AsyncCtrl (DP_​3_​11_​B0_​AsyncCtrl)

Package

00000000h

48798h

4

DP Config (DP_​3_​11_​B1_​Config)

Package

00000000h

4879ch

4

DP ChannelEn (DP_​3_​11_​B1_​ChannelEn)

Package

00000000h

487a0h

4

DP SampleCtrl (DP_​3_​11_​B1_​SampleCtrl)

Package

00000000h

487a4h

4

DP OffsetCtrl (DP_​3_​11_​B1_​OffsetCtrl)

Package

00000000h

487a8h

4

DP HCtrl (DP_​3_​11_​B1_​HCtrl)

Package

00000000h

487ach

4

DP AsyncCtrl (DP_​3_​11_​B1_​AsyncCtrl)

Package

00000000h

487b0h

4

DP Port Ctrl (DP_​3_​11_​Port_​Ctrl)

Package

00000000h

48800h

4

DP Config (DP_​3_​12_​B0_​Config)

Package

00000000h

48804h

4

DP ChannelEn (DP_​3_​12_​B0_​ChannelEn)

Package

00000000h

48808h

4

DP SampleCtrl (DP_​3_​12_​B0_​SampleCtrl)

Package

00000000h

4880ch

4

DP OffsetCtrl (DP_​3_​12_​B0_​OffsetCtrl)

Package

00000000h

48810h

4

DP HCtrl (DP_​3_​12_​B0_​HCtrl)

Package

00000000h

48814h

4

DP AsyncCtrl (DP_​3_​12_​B0_​AsyncCtrl)

Package

00000000h

48818h

4

DP Config (DP_​3_​12_​B1_​Config)

Package

00000000h

4881ch

4

DP ChannelEn (DP_​3_​12_​B1_​ChannelEn)

Package

00000000h

48820h

4

DP SampleCtrl (DP_​3_​12_​B1_​SampleCtrl)

Package

00000000h

48824h

4

DP OffsetCtrl (DP_​3_​12_​B1_​OffsetCtrl)

Package

00000000h

48828h

4

DP HCtrl (DP_​3_​12_​B1_​HCtrl)

Package

00000000h

4882ch

4

DP AsyncCtrl (DP_​3_​12_​B1_​AsyncCtrl)

Package

00000000h

48830h

4

DP Port Ctrl (DP_​3_​12_​Port_​Ctrl)

Package

00000000h

48880h

4

DP Config (DP_​3_​13_​B0_​Config)

Package

00000000h

48884h

4

DP ChannelEn (DP_​3_​13_​B0_​ChannelEn)

Package

00000000h

48888h

4

DP SampleCtrl (DP_​3_​13_​B0_​SampleCtrl)

Package

00000000h

4888ch

4

DP OffsetCtrl (DP_​3_​13_​B0_​OffsetCtrl)

Package

00000000h

48890h

4

DP HCtrl (DP_​3_​13_​B0_​HCtrl)

Package

00000000h

48894h

4

DP AsyncCtrl (DP_​3_​13_​B0_​AsyncCtrl)

Package

00000000h

48898h

4

DP Config (DP_​3_​13_​B1_​Config)

Package

00000000h

4889ch

4

DP ChannelEn (DP_​3_​13_​B1_​ChannelEn)

Package

00000000h

488a0h

4

DP SampleCtrl (DP_​3_​13_​B1_​SampleCtrl)

Package

00000000h

488a4h

4

DP OffsetCtrl (DP_​3_​13_​B1_​OffsetCtrl)

Package

00000000h

488a8h

4

DP HCtrl (DP_​3_​13_​B1_​HCtrl)

Package

00000000h

488ach

4

DP AsyncCtrl (DP_​3_​13_​B1_​AsyncCtrl)

Package

00000000h

488b0h

4

DP Port Ctrl (DP_​3_​13_​Port_​Ctrl)

Package

00000000h

48900h

4

DP Config (DP_​3_​14_​B0_​Config)

Package

00000000h

48904h

4

DP ChannelEn (DP_​3_​14_​B0_​ChannelEn)

Package

00000000h

48908h

4

DP SampleCtrl (DP_​3_​14_​B0_​SampleCtrl)

Package

00000000h

4890ch

4

DP OffsetCtrl (DP_​3_​14_​B0_​OffsetCtrl)

Package

00000000h

48910h

4

DP HCtrl (DP_​3_​14_​B0_​HCtrl)

Package

00000000h

48914h

4

DP AsyncCtrl (DP_​3_​14_​B0_​AsyncCtrl)

Package

00000000h

48918h

4

DP Config (DP_​3_​14_​B1_​Config)

Package

00000000h

4891ch

4

DP ChannelEn (DP_​3_​14_​B1_​ChannelEn)

Package

00000000h

48920h

4

DP SampleCtrl (DP_​3_​14_​B1_​SampleCtrl)

Package

00000000h

48924h

4

DP OffsetCtrl (DP_​3_​14_​B1_​OffsetCtrl)

Package

00000000h

48928h

4

DP HCtrl (DP_​3_​14_​B1_​HCtrl)

Package

00000000h

4892ch

4

DP AsyncCtrl (DP_​3_​14_​B1_​AsyncCtrl)

Package

00000000h

48930h

4

DP Port Ctrl (DP_​3_​14_​Port_​Ctrl)

Package

00000000h

49200h

4

PDI Config (PDI_​3_​0_​Config)

Package

00000000h

49210h

4

PDI Config (PDI_​3_​1_​Config)

Package

00000000h

49220h

4

PDI Config (PDI_​3_​2_​Config)

Package

00000000h

49230h

4

PDI Config (PDI_​3_​3_​Config)

Package

00000000h

49240h

4

PDI Config (PDI_​3_​4_​Config)

Package

00000000h

49250h

4

PDI Config (PDI_​3_​5_​Config)

Package

00000000h

49260h

4

PDI Config (PDI_​3_​6_​Config)

Package

00000000h

49270h

4

PDI Config (PDI_​3_​7_​Config)

Package

00000000h

49280h

4

PDI Config (PDI_​3_​8_​Config)

Package

00000000h

49290h

4

PDI Config (PDI_​3_​9_​Config)

Package

00000000h

492a0h

4

PDI Config (PDI_​3_​10_​Config)

Package

00000000h

492b0h

4

PDI Config (PDI_​3_​11_​Config)

Package

00000000h

492c0h

4

PDI Config (PDI_​3_​12_​Config)

Package

00000000h

492d0h

4

PDI Config (PDI_​3_​13_​Config)

Package

00000000h

492e0h

4

PDI Config (PDI_​3_​14_​Config)

Package

00000000h

492f0h

4

PDI Config (PDI_​3_​15_​Config)

Package

00000000h

4c100h

4

IP MCP Config (IP_​MCP_​3_​Config)

Package

001F0005h

4c104h

4

IP MCP Control (IP_​MCP_​3_​Control)

Package

00000000h

4c108h

4

IP MCP CmdCtrl (IP_​MCP_​3_​CmdCtrl)

Package

00000000h

4c11ch

4

IP MCP PHYCtrl (IP_​MCP_​3_​PHYCtrl)

Package

00000000h

4c130h

4

IP MCP B0_​ClockCtrl (IP_​MCP_​3_​B0_​ClockCtrl)

Package

00000000h

4c140h

4

IP MCP Stat (IP_​MCP_​3_​Stat)

Package

00000000h

4c14ch

4

IP MCP IntSet (IP_​MCP_​3_​IntSet)

Package

00000000h

4c180h

4

IP MCP Command (IP_​MCP_​3_​Command)

Package

00000000h

4e004h

4

SoundWire x Link Vendor Specific Control (SNDW3LVSCTL)

Package

00000000h

4e008h

2

SoundWire x Wake Enable (SNDW3WAKEEN)

Package

0000h

4e00ah

2

SoundWire x Wake Status (SNDW3WAKESTS)

Package

0000h

4e00ch

2

SoundWire x I/O Control (SNDW3IOCTL)

Package

0004h

4e00eh

2

SoundWire x AC Timing Control (SNDW3ACTMCTL)

Package

003Ah

4e010h

2

SoundWire x Microphone Privacy Control & Status (SNDW3PVCCS)

Package

0000h

50000h

4

SoundWire x Link Extended Capability (SNDW4LECAP)

Package

00000008h

50010h

2

SoundWire x PCM Stream Capabilities (SNDW4PCMSCAP)

Package

0F00h

50014h

2

SoundWire PCM Stream y Channel Count (SNDW4PCMS0CHC)

Package

0007h

50016h

2

SoundWire x PCM Stream y Channel Map (SNDW4PCMS0CM)

Package

00F0h

50018h

2

SoundWire PCM Stream y Channel Count (SNDW4PCMS1CHC)

Package

0007h

5001ah

2

SoundWire x PCM Stream y Channel Map (SNDW4PCMS1CM)

Package

00F0h

5001ch

2

SoundWire PCM Stream y Channel Count (SNDW4PCMS2CHC)

Package

0007h

5001eh

2

SoundWire x PCM Stream y Channel Map (SNDW4PCMS2CM)

Package

00F0h

50020h

2

SoundWire PCM Stream y Channel Count (SNDW4PCMS3CHC)

Package

0007h

50022h

2

SoundWire x PCM Stream y Channel Map (SNDW4PCMS3CM)

Package

00F0h

50024h

2

SoundWire PCM Stream y Channel Count (SNDW4PCMS4CHC)

Package

0007h

50026h

2

SoundWire x PCM Stream y Channel Map (SNDW4PCMS4CM)

Package

00F0h

50028h

2

SoundWire PCM Stream y Channel Count (SNDW4PCMS5CHC)

Package

0007h

5002ah

2

SoundWire x PCM Stream y Channel Map (SNDW4PCMS5CM)

Package

00F0h

5002ch

2

SoundWire PCM Stream y Channel Count (SNDW4PCMS6CHC)

Package

0007h

5002eh

2

SoundWire x PCM Stream y Channel Map (SNDW4PCMS6CM)

Package

00F0h

50030h

2

SoundWire PCM Stream y Channel Count (SNDW4PCMS7CHC)

Package

0007h

50032h

2

SoundWire x PCM Stream y Channel Map (SNDW4PCMS7CM)

Package

00F0h

50034h

2

SoundWire PCM Stream y Channel Count (SNDW4PCMS8CHC)

Package

0007h

50036h

2

SoundWire x PCM Stream y Channel Map (SNDW4PCMS8CM)

Package

00F0h

50038h

2

SoundWire PCM Stream y Channel Count (SNDW4PCMS9CHC)

Package

0007h

5003ah

2

SoundWire x PCM Stream y Channel Map (SNDW4PCMS9CM)

Package

00F0h

5003ch

2

SoundWire PCM Stream y Channel Count (SNDW4PCMS10CHC)

Package

0007h

5003eh

2

SoundWire x PCM Stream y Channel Map (SNDW4PCMS10CM)

Package

00F0h

50040h

2

SoundWire PCM Stream y Channel Count (SNDW4PCMS11CHC)

Package

0007h

50042h

2

SoundWire x PCM Stream y Channel Map (SNDW4PCMS11CM)

Package

00F0h

50044h

2

SoundWire PCM Stream y Channel Count (SNDW4PCMS12CHC)

Package

0007h

50046h

2

SoundWire x PCM Stream y Channel Map (SNDW4PCMS12CM)

Package

00F0h

50048h

2

SoundWire PCM Stream y Channel Count (SNDW4PCMS13CHC)

Package

0007h

5004ah

2

SoundWire x PCM Stream y Channel Map (SNDW4PCMS13CM)

Package

00F0h

5004ch

2

SoundWire PCM Stream y Channel Count (SNDW4PCMS14CHC)

Package

0007h

5004eh

2

SoundWire x PCM Stream y Channel Map (SNDW4PCMS14CM)

Package

00F0h

50050h

2

SoundWire PCM Stream y Channel Count (SNDW4PCMS15CHC)

Package

0007h

50052h

2

SoundWire x PCM Stream y Channel Map (SNDW4PCMS15CM)

Package

00F0h

50100h

4

MCP Config (MCP_​4_​Config)

Package

00000000h

50104h

4

MCP Control (MCP_​4_​Control)

Package

00000000h

5010ch

4

MCP SSPStat (MCP_​4_​SSPStat)

Package

00000000h

50110h

4

MCP FrameShape (MCP_​4_​FrameShape)

Package

00000000h

50114h

4

MCP FrameShapeInit (MCP_​4_​FrameShapeInit)

Package

00000000h

50118h

4

MCP ConfigUpdate (MCP_​4_​ConfigUpdate)

Package

00000000h

50120h

4

MCP SSPCtrl (MCP_​4_​B0_​SSPCtrl)

Package

00000000h

50128h

4

MCP SSPCtrl (MCP_​4_​B1_​SSPCtrl)

Package

00000000h

50130h

4

MCP ClockCtrl (MCP_​4_​B0_​ClockCtrl)

Package

00000000h

50138h

4

MCP ClockCtrl (MCP_​4_​B1_​ClockCtrl)

Package

00000000h

50140h

4

MCP Stat (MCP_​4_​Stat)

Package

00000002h

50144h

4

MCP IntStat (MCP_​4_​IntStat)

Package

00000000h

50148h

4

MCP IntMask (MCP_​4_​IntMask)

Package

00000000h

50150h

4

MCP PeripheryStat (MCP_​4_​PeripheryStat)

Package

00000000h

50154h

4

MCP PeripheryIntStat0 (MCP_​4_​PeripheryIntStat0)

Package

00000000h

50158h

4

MCP PeripheryIntStat1 (MCP_​4_​PeripheryIntStat1)

Package

00000000h

5015ch

4

MCP PeripheryIntMask0 (MCP_​4_​PeripheryIntMask0)

Package

00000000h

50160h

4

MCP PeripheryIntMask1 (MCP_​4_​PeripheryIntMask1)

Package

00000000h

50164h

4

MCP PortIntStat (MCP_​4_​PortIntStat)

Package

00000000h

5016ch

4

MCP PDIStat (MCP_​4_​PDIStat)

Package

00000000h

50178h

4

MCP FIFOLevel (MCP_​4_​FIFOLevel)

Package

00000002h

5017ch

4

MCP FIFOStat (MCP_​4_​FIFOStat)

Package

00000800h

50200h

4

DP Config (DP_​4_​0_​B0_​Config)

Package

00000000h

50204h

4

DP ChannelEn (DP_​4_​0_​B0_​ChannelEn)

Package

00000000h

50208h

4

DP SampleCtrl (DP_​4_​0_​B0_​SampleCtrl)

Package

00000000h

5020ch

4

DP OffsetCtrl (DP_​4_​0_​B0_​OffsetCtrl)

Package

00000000h

50210h

4

DP HCtrl (DP_​4_​0_​B0_​HCtrl)

Package

00000000h

50214h

4

DP AsyncCtrl (DP_​4_​0_​B0_​AsyncCtrl)

Package

00000000h

50218h

4

DP Config (DP_​4_​0_​B1_​Config)

Package

00000000h

5021ch

4

DP ChannelEn (DP_​4_​0_​B1_​ChannelEn)

Package

00000000h

50220h

4

DP SampleCtrl (DP_​4_​0_​B1_​SampleCtrl)

Package

00000000h

50224h

4

DP OffsetCtrl (DP_​4_​0_​B1_​OffsetCtrl)

Package

00000000h

50228h

4

DP HCtrl (DP_​4_​0_​B1_​HCtrl)

Package

00000000h

5022ch

4

DP AsyncCtrl (DP_​4_​0_​B1_​AsyncCtrl)

Package

00000000h

50230h

4

DP Port Ctrl (DP_​4_​0_​Port_​Ctrl)

Package

00000000h

50280h

4

DP Config (DP_​4_​1_​B0_​Config)

Package

00000000h

50284h

4

DP ChannelEn (DP_​4_​1_​B0_​ChannelEn)

Package

00000000h

50288h

4

DP SampleCtrl (DP_​4_​1_​B0_​SampleCtrl)

Package

00000000h

5028ch

4

DP OffsetCtrl (DP_​4_​1_​B0_​OffsetCtrl)

Package

00000000h

50290h

4

DP HCtrl (DP_​4_​1_​B0_​HCtrl)

Package

00000000h

50294h

4

DP AsyncCtrl (DP_​4_​1_​B0_​AsyncCtrl)

Package

00000000h

50298h

4

DP Config (DP_​4_​1_​B1_​Config)

Package

00000000h

5029ch

4

DP ChannelEn (DP_​4_​1_​B1_​ChannelEn)

Package

00000000h

502a0h

4

DP SampleCtrl (DP_​4_​1_​B1_​SampleCtrl)

Package

00000000h

502a4h

4

DP OffsetCtrl (DP_​4_​1_​B1_​OffsetCtrl)

Package

00000000h

502a8h

4

DP HCtrl (DP_​4_​1_​B1_​HCtrl)

Package

00000000h

502ach

4

DP AsyncCtrl (DP_​4_​1_​B1_​AsyncCtrl)

Package

00000000h

502b0h

4

DP Port Ctrl (DP_​4_​1_​Port_​Ctrl)

Package

00000000h

50300h

4

DP Config (DP_​4_​2_​B0_​Config)

Package

00000000h

50304h

4

DP ChannelEn (DP_​4_​2_​B0_​ChannelEn)

Package

00000000h

50308h

4

DP SampleCtrl (DP_​4_​2_​B0_​SampleCtrl)

Package

00000000h

5030ch

4

DP OffsetCtrl (DP_​4_​2_​B0_​OffsetCtrl)

Package

00000000h

50310h

4

DP HCtrl (DP_​4_​2_​B0_​HCtrl)

Package

00000000h

50314h

4

DP AsyncCtrl (DP_​4_​2_​B0_​AsyncCtrl)

Package

00000000h

50318h

4

DP Config (DP_​4_​2_​B1_​Config)

Package

00000000h

5031ch

4

DP ChannelEn (DP_​4_​2_​B1_​ChannelEn)

Package

00000000h

50320h

4

DP SampleCtrl (DP_​4_​2_​B1_​SampleCtrl)

Package

00000000h

50324h

4

DP OffsetCtrl (DP_​4_​2_​B1_​OffsetCtrl)

Package

00000000h

50328h

4

DP HCtrl (DP_​4_​2_​B1_​HCtrl)

Package

00000000h

5032ch

4

DP AsyncCtrl (DP_​4_​2_​B1_​AsyncCtrl)

Package

00000000h

50330h

4

DP Port Ctrl (DP_​4_​2_​Port_​Ctrl)

Package

00000000h

50380h

4

DP Config (DP_​4_​3_​B0_​Config)

Package

00000000h

50384h

4

DP ChannelEn (DP_​4_​3_​B0_​ChannelEn)

Package

00000000h

50388h

4

DP SampleCtrl (DP_​4_​3_​B0_​SampleCtrl)

Package

00000000h

5038ch

4

DP OffsetCtrl (DP_​4_​3_​B0_​OffsetCtrl)

Package

00000000h

50390h

4

DP HCtrl (DP_​4_​3_​B0_​HCtrl)

Package

00000000h

50394h

4

DP AsyncCtrl (DP_​4_​3_​B0_​AsyncCtrl)

Package

00000000h

50398h

4

DP Config (DP_​4_​3_​B1_​Config)

Package

00000000h

5039ch

4

DP ChannelEn (DP_​4_​3_​B1_​ChannelEn)

Package

00000000h

503a0h

4

DP SampleCtrl (DP_​4_​3_​B1_​SampleCtrl)

Package

00000000h

503a4h

4

DP OffsetCtrl (DP_​4_​3_​B1_​OffsetCtrl)

Package

00000000h

503a8h

4

DP HCtrl (DP_​4_​3_​B1_​HCtrl)

Package

00000000h

503ach

4

DP AsyncCtrl (DP_​4_​3_​B1_​AsyncCtrl)

Package

00000000h

503b0h

4

DP Port Ctrl (DP_​4_​3_​Port_​Ctrl)

Package

00000000h

50400h

4

DP Config (DP_​4_​4_​B0_​Config)

Package

00000000h

50404h

4

DP ChannelEn (DP_​4_​4_​B0_​ChannelEn)

Package

00000000h

50408h

4

DP SampleCtrl (DP_​4_​4_​B0_​SampleCtrl)

Package

00000000h

5040ch

4

DP OffsetCtrl (DP_​4_​4_​B0_​OffsetCtrl)

Package

00000000h

50410h

4

DP HCtrl (DP_​4_​4_​B0_​HCtrl)

Package

00000000h

50414h

4

DP AsyncCtrl (DP_​4_​4_​B0_​AsyncCtrl)

Package

00000000h

50418h

4

DP Config (DP_​4_​4_​B1_​Config)

Package

00000000h

5041ch

4

DP ChannelEn (DP_​4_​4_​B1_​ChannelEn)

Package

00000000h

50420h

4

DP SampleCtrl (DP_​4_​4_​B1_​SampleCtrl)

Package

00000000h

50424h

4

DP OffsetCtrl (DP_​4_​4_​B1_​OffsetCtrl)

Package

00000000h

50428h

4

DP HCtrl (DP_​4_​4_​B1_​HCtrl)

Package

00000000h

5042ch

4

DP AsyncCtrl (DP_​4_​4_​B1_​AsyncCtrl)

Package

00000000h

50430h

4

DP Port Ctrl (DP_​4_​4_​Port_​Ctrl)

Package

00000000h

50480h

4

DP Config (DP_​4_​5_​B0_​Config)

Package

00000000h

50484h

4

DP ChannelEn (DP_​4_​5_​B0_​ChannelEn)

Package

00000000h

50488h

4

DP SampleCtrl (DP_​4_​5_​B0_​SampleCtrl)

Package

00000000h

5048ch

4

DP OffsetCtrl (DP_​4_​5_​B0_​OffsetCtrl)

Package

00000000h

50490h

4

DP HCtrl (DP_​4_​5_​B0_​HCtrl)

Package

00000000h

50494h

4

DP AsyncCtrl (DP_​4_​5_​B0_​AsyncCtrl)

Package

00000000h

50498h

4

DP Config (DP_​4_​5_​B1_​Config)

Package

00000000h

5049ch

4

DP ChannelEn (DP_​4_​5_​B1_​ChannelEn)

Package

00000000h

504a0h

4

DP SampleCtrl (DP_​4_​5_​B1_​SampleCtrl)

Package

00000000h

504a4h

4

DP OffsetCtrl (DP_​4_​5_​B1_​OffsetCtrl)

Package

00000000h

504a8h

4

DP HCtrl (DP_​4_​5_​B1_​HCtrl)

Package

00000000h

504ach

4

DP AsyncCtrl (DP_​4_​5_​B1_​AsyncCtrl)

Package

00000000h

504b0h

4

DP Port Ctrl (DP_​4_​5_​Port_​Ctrl)

Package

00000000h

50500h

4

DP Config (DP_​4_​6_​B0_​Config)

Package

00000000h

50504h

4

DP ChannelEn (DP_​4_​6_​B0_​ChannelEn)

Package

00000000h

50508h

4

DP SampleCtrl (DP_​4_​6_​B0_​SampleCtrl)

Package

00000000h

5050ch

4

DP OffsetCtrl (DP_​4_​6_​B0_​OffsetCtrl)

Package

00000000h

50510h

4

DP HCtrl (DP_​4_​6_​B0_​HCtrl)

Package

00000000h

50514h

4

DP AsyncCtrl (DP_​4_​6_​B0_​AsyncCtrl)

Package

00000000h

50518h

4

DP Config (DP_​4_​6_​B1_​Config)

Package

00000000h

5051ch

4

DP ChannelEn (DP_​4_​6_​B1_​ChannelEn)

Package

00000000h

50520h

4

DP SampleCtrl (DP_​4_​6_​B1_​SampleCtrl)

Package

00000000h

50524h

4

DP OffsetCtrl (DP_​4_​6_​B1_​OffsetCtrl)

Package

00000000h

50528h

4

DP HCtrl (DP_​4_​6_​B1_​HCtrl)

Package

00000000h

5052ch

4

DP AsyncCtrl (DP_​4_​6_​B1_​AsyncCtrl)

Package

00000000h

50530h

4

DP Port Ctrl (DP_​4_​6_​Port_​Ctrl)

Package

00000000h

50580h

4

DP Config (DP_​4_​7_​B0_​Config)

Package

00000000h

50584h

4

DP ChannelEn (DP_​4_​7_​B0_​ChannelEn)

Package

00000000h

50588h

4

DP SampleCtrl (DP_​4_​7_​B0_​SampleCtrl)

Package

00000000h

5058ch

4

DP OffsetCtrl (DP_​4_​7_​B0_​OffsetCtrl)

Package

00000000h

50590h

4

DP HCtrl (DP_​4_​7_​B0_​HCtrl)

Package

00000000h

50594h

4

DP AsyncCtrl (DP_​4_​7_​B0_​AsyncCtrl)

Package

00000000h

50598h

4

DP Config (DP_​4_​7_​B1_​Config)

Package

00000000h

5059ch

4

DP ChannelEn (DP_​4_​7_​B1_​ChannelEn)

Package

00000000h

505a0h

4

DP SampleCtrl (DP_​4_​7_​B1_​SampleCtrl)

Package

00000000h

505a4h

4

DP OffsetCtrl (DP_​4_​7_​B1_​OffsetCtrl)

Package

00000000h

505a8h

4

DP HCtrl (DP_​4_​7_​B1_​HCtrl)

Package

00000000h

505ach

4

DP AsyncCtrl (DP_​4_​7_​B1_​AsyncCtrl)

Package

00000000h

505b0h

4

DP Port Ctrl (DP_​4_​7_​Port_​Ctrl)

Package

00000000h

50600h

4

DP Config (DP_​4_​8_​B0_​Config)

Package

00000000h

50604h

4

DP ChannelEn (DP_​4_​8_​B0_​ChannelEn)

Package

00000000h

50608h

4

DP SampleCtrl (DP_​4_​8_​B0_​SampleCtrl)

Package

00000000h

5060ch

4

DP OffsetCtrl (DP_​4_​8_​B0_​OffsetCtrl)

Package

00000000h

50610h

4

DP HCtrl (DP_​4_​8_​B0_​HCtrl)

Package

00000000h

50614h

4

DP AsyncCtrl (DP_​4_​8_​B0_​AsyncCtrl)

Package

00000000h

50618h

4

DP Config (DP_​4_​8_​B1_​Config)

Package

00000000h

5061ch

4

DP ChannelEn (DP_​4_​8_​B1_​ChannelEn)

Package

00000000h

50620h

4

DP SampleCtrl (DP_​4_​8_​B1_​SampleCtrl)

Package

00000000h

50624h

4

DP OffsetCtrl (DP_​4_​8_​B1_​OffsetCtrl)

Package

00000000h

50628h

4

DP HCtrl (DP_​4_​8_​B1_​HCtrl)

Package

00000000h

5062ch

4

DP AsyncCtrl (DP_​4_​8_​B1_​AsyncCtrl)

Package

00000000h

50630h

4

DP Port Ctrl (DP_​4_​8_​Port_​Ctrl)

Package

00000000h

50680h

4

DP Config (DP_​4_​9_​B0_​Config)

Package

00000000h

50684h

4

DP ChannelEn (DP_​4_​9_​B0_​ChannelEn)

Package

00000000h

50688h

4

DP SampleCtrl (DP_​4_​9_​B0_​SampleCtrl)

Package

00000000h

5068ch

4

DP OffsetCtrl (DP_​4_​9_​B0_​OffsetCtrl)

Package

00000000h

50690h

4

DP HCtrl (DP_​4_​9_​B0_​HCtrl)

Package

00000000h

50694h

4

DP AsyncCtrl (DP_​4_​9_​B0_​AsyncCtrl)

Package

00000000h

50698h

4

DP Config (DP_​4_​9_​B1_​Config)

Package

00000000h

5069ch

4

DP ChannelEn (DP_​4_​9_​B1_​ChannelEn)

Package

00000000h

506a0h

4

DP SampleCtrl (DP_​4_​9_​B1_​SampleCtrl)

Package

00000000h

506a4h

4

DP OffsetCtrl (DP_​4_​9_​B1_​OffsetCtrl)

Package

00000000h

506a8h

4

DP HCtrl (DP_​4_​9_​B1_​HCtrl)

Package

00000000h

506ach

4

DP AsyncCtrl (DP_​4_​9_​B1_​AsyncCtrl)

Package

00000000h

506b0h

4

DP Port Ctrl (DP_​4_​9_​Port_​Ctrl)

Package

00000000h

50700h

4

DP Config (DP_​4_​10_​B0_​Config)

Package

00000000h

50704h

4

DP ChannelEn (DP_​4_​10_​B0_​ChannelEn)

Package

00000000h

50708h

4

DP SampleCtrl (DP_​4_​10_​B0_​SampleCtrl)

Package

00000000h

5070ch

4

DP OffsetCtrl (DP_​4_​10_​B0_​OffsetCtrl)

Package

00000000h

50710h

4

DP HCtrl (DP_​4_​10_​B0_​HCtrl)

Package

00000000h

50714h

4

DP AsyncCtrl (DP_​4_​10_​B0_​AsyncCtrl)

Package

00000000h

50718h

4

DP Config (DP_​4_​10_​B1_​Config)

Package

00000000h

5071ch

4

DP ChannelEn (DP_​4_​10_​B1_​ChannelEn)

Package

00000000h

50720h

4

DP SampleCtrl (DP_​4_​10_​B1_​SampleCtrl)

Package

00000000h

50724h

4

DP OffsetCtrl (DP_​4_​10_​B1_​OffsetCtrl)

Package

00000000h

50728h

4

DP HCtrl (DP_​4_​10_​B1_​HCtrl)

Package

00000000h

5072ch

4

DP AsyncCtrl (DP_​4_​10_​B1_​AsyncCtrl)

Package

00000000h

50730h

4

DP Port Ctrl (DP_​4_​10_​Port_​Ctrl)

Package

00000000h

50780h

4

DP Config (DP_​4_​11_​B0_​Config)

Package

00000000h

50784h

4

DP ChannelEn (DP_​4_​11_​B0_​ChannelEn)

Package

00000000h

50788h

4

DP SampleCtrl (DP_​4_​11_​B0_​SampleCtrl)

Package

00000000h

5078ch

4

DP OffsetCtrl (DP_​4_​11_​B0_​OffsetCtrl)

Package

00000000h

50790h

4

DP HCtrl (DP_​4_​11_​B0_​HCtrl)

Package

00000000h

50794h

4

DP AsyncCtrl (DP_​4_​11_​B0_​AsyncCtrl)

Package

00000000h

50798h

4

DP Config (DP_​4_​11_​B1_​Config)

Package

00000000h

5079ch

4

DP ChannelEn (DP_​4_​11_​B1_​ChannelEn)

Package

00000000h

507a0h

4

DP SampleCtrl (DP_​4_​11_​B1_​SampleCtrl)

Package

00000000h

507a4h

4

DP OffsetCtrl (DP_​4_​11_​B1_​OffsetCtrl)

Package

00000000h

507a8h

4

DP HCtrl (DP_​4_​11_​B1_​HCtrl)

Package

00000000h

507ach

4

DP AsyncCtrl (DP_​4_​11_​B1_​AsyncCtrl)

Package

00000000h

507b0h

4

DP Port Ctrl (DP_​4_​11_​Port_​Ctrl)

Package

00000000h

50800h

4

DP Config (DP_​4_​12_​B0_​Config)

Package

00000000h

50804h

4

DP ChannelEn (DP_​4_​12_​B0_​ChannelEn)

Package

00000000h

50808h

4

DP SampleCtrl (DP_​4_​12_​B0_​SampleCtrl)

Package

00000000h

5080ch

4

DP OffsetCtrl (DP_​4_​12_​B0_​OffsetCtrl)

Package

00000000h

50810h

4

DP HCtrl (DP_​4_​12_​B0_​HCtrl)

Package

00000000h

50814h

4

DP AsyncCtrl (DP_​4_​12_​B0_​AsyncCtrl)

Package

00000000h

50818h

4

DP Config (DP_​4_​12_​B1_​Config)

Package

00000000h

5081ch

4

DP ChannelEn (DP_​4_​12_​B1_​ChannelEn)

Package

00000000h

50820h

4

DP SampleCtrl (DP_​4_​12_​B1_​SampleCtrl)

Package

00000000h

50824h

4

DP OffsetCtrl (DP_​4_​12_​B1_​OffsetCtrl)

Package

00000000h

50828h

4

DP HCtrl (DP_​4_​12_​B1_​HCtrl)

Package

00000000h

5082ch

4

DP AsyncCtrl (DP_​4_​12_​B1_​AsyncCtrl)

Package

00000000h

50830h

4

DP Port Ctrl (DP_​4_​12_​Port_​Ctrl)

Package

00000000h

50880h

4

DP Config (DP_​4_​13_​B0_​Config)

Package

00000000h

50884h

4

DP ChannelEn (DP_​4_​13_​B0_​ChannelEn)

Package

00000000h

50888h

4

DP SampleCtrl (DP_​4_​13_​B0_​SampleCtrl)

Package

00000000h

5088ch

4

DP OffsetCtrl (DP_​4_​13_​B0_​OffsetCtrl)

Package

00000000h

50890h

4

DP HCtrl (DP_​4_​13_​B0_​HCtrl)

Package

00000000h

50894h

4

DP AsyncCtrl (DP_​4_​13_​B0_​AsyncCtrl)

Package

00000000h

50898h

4

DP Config (DP_​4_​13_​B1_​Config)

Package

00000000h

5089ch

4

DP ChannelEn (DP_​4_​13_​B1_​ChannelEn)

Package

00000000h

508a0h

4

DP SampleCtrl (DP_​4_​13_​B1_​SampleCtrl)

Package

00000000h

508a4h

4

DP OffsetCtrl (DP_​4_​13_​B1_​OffsetCtrl)

Package

00000000h

508a8h

4

DP HCtrl (DP_​4_​13_​B1_​HCtrl)

Package

00000000h

508ach

4

DP AsyncCtrl (DP_​4_​13_​B1_​AsyncCtrl)

Package

00000000h

508b0h

4

DP Port Ctrl (DP_​4_​13_​Port_​Ctrl)

Package

00000000h

50900h

4

DP Config (DP_​4_​14_​B0_​Config)

Package

00000000h

50904h

4

DP ChannelEn (DP_​4_​14_​B0_​ChannelEn)

Package

00000000h

50908h

4

DP SampleCtrl (DP_​4_​14_​B0_​SampleCtrl)

Package

00000000h

5090ch

4

DP OffsetCtrl (DP_​4_​14_​B0_​OffsetCtrl)

Package

00000000h

50910h

4

DP HCtrl (DP_​4_​14_​B0_​HCtrl)

Package

00000000h

50914h

4

DP AsyncCtrl (DP_​4_​14_​B0_​AsyncCtrl)

Package

00000000h

50918h

4

DP Config (DP_​4_​14_​B1_​Config)

Package

00000000h

5091ch

4

DP ChannelEn (DP_​4_​14_​B1_​ChannelEn)

Package

00000000h

50920h

4

DP SampleCtrl (DP_​4_​14_​B1_​SampleCtrl)

Package

00000000h

50924h

4

DP OffsetCtrl (DP_​4_​14_​B1_​OffsetCtrl)

Package

00000000h

50928h

4

DP HCtrl (DP_​4_​14_​B1_​HCtrl)

Package

00000000h

5092ch

4

DP AsyncCtrl (DP_​4_​14_​B1_​AsyncCtrl)

Package

00000000h

50930h

4

DP Port Ctrl (DP_​4_​14_​Port_​Ctrl)

Package

00000000h

51200h

4

PDI Config (PDI_​4_​0_​Config)

Package

00000000h

51210h

4

PDI Config (PDI_​4_​1_​Config)

Package

00000000h

51220h

4

PDI Config (PDI_​4_​2_​Config)

Package

00000000h

51230h

4

PDI Config (PDI_​4_​3_​Config)

Package

00000000h

51240h

4

PDI Config (PDI_​4_​4_​Config)

Package

00000000h

51250h

4

PDI Config (PDI_​4_​5_​Config)

Package

00000000h

51260h

4

PDI Config (PDI_​4_​6_​Config)

Package

00000000h

51270h

4

PDI Config (PDI_​4_​7_​Config)

Package

00000000h

51280h

4

PDI Config (PDI_​4_​8_​Config)

Package

00000000h

51290h

4

PDI Config (PDI_​4_​9_​Config)

Package

00000000h

512a0h

4

PDI Config (PDI_​4_​10_​Config)

Package

00000000h

512b0h

4

PDI Config (PDI_​4_​11_​Config)

Package

00000000h

512c0h

4

PDI Config (PDI_​4_​12_​Config)

Package

00000000h

512d0h

4

PDI Config (PDI_​4_​13_​Config)

Package

00000000h

512e0h

4

PDI Config (PDI_​4_​14_​Config)

Package

00000000h

512f0h

4

PDI Config (PDI_​4_​15_​Config)

Package

00000000h

54100h

4

IP MCP Config (IP_​MCP_​4_​Config)

Package

001F0005h

54104h

4

IP MCP Control (IP_​MCP_​4_​Control)

Package

00000000h

54108h

4

IP MCP CmdCtrl (IP_​MCP_​4_​CmdCtrl)

Package

00000000h

5411ch

4

IP MCP PHYCtrl (IP_​MCP_​4_​PHYCtrl)

Package

00000000h

54130h

4

IP MCP B0_​ClockCtrl (IP_​MCP_​4_​B0_​ClockCtrl)

Package

00000000h

54140h

4

IP MCP Stat (IP_​MCP_​4_​Stat)

Package

00000000h

5414ch

4

IP MCP IntSet (IP_​MCP_​4_​IntSet)

Package

00000000h

54180h

4

IP MCP Command (IP_​MCP_​4_​Command)

Package

00000000h

56004h

4

SoundWire x Link Vendor Specific Control (SNDW4LVSCTL)

Package

00000000h

56008h

2

SoundWire x Wake Enable (SNDW4WAKEEN)

Package

0000h

5600ah

2

SoundWire x Wake Status (SNDW4WAKESTS)

Package

0000h

5600ch

2

SoundWire x I/O Control (SNDW4IOCTL)

Package

0004h

5600eh

2

SoundWire x AC Timing Control (SNDW4ACTMCTL)

Package

003Ah

56010h

2

SoundWire x Microphone Privacy Control & Status (SNDW4PVCCS)

Package

0000h
Global Capabilities (GCAP)