Function Configuration (FNCFG) – Offset 1e30 - 001 - ID:872352 | Intel® Core™ Ultra Series 3 Processors I/O Registers

Intel® Core™ Ultra Series 3 Processors I/O Registers

ID	Date	Version	Classification
872352	04/14/2026	001	Public

Function Configuration (FNCFG) – Offset 1e30

This register configures the ACE IP behavior as a device function (host root space) in the SoC.
Implementation Notes: The clock gating policy disable (CGD = 1) only needs to prevent the clock gating through the clock sustain term of the clock gating control, i.e. prevent the clock from being gated when the gated clock is still running. There is no requirement to wake up the clock when CGD being programmed to 1 whilst the clock already gated, but just nice to have.

Bit Range	Default	Access	Field Name and Description
31:7	0h	RO	Reserved (Preserved) (RSVD31) SW must preserve the original value when writing.
6	0h	RW	SRAM Retention Mode Disable (SRMD) Register is used to disable the SRAM retention mode capability of the L1 & L2 SRAMs.
5	1h	RW	Power Gating Disabled (PGD) When cleared, it allows power gating to take place per their associated enable and idle conditions. When set, it globally disables all power gating. If SSTRVAL.DPGE = 1, hardware should treat this bit to equal 0.
4	0h	RW	BIOS Configuration Lock Down (BCLD) When set, it indicates BIOS configuration is done and ready for operations. If SSTRVAL.DBCLD = 1, hardware should treat this bit to equal 1.
3	1h	RW	Clock Gating Disabled (CGD) When cleared, it allows local/dynamic clock gating and trunk clock gating to take place per the associated enable and idle conditions. When set, it globally disables all clock gating. If SSTRVAL.DCGE = 1, hardware should treat this bit to equal 0.
2	0h	RW	DSP Subsystem Disable (DSPSD) When set, the DSP subsystem is disabled and all register accesses associated with DSP subsystem are treated as unsupported requests, and returns the UR response if it is a non-posted cycle. This bit does not affect cycles from IOSF Sideband Interface. If FUSVAL.DSPSD = 1, hardware should treat this bit to equal 1.
1	1h	RW	ACE IP as PCI Device (ACEPCID) When this bit is set to 1, the ACE IP appears as a PCI device to the software. When this bit is 0, the ACE IP appears as a PCI-Express device to the software.
0	0h	RW	ACE IP Disable (ACED) When set, the ACE IP (including DSP subsystem) is disabled and all register accesses are treated as unsupported requests, and returns the UR response if it is a non-posted cycle. This bit does not affect cycles from IOSF Sideband Interface.