SSP x Status (I2S0_SSS) – Offset 28108 - 001 - ID:872352 | Intel® Core™ Ultra Series 3 Processors I/O Registers

Intel® Core™ Ultra Series 3 Processors I/O Registers

ID	Date	Version	Classification
872352	04/14/2026	001	Public

SSP x Status (I2S0_SSS) – Offset 28108

This register contains bits that signal overrun errors as well as the transmit and receive FIFO service requests. Each of these HW detected events signals an interrupt request to the interrupt controller.
The register also contains flags that indicate when the SSP Interface is actively transmitting data, when the transmit FIFO is not full, and when the receive FIFO is not empty.
One interrupt signal is sent to the interrupt controller for each SSP. These events can cause an interrupt: end of chain, receiver time-out, peripheral trailing byte, receive FIFO overrun, receive FIFO request, and transmit FIFO request.
Note: TUR bit can only be set when the SSP is a device to the SFRM signal (SSC1.SFRMDIR = 1), or if the SSP is a host to the SFRM signal (SSC1.SFRMDIR = 0) and in Network mode (SSC0.MOD = 1).

Bit Range	Default	Access	Field Name and Description
31:24	0h	RO	Reserved (Zero) (RSVD31) SW must use zeros for writes.
23	0h	RW/1C	Bit Count Error (BCE) 0: SSP has not experienced a bit count error. 1: SFRM signal has been asserted when the bit counter was not 0.
22	0h	RO/V	Clock Synchronization Status (CSS) 0: SSP is ready for device clock operations. 1: SSP is currently busy synchronizing device mode signals.
21	0h	RO/V	Transmit FIFO Underrun (TUR) 0: Transmit FIFO has not experienced an underrun. 1: Attempted read from the transmit FIFO when the FIFO was empty. Consolidated from corresponding multi DMA status bit.
20	0h	RO	Reserved (Zero) (RSVD20) SW must use zeros for writes.
19	0h	RO/V	Receiver Time-out Interrupt (TINT) 0: No receiver time-out pending. 1: Receiver time-out pending. Consolidated from corresponding multi DMA status bit.
18:8	0h	RO	Reserved (Zero) (RSVD18) SW must use zeros for writes.
7	0h	RO/V	Receive FIFO Overrun (ROR) 0: Receive FIFO has not experienced an overrun. 1: Attempted data write to full receive FIFO. Consolidated from corresponding multi DMA status bit.
6:5	0h	RO	Reserved (Zero) (RSVD6) SW must use zeros for writes.
4	0h	RO/V	SSP Busy (BSY) 0: SSP is idle or disabled. 1: SSP currently transmitting or receiving a frame.
3:0	0h	RO	Reserved (Zero) (RSVD3) SW must use zeros for writes.