REG IC_STATUS (IC_STATUS) – Offset 70 - 001 - ID:872352 | Intel® Core™ Ultra Series 3 Processors I/O Registers

Intel® Core™ Ultra Series 3 Processors I/O Registers

ID	Date	Version	Classification
872352	04/14/2026	001	Public

REG IC_STATUS (IC_STATUS) – Offset 70

Bit Range	Default	Access	Field Name and Description
31:21	0h	RO	RSVD_IC_STATUS_2 (RSVD_IC_STATUS_2) IC_STATUS Reserved bits - Read Only
20	0h	RO	RSVD_SMBUS_ALERT_STATUS (RSVD_SMBUS_ALERT_STATUS) This bit indicates the status of the SMBus Alert signal (ic_smbalert_in_n). This signal is asserted when the SMBus Alert signal is asserted by the SMBus Device.
19	0h	RO	RSVD_SMBUS_SUSPEND_STATUS (RSVD_SMBUS_SUSPEND_STATUS) This bit indicates the status of the SMBus Suspend signal (ic_smbsus_in_n). This signal is asserted when the SMBus Suspend signal is asserted by the SMBus Host.
18	0h	RO	RSVD_SMBUS_SLAVE_ADDR_RESOLVED (RSVD_SMBUS_SLAVE_ADDR_RESOLVED) This bit indicates whether the slave address (ic_sar) is resolved by the ARP Master.
17	0h	RO	RSVD_SMBUS_SLAVE_ADDR_VALID (RSVD_SMBUS_SLAVE_ADDR_VALID) This bit indicates whether the slave address (ic_sar) is valid or not.
16	0h	RO	RSVD_SMBUS_QUICK_CMD_BIT (RSVD_SMBUS_QUICK_CMD_BIT) This bit indicates the R/W bit of the Quick command received. This bit will be cleared after the user has read this bit.
15:12	0h	RO	RSVD_IC_STATUS_1 (RSVD_IC_STATUS_1) RSVD_IC_STATUS_1 Reserved bits - Read Only
11	0h	RO	RSVD_SDA_STUCK_NOT_RECOVERED (RSVD_SDA_STUCK_NOT_RECOVERED) This bit indicates that SDA stuck at low is not recovered after the recovery mechanism. In Slave mode, this register bit is not applicable.
10	0h	RO	RSVD_SLV_HOLD_RX_FIFO_FULL (RSVD_SLV_HOLD_RX_FIFO_FULL) This bit indicates the BUS Hold in Slave mode due to Rx FIFO is Full and an additional byte has been received (This kind of Bus hold is applicable if IC_RX_FULL_HLD_BUS_EN is set to 1).
9	0h	RO	RSVD_SLV_HOLD_TX_FIFO_EMPTY (RSVD_SLV_HOLD_TX_FIFO_EMPTY) This bit indicates the BUS Hold in Slave mode for the Read request when the Tx FIFO is empty. The Bus is in hold until the Tx FIFO has data to Transmit for the read request.
8	0h	RO	RSVD_MST_HOLD_RX_FIFO_FULL (RSVD_MST_HOLD_RX_FIFO_FULL) This bit indicates the BUS Hold in Master mode due to Rx FIFO is Full and additional byte has been received
7	0h	RO	RSVD_MST_HOLD_TX_FIFO_EMPTY (RSVD_MST_HOLD_TX_FIFO_EMPTY) If the IC_EMPTYFIFO_HOLD_MASTER_EN parameter is set to 1, the DW_apb_i2c master stalls the write transfer when Tx FIFO is empty, and the the last byte does not have the Stop bit set.
6	0h	RO	SLV_ACTIVITY (SLV_ACTIVITY) Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active
5	0h	RO	MST_ACTIVITY (MST_ACTIVITY) Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits.
4	0h	RO	RFF (RFF) Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared.
3	0h	RO	RFNE (RFNE) Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty.
2	1h	RO	TFE (TFE) Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt.
1	1h	RO	TFNF (TFNF) Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full.
0	0h	RO	ACTIVITY (ACTIVITY) I2C Activity Status.