I2S / PCM Link Synchronization (I2SLSYNC) – Offset d1c - 001 - ID:872352 | Intel® Core™ Ultra Series 3 Processors I/O Registers

Intel® Core™ Ultra Series 3 Processors I/O Registers

ID	Date	Version	Classification
872352	04/14/2026	001	Public

I2S / PCM Link Synchronization (I2SLSYNC) – Offset d1c

This register controls the synchronization of the multiple link segments. This register is applicable for link that support host mode only.
If LCAP.LSS = 0, this register is Reserved.

Bit Range	Default	Access	Field Name and Description
31:27	0h	RO	Reserved (Preserved) (RSVD31) SW must preserve the original value when writing.
26:24	0h	RW/1S	Command Sync (CMDSYNC) This bit is used to synchronize the command execution of multiple link segments. Software sets this bit to hold off the command from being executed on the intended link segments, until they have been setup with the same command, and lastly write to the SYNCGO bit to simultaneously clear this bit on all link segments. Note that the SYNCGO bit may be located in this register (same link type) or located in CLTSYNC register (cross link type) depending on parameter TTSCLTSE.
23	0h	WO	Sync Go (SYNCGO) This bit is used to synchronize the command execution of multiple link segments. Software sets the CMDSYNC bit to hold off the command from being executed on the intended link segments, until they have been setup with the same command, and lastly write to this bit to simultaneously clear the CMDSYNC bit on all link segments.
22:21	0h	RO	Reserved (Preserved) (RSVD22) SW must preserve the original value when writing.
20	0h	RW/1S	Sync Period Update (SYNCPU) When set to 1, an update to the sync event generation period is being requested per the value programmed in SYNCPRD field. HW will clear this bit to 0 when it has successfully updated the new period requested. HW will always make the update on 2nd sync event assertion, i.e. at the end (sampling) of the 2nd sync event of current sync event generation period, after all CMDSYNCs cleared to 0. This is to ensure all command synchronizations (if any) are completed before the update (as the 1st sync event is where the command is triggered for sending out on the bus by the controller, and the 2nd sync event is where the command is synchronously executed by the bus devices). In this case (if command synchronization is needed), SW is required to set CMDSYNC, write SYNCPRD, set SYNCPU, write SYNCGO allowing CMDSYNC to clear.
19:0	0h	RW	Sync Period (SYNCPRD) Indicates the number of host link clock the sync event should be generated periodically. 0-based value. Minimum sync period should never be programmed to less than 125 Hz. The sync event is 1 host link clock wide per sync period. Value must be programmed before setting SYNCPU bit. Default value of zero (sync period = 1 clock) means the sync event will be asserted every clock, i.e. the sync period counter is disabled. When value is programmed to a non-zero value from a current zero value and set SYNCPU bit, HW enables the sync period counter to operate. E.g. for 19.2 MHz XTAL oscillator clock, 4 KHz sync period, the value to be programmed is 12BFh. Value may be programmed dynamically when sync period counter already running, and request an update by setting the SYNCPU bit.