Clock Control (HfCLKCTL) – Offset 1d10 - 001 - ID:872352 | Intel® Core™ Ultra Series 3 Processors I/O Registers

Intel® Core™ Ultra Series 3 Processors I/O Registers

ID	Date	Version	Classification
872352	04/14/2026	001	Public

Clock Control (HfCLKCTL) – Offset 1d10

This register controls the clock operations, under host SW management.

Bit Range	Default	Access	Field Name and Description
31	0h	RW	Request HP RING Oscillator Clock (RHROSCC) FW write this bit to 1 to request for the clock. Typically for shortening the latency of clock waking by requesting it ahead of time before it is actually needed, or to disable trunk clock gating.
30	0h	RW	Request XTAL Oscillator Clock (RXOSCC) FW write this bit to 1 to request for the clock. Typically for shortening the latency of clock waking by requesting it ahead of time before it is actually needed, or to disable trunk clock gating.
29	0h	RW	Request LP RING Oscillator Clock (RLROSCC) FW write this bit to 1 to request for the clock. Typically for shortening the latency of clock waking by requesting it ahead of time before it is actually needed, or to disable trunk clock gating.
28	0h	RW	Request Serial I/O RING Oscillator Clock (RSIOROSCC) FW write this bit to 1 to request for the clock. Typically for shortening the latency of clock waking by requesting it ahead of time before it is actually needed, or to disable trunk clock gating.
27	0h	RW	Request HS I/O RING Oscillator Clock (RHSIOROSCC) FW write this bit to 1 to request for the clock. Typically for shortening the latency of clock waking by requesting it ahead of time before it is actually needed, or to disable trunk clock gating.
26	0h	RW	Request Audio PLL Clock (RAPLLC) FW write this bit to 1 to request for the clock. Typically for shortening the latency of clock waking by requesting it ahead of time before it is actually needed, or to disable trunk clock gating.
25	0h	RW	Request Audio Cardinal Clock (RACC) FW write this bit to 1 to request for the clock. Typically for shortening the latency of clock waking by requesting it ahead of time before it is actually needed, or to disable trunk clock gating.
24	0h	RW	Request IOSF Sideband Clock (RIOSFSC) FW write this bit to 1 to request for the clock. Typically for shortening the latency of clock waking by requesting it ahead of time before it is actually needed, or to disable trunk clock gating.
23	0h	RW	Request IOSF Primary Clock (RIOSFPC) FW write this bit to 1 to request for the clock. Typically for shortening the latency of clock waking by requesting it ahead of time before it is actually needed, or to disable trunk clock gating.
22	0h	RW	Request AON RING Oscillator Clock (RAONROSCC) FW write this bit to 1 to request for the clock. Typically for shortening the latency of clock waking by requesting it ahead of time before it is actually needed, or to disable trunk clock gating.
21	0h	RW	Request WoV RING Oscillator Clock (RWOVROSCC) FW write this bit to 1 to request for the clock. Typically for shortening the latency of clock waking by requesting it ahead of time before it is actually needed, or to disable trunk clock gating. Note: ACE-PLL is mutex with WoV CRO.
20	0h	RW	Request ACE PLL Clock (RACEPLLC) FW write this bit to 1 to request for the clock from ACE PLL. Typically for shortening the latency of clock waking by requesting it ahead of time before it is actually needed, or to disable trunk clock gating. Note: ACE-PLL is mutex with WoV CRO.
19:10	0h	RO	Reserved (Preserved) (RSVD19) SW must preserve the original value when writing.
9	1h	RW	HP DSP Core Dynamic Clock Gate Enable (HPDSPCDCGE) Enable dynamic clock gating functionality on the HP DSP Core clock mux output. When set, the dynamic clock gating functionality is enabled. Implementation Note: this is actually implemented as intermediate level of trunk clock gating in between the upstream clock request to SoC and downstream clock consumer dynamic clock gating, that clearing the clock gate enable will also serve as a wake condition and cause the clock request upstream to SoC to be asserted.
8	1h	RW	IOSF Sideband Dynamic Clock Gate Enable (IOSFSDCGE) Enable IOSF dynamic clock gating functionality inside IOSF interface. When set, IOSF Sideband clock gating functionality is enabled.
7	1h	RW	IOSF Backbone Dynamic Clock Gate Enable (IOSFBDCGE) Enable IOSF dynamic clock gating functionality inside IOSF interface. When set, IOSF Primary clock gating functionality is enabled.
6	1h	RW	Miscellaneous Backbone Dynamic Clock Gating Enable (MISCBDCGE) This controls dynamic clock gating of backbone (Command/data) clocks to the rest of the Intel HD Audio controller (i.e. other than the IOSF, Input DMA engine, and Output DMA engine). When this bit is asserted, dynamic clock gating logic is enabled for backbone clocks to the rest of the Intel HD Audio controller.
5	1h	RW	IDMA Backbone Dynamic Clock Gating Enable (IDMABDCGE) This controls dynamic clock gating of backbone (Command/data) clocks to each Input DMA engine. When this bit is asserted, dynamic clock gating logic is enabled for backbone clocks to each Input DMA engine.
4	1h	RW	ODMA Backbone Dynamic Clock Gating Enable (ODMABDCGE) This controls dynamic clock gating of backbone (Command/data) clocks to each Output DMA engines. When this bit is asserted, dynamic clock gating logic is enabled for backbone clocks to each Output DMA engine.
3	1h	RW	HD Audio Link Dynamic Clock Gating Enable (HDALDCGE) This controls dynamic clock gating of bitclk to Link Layer and each Input/Output DMA engine. When this bit is asserted, dynamic clock gating logic is enabled for bitclk.
2	1h	RW	HP Fabric Dynamic Clock Gate Enable (HPFBRDCGE) Enable dynamic clock gating functionality on the HP Fabric clock mux and divider output. When set, the dynamic clock gating functionality is enabled. Implementation Note: this is actually implemented as intermediate level of trunk clock gating in between the upstream clock request to SoC and downstream clock consumer dynamic clock gating, that clearing the clock gate enable will also serve as a wake condition and cause the clock request upstream to SoC to be asserted.
1	1h	RW	ULP Fabric Dynamic Clock Gate Enable (ULPFBRDCGE) Enable dynamic clock gating functionality on the ULP Fabric clock mux and divider output. When set, the dynamic clock gating functionality is enabled. Implementation Note: this is actually implemented as intermediate level of trunk clock gating in between the upstream clock request to SoC and downstream clock consumer dynamic clock gating, that clearing the clock gate enable will also serve as a wake condition and cause the clock request upstream to SoC to be asserted.
0	1h	RW	Memory Dynamic Clock Gating Enable (MEMDCGE) When set to 1, it allows HW to automatically detect for idle condition and clock gate Memory block. When clear to 0, it disables this HW auto detect idle clock gating.