Power Management Control & Status (PCS) – Offset 54 - 001 - ID:872352 | Intel® Core™ Ultra Series 3 Processors I/O Registers

Intel® Core™ Ultra Series 3 Processors I/O Registers

ID	Date	Version	Classification
872352	04/14/2026	001	Public

Power Management Control & Status (PCS) – Offset 54

This register is used to manage the PCI function power management state as well as to enable/monitor PMEs.
Implementation Notes: Because of the legacy implementation of the PMES bit is physically located in the Resume clock domain and it takes time to clock cross the clearing event resulted from SW writing a 1, it is possible that the SW may still read back 1 after clearing the PMES bit, especially if the Resume clock is tied to a slow clock in the SoC, e.g. RTC clock.

Bit Range	Default	Access	Field Name and Description
31:24	0h	RO	State Dependent Data (DT) Does not apply. Hardwired to 0's.
23	0h	RO	Bus Power/Clock Control Enable (BPCCE) Does not apply. Hardwired to 0.
22	0h	RO	B2/B3 Support (B23) Does not apply. Hardwired to 0.
21:16	0h	RO	Reserved (Zero) (RSVD21) SW must use zeros for writes.
15	0h	RW/1C	PME Status (PMES) This bit is set when the ACE IP would normally assert the PME# signal independent of the state of the PMEE bit. This bit is preserved in Sx state, and may be set during Sx state.
14:13	0h	RO	Data Scale (DSCA) This field indicates the scaling factor to be used when interpreting the value of the Data register. Not implemented.
12:9	0h	RO	Data Select (DSEL) This 4-bit field is used to select which data is to be reported through the Data register and Data_Scale field Not implemented.
8	0h	RW	PME Enable (PMEE) When set, and if corresponding PMES is also set, the Intel HD Audio subsystem will send PME to wake up the system. This bit is preserved in Sx state.
7:4	0h	RO	Reserved (Preserved) (RSVD7) SW must preserve the original value when writing.
3	1h	RO	No Soft Reset (NSR) When set ('1'), this bit indicates that devices transitioning from D3hot to D0 because of PowerState commands do not perform an internal reset. Configuration Context is preserved. Upon transition from the D3hot to the D0 Initialized state, no additional operating system intervention is required to preserve Configuration Context beyond writing the PowerState bits. When clear ('0'), devices do perform an internal reset upon transitioning from D3hot to D0 via software control of the PowerState bits. Configuration Context is lost when performing the soft reset. Upon transition from the D3hot to the D0 state, full reinitialization sequence is needed to return the device to D0 Initialized. Regardless of this bit, devices that transition from D3hot to D0 by a system or bus segment reset will return to the device state D0 Uninitialized with only PME context preserved if PME is supported and enabled.
2	0h	RO	Reserved (Preserved) (RSVD2) SW must preserve the original value when writing.
1:0	0h	RW	Power State (PS) This field is used both to determine the current power state of the ACE IP (host space) and to set a new power state. The values are: 00 - D0 state 11 - D3HOT state If software attempts to write a value of 10b or 01b in to this field, the write operation must complete normally; however, the data is discarded and no state change occurs. When in the D3HOT states, the ACE IP's configuration space is available, but the I/O and memory spaces are not. Additionally, interrupts are blocked. When software changes this value from the D3HOT state to the D0 state, no internal warm (soft) reset is generated, and software is optional to re-initialize the function.