PIO Interrupt Status Register (DWC_mipi_i3c_HCI_block.PIO_INTR_STATUS) – Offset e0 - 001 - ID:872352 | Intel® Core™ Ultra Series 3 Processors I/O Registers

Intel® Core™ Ultra Series 3 Processors I/O Registers

ID	Date	Version	Classification
872352	04/14/2026	001	Public

PIO Interrupt Status Register (DWC_mipi_i3c_HCI_block.PIO_INTR_STATUS) – Offset e0

The PIO Interrupt Status register indicates the status of outstanding interrupts.

Bit Range	Default	Access	Field Name and Description
31:10	0h	RO	Reserved
9	0h	RW/1C	(TRANSFER_ERR_STAT) Transfer Error Status The Host Controller sets this bit to 1'b1 when any tranfer error occurs on the I3C Bus. The Error Type for this error is available in the Response structure corresponding to this transfer/command. To clear, write 1'b0 to this bit.
8:6	0h	RO	Reserved
5	0h	RW/1C	(TRANSFER_ABORT_STAT) Transfer Abort Status The Host Controller sets this bit to 1'b1 when any transfer is aborted. To clear, write 1'b0 to this bit.
4	0h	RO	(RESP_READY_STAT) Response Ready Status The Host Controller sets this bit to 1'b1 when the number of Response Queue entries is >= the RESP_BUF_THLD threshold (See Register QUEUE_THLD_CTRL). The Host Controller automatically clears this field to 1'b0 when the number of Response Queue entries falls below the RESP_BUF_THLD threshold.
3	0h	RO	(CMD_QUEUE_READY_STAT) Command Queue Ready Status The Host Controller sets this bit to 1'b1 when the number of Command Queue entries is <= the CMD_EMPTY_BUF_THLD threshold (See Register QUEUE_THLD_CTRL). The Host Controller automatically clears this field to 1'b0 when the number of Command Queue entries exceeds the RESP_BUF_THLD threshold.
2	0h	RO	(IBI_STATUS_THLD_STAT) IBI Status Threshold Status The Host Controller sets this bit to 1'b1 when the number of IBI Status Entries in the IBI Queue reaches the IBI_STATUS_THLD threshold (See Register QUEUE_THLD_CTRL). The Host Controller automatically clears this field to 1'b0 when the number of IBI Status entries in the IBI Queue falls below the IBI_STATUS_THLD threshold as a result of application reads.
1	0h	RO	(RX_THLD_STAT) Rx Data Buffer Threshold Status The Host Controller sets this bit to 1'b1 when the number of entries in the Rx Data Queue is >= the RX_BUF_THLD threshold (See Register DATA_BUFFER_THLD_CTRL). The Host Controller automatically clears this field to 1'b0 when the number of Rx Data Queue entries falls below the RX_BUF_THLD threshold.
0	0h	RO	(TX_THLD_STAT) Tx Data Buffer Threshold Status The Host Controller sets this bit to 1'b1 when the number of entries in the Tx Data Queue is <= the TX_BUF_THLD threshold (see register DATA_BUFFER_THLD_CTRL). The Host Controller automatically clears this field to 1'b0 when the number of Tx Data Queue entries exceeds the TX_BUF_THLD threshold.