SoundWire x I/O Control (SNDW0IOCTL) – Offset 3600c - 001 - ID:872352 | Intel® Core™ Ultra Series 3 Processors I/O Registers

Intel® Core™ Ultra Series 3 Processors I/O Registers

ID	Date	Version	Classification
872352	04/14/2026	001	Public

SoundWire x I/O Control (SNDW0IOCTL) – Offset 3600c

This register controls the SoundWire link I/O buffers.

Bit Range	Default	Access	Field Name and Description
15:11	0h	RO	Reserved (Preserved) (RSVD15) SW must preserve the original value when writing.
10	0h	RW	Hardware Autonomous Manager IP Flowthrough Disable (HAMIFD) Software sets this bit to '1' to disable the HW autonomous sequencing of I/O buffer controls from the Manager IP to flow through, and manually sequencing through the override bits in this register (e.g. MIF).
9	0h	RW	Data Input Buffer Disable (DIBD) This register bit controls the disabling of the input buffer portion of the SoundWire Data I/O. In SoundWire functional mode, the input buffer is always enabled to receive driven bus state. However, in certain SoundWire PHY test modes, manager's data output buffer may be tri-stated and its keeper may be disabled. This bit provides flexibility to address an undesirable state at the data input buffer where the input pad is floating under certain test modes. '0' state on this register bit enables the data input buffer - Default '1' state on this register bit disables the data input buffer
8	0h	RW	Clock Input Buffer Disable (CIBD) This register bit controls the disabling of the input buffer portion of the SoundWire Clock I/O. In SoundWire functional mode, the input buffer is always enabled to receive driven bus state. However, in certain SoundWire PHY test modes, manager's clock output buffer may be tri-stated. This bit provides flexibility to address an undesirable state at the clock input buffer where the input pad is floating under certain test modes. '0' state on this register bit enables the clock input buffer - Default '1' state on this register bit disables the clock input buffer
7	0h	RO	Reserved (Preserved) (RSVD7) SW must preserve the original value when writing.
6	0h	RW	Weak Pull Down Disable (WPDD) This register bit controls the Weak Pull Down on the SoundWire Data. '0' state on this register bit enables the weak pull-down - Default '1' state on this register bit disables the weak pull-down Generally, Weak Pull Down and Bus Keeper usage are mutually exclusive. When Weak Pull Down is enabled, bus keeper is disabled, and vice versa. However, an exception exists with the initial enabling of the bus keeper at hard reset exit where the SoundWire Data strong output driver is still tri-stated. In this case to ensure that that keeper will properly latch a deterministic value when enabled, the Weak Pull Down is on by default to pull the initially indeterminate bus low while the Bus Keeper is off by default to avoid its pulling against the Weak Pull Down. After pull down settling, the bus keeper is then enabled and allowed to be overlapped with the enabled Weak Pull Down to ensure the keeper hold the low value. Then, the Weak Pull Down is disabled.
5	0h	RW	Bus Keeper Enable (BKE) When register bit MIF is '1', this bit BKE needs to be programmed to '0' non-controlling state allowing Manager IP control of the Bus Keeper. When register bit MIF is '0', this bit BKE state affects SoundWire Bus Keeper. In this case, '0' state on this register bit disables the Bus Keeper - Default '1' state on this register bit enables the Bus Keeper See description for bit WPDD regarding the relationship of Bus Keeper and Weak Pull Down.
4	0h	RW	Data Out Enable (DOE) When register bit MIF is '1', this bit DOE needs to be programmed to '0' non-controlling state allowing Manager IP control of the data output enable. When register bit MIF is '0', this bit DOE state affects SoundWire Data Output driver. In this case, '0' state on this register bit tri-states Data - Default '1' state on this register bit enables Data output driver
3	0h	RW	Data Out (DO) When register bit MIF is '1', this bit DO needs to be programmed to '0' non-controlling state allowing Manager IP control of the data. When register bit MIF is '0', this bit DO state is driven onto SoundWire Data as a corresponding electrical level provided that bit DOE is also at proper state to allow the buffer to drive. In this case, '0' state on this register bit is driven as electrical low on Data '1' state on this register bit is driven as electrical high on Data
2	1h	RW	Clock Out Enable (COE) When register bit MIF is '1', this bit COE needs to be programmed to '0' non-controlling state allowing Manager IP control of the clock output enable. When register bit MIF is '0', this bit COE state affects SoundWire Clock Output driver. In this case, '0' state on this register bit tri-states Clock '1' state on this register bit enables Clock output driver - Default
1	0h	RO	Clock Out (CO) When register bit MIF is '1', this bit CO needs to be at '0' non-controlling state allowing Manager IP control of the clock. When register bit MIF is '0', this bit CO state is driven onto SoundWire Clock as a corresponding electrical level assuming that the clock driver is enabled. In this case, '0' state on this register bit is driven as electrical low on Clock Default '1' state on this register bit is driven as electrical high on Clock
0	0h	RW	Manager IP Flowthrough (MIF) Software sets this bit to '1' to allow the I/O buffer controls from the Manager IP to flow through, and clears to '0' to make the Manager IP non-controlling. Effect of this bit being '0' (Default) includes: SoundWire Clock state is determined by register bit CO and COE SoundWire Data state is determined by register bits DO and DOE SoundWire Keeper state is determined by register bit BKE To completely release control of the I/O buffer to the Manager IP, this bit needs to be '1' to allow Manager IP flow through and also bits CO, COE, DO, DOE, BKE need to be at non-controlling '0' state. Also see description for bit WPDD regarding the relationship of Bus Keeper and Weak Pull Down. Software is to switch control with Manager IP, i.e. flip this MIF bit, at the bus state of {SoundWire Clock Low, SoundWire Data Tri-stated, Bus Keeper Enabled.} Prior to this switch point, bits CO, COE, DO, DOE, and BKE would need to be programmed to same bus state {CO=0, COE = 1, DO=0, DOE=0, BKE=1} first. This is to ensure glitch-free behavior on the bus for key usage scenario of Manager IP reset exit while SoundWire bus is under ClockStop state.