Intel® Core™ Processor (Series 3)

Formerly known as Wildcat Lake, Datasheet, Volume 1 of 2

ID Date Version Classification
913965 05/19/2026 001 Public
Document Table of Contents
Document Table of Contents
Legal Disclaimer Revision History Introduction Processor and Device IDs Package Mechanical Specifications Memory Mapping Security Technologies Intel Virtualization Technology Instructions Set Enhancements Intel® Neural Processing Unit (Intel® NPU) Audio Voice and Speech Power Management Power Delivery Thermal Management System Clocks Real Time Clock (RTC) Memory USB Type-C Sub System Universal Serial Bus (USB) PCI Express (PCIe) Universal Flash Storage Graphics Display Processor Sideband Signals General Purpose Input and Output Interrupt Timer Subsystem (ITSS) Intel® Serial IO Inter-Integrated Circuit (I2C) Controllers Intel® Serial IO Improved Inter-Integrated Circuit (I3C) Controllers Gigabit Ethernet Controller Connectivity Integrated (CNVi) Controller Link Integrated Sensor Hub (ISH) System Management Interface and SMLink Host System Management Bus (SMBus) Controller Serial Peripheral Interface (SPI) Enhanced Serial Peripheral Interface (eSPI) Intel® Serial IO Generic SPI (GSPI) Controllers Touch Host Controller (THC) Intel® Serial IO Universal Asynchronous ReceiverTransmitter (UART) Controlle Private Configuration Space Port ID Testability and Monitoring
Legal Disclaimer
Revision History
Introduction
Introduction Processor Volatility Statement Package Dimensions Supported Technologies Power Management Support Thermal Management Support Ballout Information Operating Systems Support Terminology and Special Marks Flexible High Speed IO
Processor Volatility Statement
Package Dimensions
Intel® Core™ Processor (Series 3) Package Details
Intel® Core™ Processor (Series 3) Package Details
Supported Technologies
Supported Technologies API Support (Windows)
API Support (Windows)
Power Management Support
Power Management Support Processor Core Power Management Memory Controller Power Management Processor Graphics Power Management
Processor Core Power Management
Memory Controller Power Management
Processor Graphics Power Management
Thermal Management Support
Ballout Information
Operating Systems Support
Terminology and Special Marks
Flexible High Speed IO
Flexible High Speed IO Intel® Core™ Series 3 Flexible HSIO Lanes
Intel® Core™ Series 3 Flexible HSIO Lanes
Processor and Device IDs
Processor and Device IDs CPUID PCI Configuration Header Device IDs Revision IDs
CPUID
PCI Configuration Header
Device IDs
Revision IDs
Package Mechanical Specifications
Package Mechanical Specifications Package Mechanical Attributes Package Loading and Tile Pressure Specifications Package Storage Specifications
Package Mechanical Attributes
Package Loading and Tile Pressure Specifications
Package Loading and Tile Pressure Specifications Static Compressive Load Specification Maximum Pressure Specifications
Maximum Pressure Specifications
Package Storage Specifications
Memory Mapping
Memory Mapping Functional Description Memory Map
Functional Description
PCI Devices and Functions Fixed IO Address Ranges Variable IO Decode Ranges
PCI Devices and Functions
Fixed IO Address Ranges
Variable IO Decode Ranges
Memory Map
Memory Map Boot Block Update Scheme
Boot Block Update Scheme
Security Technologies
Security Technologies Intel® Converged Boot Guard and TXT Crypto Acceleration Instructions Intel® Secure Key Execute Disable Bit Intel® Supervisor Mode Execution Protection (Intel® SMEP) Intel® Supervisor Mode Access Protection (Intel® SMAP) User Mode Instruction Prevention (UMIP) Read Processor ID (RDPID) Intel® System Resources Defense and Intel® System Security Report Intel® Total Memory Encryption - Multi-Key Control-flow Enforcement Technology (Intel® CET) BIOS Guard Intel® Platform Trust Technology Linear Address Space Separation (LASS) Intel® Total Storage Encryption (Intel® TSE) Security Firmware Engines
Intel® Converged Boot Guard and TXT
Crypto Acceleration Instructions
Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) Perform Carry-Less Multiplication Quad Word Instruction (PCLMULQDQ) Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions) New Cryptographic Acceleration Instructions
Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)
Perform Carry-Less Multiplication Quad Word Instruction (PCLMULQDQ)
Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions)
New Cryptographic Acceleration Instructions
Intel® Secure Key
Execute Disable Bit
Intel® Supervisor Mode Execution Protection (Intel® SMEP)
Intel® Supervisor Mode Access Protection (Intel® SMAP)
User Mode Instruction Prevention (UMIP)
Read Processor ID (RDPID)
Intel® System Resources Defense and Intel® System Security Report
Intel® Total Memory Encryption - Multi-Key
Control-flow Enforcement Technology (Intel® CET)
Control-flow Enforcement Technology (Intel® CET) Shadow Stack Indirect Branch Tracking
Shadow Stack
Indirect Branch Tracking
BIOS Guard
Intel® Platform Trust Technology
Linear Address Space Separation (LASS)
Intel® Total Storage Encryption (Intel® TSE)
Security Firmware Engines
Intel®Converged Security and Management Engine (Intel®CSME) Intel® Silicon Security Engine Intel® Graphics System Controller (Intel® GSC) Intel® Partner Security Engine
Intel®Converged Security and Management Engine (Intel®CSME)
Intel® Silicon Security Engine
Intel® Graphics System Controller (Intel® GSC)
Intel® Partner Security Engine
Intel Virtualization Technology
Intel Virtualization Technology Intel® Virtualization Technology (Intel® VT) for Intel® 64 and Intel® Archit Intel® Virtualization Technology (Intel® VT) for Directed IO (Intel® VT-d) Intel® APIC Virtualization Technology (Intel® APICv)
Intel® Virtualization Technology (Intel® VT) for Intel® 64 and Intel® Archit
Intel® Virtualization Technology (Intel® VT) for Directed IO (Intel® VT-d)
Intel® APIC Virtualization Technology (Intel® APICv)
Instructions Set Enhancements
Instructions Set Enhancements CMPccXADD Linear Address Masking (LAM) SW Resource Prioritization
CMPccXADD
Linear Address Masking (LAM)
SW Resource Prioritization
Intel® Neural Processing Unit (Intel® NPU)
Intel® Neural Processing Unit (Intel® NPU) Functional Description
Functional Description
Functional Description HOST Control Deep Learning Accelerators (NCE)
HOST Control
Deep Learning Accelerators (NCE)
Deep Learning Accelerators (NCE) Feature Set NCE Tile ACTIVATION-SHAVE (ACT-SHAVE) Data Processing Unit (DPU)
Feature Set
NCE Tile
ACTIVATION-SHAVE (ACT-SHAVE)
Data Processing Unit (DPU)
Audio Voice and Speech
Audio Voice and Speech Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities Audio DSP Capabilities Intel® High Definition Audio Interface Capabilities Direct Attached Digital Microphone (PDM) Interface USB Audio Offload Support I2S PCM Interface Intel® Display Audio Interface MIPI® SoundWire Interface Signal Description Integrated Pull-Ups and Pull-Downs IO Signal Planes and States
Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities
Audio DSP Capabilities
Intel® High Definition Audio Interface Capabilities
Direct Attached Digital Microphone (PDM) Interface
USB Audio Offload Support
I2S PCM Interface
Intel® Display Audio Interface
MIPI® SoundWire Interface
Signal Description
Integrated Pull-Ups and Pull-Downs
IO Signal Planes and States
Power Management
Power Management System Power States, Advanced Configuration and Power Interface (ACPI) Functional Description Processor Graphics Power Management TCSS Power States Power and Performance Technologies Power and Internal Signals
System Power States, Advanced Configuration and Power Interface (ACPI)
Functional Description
Features Power Saving Features SMI SCI Generation Sleep States Event Input Signals and Their Usage System Power Supplies, Planes, and Signals Reset Behavior
Features
Power Saving Features
SMI SCI Generation
Sleep States
Event Input Signals and Their Usage
System Power Supplies, Planes, and Signals
Reset Behavior
Processor Graphics Power Management
Processor Graphics Power Management Memory Power Savings Technologies Display Power Savings Technologies Processor Graphics Core Power Savings Technologies
Memory Power Savings Technologies
Display Power Savings Technologies
Processor Graphics Core Power Savings Technologies
TCSS Power States
Power and Performance Technologies
Power and Performance Technologies Intel® Thread Director Intel® Smart Cache Technology P-core LP E-core Level 0, Level 1 and Level 2 Caches Ring Interconnect Intel® Hybrid Technology Intel® Turbo Boost Technology 2.0 Intel® Adaptive Boost Technology Intel System Agent Enhanced SpeedStep ® Technology Enhanced Intel SpeedStep® Technology Intel® Speed Shift Technology Intel® Advanced Vector Extensions 2 (Intel® AVX2) Intel® 64 Architecture x2APIC Intel® Dynamic Tuning Technology (Intel® DTT) Cache Line Write Back (CLWB) User Mode Wait Instructions
Intel® Thread Director
Intel® Smart Cache Technology
P-core LP E-core Level 0, Level 1 and Level 2 Caches
Ring Interconnect
Intel® Hybrid Technology
Intel® Turbo Boost Technology 2.0
Intel® Turbo Boost Technology 2.0 Intel® Turbo Boost Technology 2.0 Power Monitoring Intel® Turbo Boost Technology 2.0 Power Control Intel® Turbo Boost Technology 2.0 Frequency
Intel® Turbo Boost Technology 2.0 Power Monitoring
Intel® Turbo Boost Technology 2.0 Power Control
Intel® Turbo Boost Technology 2.0 Frequency
Intel® Adaptive Boost Technology
Intel System Agent Enhanced SpeedStep ® Technology
Enhanced Intel SpeedStep® Technology
Intel® Speed Shift Technology
Intel® Advanced Vector Extensions 2 (Intel® AVX2)
Intel® Advanced Vector Extensions 2 (Intel® AVX2) AI Acceleration Extensions in Intel® AVX2
AI Acceleration Extensions in Intel® AVX2
Intel® 64 Architecture x2APIC
Intel® Dynamic Tuning Technology (Intel® DTT)
Cache Line Write Back (CLWB)
User Mode Wait Instructions
Power and Internal Signals
Signal Description Power Sequencing Signals Integrated Pull-Ups and Pull-Downs IO Signal Planes and States
Signal Description
Power Sequencing Signals
Integrated Pull-Ups and Pull-Downs
IO Signal Planes and States
Power Delivery
Power and Ground Signals Digital Linear Voltage Regulator (DLVR) Current Excursion Protection (CEP) Fast V-Mode (FVM) Vsys_crit based Reactive PL4 with PL4 Boost Thermally Equal Turbo-boost Algorithm (ThETA)
Power and Ground Signals
Digital Linear Voltage Regulator (DLVR)
Current Excursion Protection (CEP)
Fast V-Mode (FVM)
Vsys_crit based Reactive PL4 with PL4 Boost
Thermally Equal Turbo-boost Algorithm (ThETA)
Thermal Management
Thermal Management Processor Thermal Management Processor Base Power Thermal and Power Specifications Thermal and Power Specifications Error and Thermal Protection Signals Thermal Sensor
Processor Thermal Management
Processor Thermal Management Thermal Considerations Thermal Management Features Assured Power Intel Memory Thermal Management
Thermal Considerations
Thermal Considerations Package Power Control Platform Power Control Turbo Time Parameter (Tau)
Package Power Control
Platform Power Control
Turbo Time Parameter (Tau)
Thermal Management Features
Thermal Management Features Skin Temperature Control (STC) Adaptive Thermal Monitor Digital Thermal Sensor FORCEPR# Signal FORCEPR Demotion Voltage Regulator Protection using FORCEPR# Thermal Solution Design and FORCEPR Behavior Low-Power States and FORCEPR Behavior THERMTRIP Signal Critical Temperature Detection
Skin Temperature Control (STC)
Adaptive Thermal Monitor
Digital Thermal Sensor
FORCEPR# Signal
FORCEPR Demotion
Voltage Regulator Protection using FORCEPR#
Thermal Solution Design and FORCEPR Behavior
Low-Power States and FORCEPR Behavior
THERMTRIP Signal
Critical Temperature Detection
Assured Power
Assured Power Assured Power Modes Low Power Mode
Assured Power Modes
Low Power Mode
Intel Memory Thermal Management
Processor Base Power Thermal and Power Specifications
Thermal and Power Specifications
Error and Thermal Protection Signals
Thermal Sensor
Thermal Sensor Modes of Operation Temperature Trip Point Thermal Reporting to EC Thermal Trip Signal
Modes of Operation
Temperature Trip Point
Thermal Reporting to EC
Thermal Trip Signal
System Clocks
System Clocks ICC IO Signal Pin States
ICC
ICC Signal Description
Signal Description
IO Signal Pin States
Real Time Clock (RTC)
Real Time Clock (RTC) Signal Description IO Signal Planes and States
Signal Description
IO Signal Planes and States
Memory
Memory System Memory Interface Integrated Memory Controller (IMC) Power Management Signal Description
System Memory Interface
System Memory Interface Processor SKU Support Matrix Supported Memory Modules and Devices System Memory Timing Support Memory Controller (MC) System Memory Frequency Technology Enhancements of Intel® Fast Memory Access (Intel® FMA) Data Scrambling Data Swapping LPDDR5x CMDADD Ascending and Descending DDR IO Interleaving DRAM Clock Generation DRAM Reference Voltage Generation Data Swizzling Error Correction With Standard RAM Post Package Repair (PPR) RFM In-Memory Analytics Accelerator
Processor SKU Support Matrix
Supported Memory Modules and Devices
System Memory Timing Support
System Memory Timing Support SAGV Points
SAGV Points
Memory Controller (MC)
System Memory Frequency
Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)
Data Scrambling
Data Swapping
LPDDR5x CMDADD Ascending and Descending
DDR IO Interleaving
DRAM Clock Generation
DRAM Reference Voltage Generation
Data Swizzling
Error Correction With Standard RAM
Post Package Repair (PPR)
RFM
In-Memory Analytics Accelerator
Integrated Memory Controller (IMC) Power Management
Integrated Memory Controller (IMC) Power Management DRAM Power Management and Initialization DDR Electrical Power Gating Power Training DVFS
DRAM Power Management and Initialization
DRAM Power Management and Initialization Conditional Self-Refresh Dynamic Power-Down DRAM IO Power Management
Conditional Self-Refresh
Dynamic Power-Down
DRAM IO Power Management
DDR Electrical Power Gating
Power Training
DVFS
Signal Description
USB Type-C Sub System
USB Type-C Sub System General Capabilities USB4 Router xHCI Controllers Display Interface USB Type-C Signals AUS BIAS/Orientation/Isolation Control
General Capabilities
USB4 Router
USB4 Router USB4 Host Router Implementation Capabilities
USB4 Host Router Implementation Capabilities
xHCI Controllers
xHCI Controllers USB 3 Controllers PCIe Interface
USB 3 Controllers
USB 3 Controllers Extensible Host Controller Interface (xHCI)
Extensible Host Controller Interface (xHCI)
PCIe Interface
Display Interface
USB Type-C Signals
AUS BIAS/Orientation/Isolation Control
Universal Serial Bus (USB)
Universal Serial Bus (USB) Functional Description Signal Description Integrated Pull-Ups and Pull-Downs IO Signal Planes and States
Functional Description
eXtensible Host Controller Interface (xHCI) Controller USB Dual Role Support - eXtensible Device Controller Interface (xDCI) Contro
eXtensible Host Controller Interface (xHCI) Controller
USB Dual Role Support - eXtensible Device Controller Interface (xDCI) Contro
Signal Description
Integrated Pull-Ups and Pull-Downs
IO Signal Planes and States
PCI Express (PCIe)
PCI Express (PCIe) Functional Description Signal Description IO Signal Planes and States PCI Express* Root Port Support Feature Details
Functional Description
Signal Description
IO Signal Planes and States
PCI Express* Root Port Support Feature Details
Universal Flash Storage
Universal Flash Storage UFS Functional Description UFS Signals IO Signals Planes and States
UFS Functional Description
UFS Signals
IO Signals Planes and States
Graphics
Graphics Processor Graphics Platform Graphics Hardware Feature
Processor Graphics
Processor Graphics Media Support (Intel® QuickSync and Clear Video Technology HD) Graphics Core Cache
Media Support (Intel® QuickSync and Clear Video Technology HD)
Media Support (Intel® QuickSync and Clear Video Technology HD) Hardware Accelerated Video Decode Hardware Accelerated Video Encode Hardware Accelerated Video Processing Hardware Accelerated Transcoding
Hardware Accelerated Video Decode
Hardware Accelerated Video Encode
Hardware Accelerated Video Processing
Hardware Accelerated Transcoding
Graphics Core Cache
Platform Graphics Hardware Feature
Platform Graphics Hardware Feature Hybrid Graphics
Hybrid Graphics
Display
Display Display Technologies Support Display Interfaces Display Features
Display Technologies Support
Display Interfaces
Display Interfaces Digital Display Interface DDI Signals Digital Display Interface TCP Signals
Digital Display Interface DDI Signals
Digital Display Interface TCP Signals
Display Features
Display Features General Capabilities Multiple Display Configurations High-bandwidth Digital Content Protection (HDCP) DisplayPort High-Definition Multimedia Interface (HDMI) embedded DisplayPort (eDP) Integrated Audio
General Capabilities
Multiple Display Configurations
High-bandwidth Digital Content Protection (HDCP)
DisplayPort
DisplayPort Multi-Stream Transport (MST)
Multi-Stream Transport (MST)
High-Definition Multimedia Interface (HDMI)
embedded DisplayPort (eDP)
Integrated Audio
Processor Sideband Signals
Processor Sideband Signals Signal Description Integrated Pull-Ups and Pull-Downs IO Signal Planes and States
Signal Description
Integrated Pull-Ups and Pull-Downs
IO Signal Planes and States
General Purpose Input and Output
General Purpose Input and Output Functional Description Signal Description
Functional Description
Functional Description Timed GPIO
Timed GPIO
Signal Description
Interrupt Timer Subsystem (ITSS)
Interrupt Timer Subsystem (ITSS) Feature Overview Functional Description
Feature Overview
Functional Description
Functional Description 8254 Timers APIC Advanced Interrupt Controller High Precision Event Timer (HPET)
8254 Timers
8254 Timers Timer Programming Reading from Interval Timer
Timer Programming
Reading from Interval Timer
APIC Advanced Interrupt Controller
High Precision Event Timer (HPET)
High Precision Event Timer (HPET) Timer Accuracy Timer Off-load Periodic Versus Non-Periodic Modes Enabling the Timers Interrupt Levels
Timer Accuracy
Timer Off-load
Periodic Versus Non-Periodic Modes
Enabling the Timers
Interrupt Levels
Intel® Serial IO Inter-Integrated Circuit (I2C) Controllers
Intel® Serial IO Inter-Integrated Circuit (I2C) Controllers Functional Description Signal Description Integrated Pull-Ups and Pull-Downs IO Signal Planes and States
Functional Description
Functional Description Protocols Overview DMA Controller Reset Power Management Interrupts Error Handling Programmable SDA Hold Time
Protocols Overview
DMA Controller
Reset
Power Management
Interrupts
Error Handling
Programmable SDA Hold Time
Signal Description
Integrated Pull-Ups and Pull-Downs
IO Signal Planes and States
Intel® Serial IO Improved Inter-Integrated Circuit (I3C) Controllers
Intel® Serial IO Improved Inter-Integrated Circuit (I3C) Controllers Functional Description Signal Description Integrated Pull-Ups and Pull-Downs IO Signal Planes and States
Functional Description
Reset Power Management Interrupts
Reset
Power Management
Interrupts
Signal Description
Integrated Pull-Ups and Pull-Downs
IO Signal Planes and States
Gigabit Ethernet Controller
Gigabit Ethernet Controller Functional Description Signal Description Integrated Pull-Ups and Pull-Downs IO Signal Planes and States
Functional Description
Functional Description GbE PCI Bus Interface Error Events and Error Reporting Ethernet Interface PCI Power Management
GbE PCI Bus Interface
Error Events and Error Reporting
Ethernet Interface
PCI Power Management
Signal Description
Integrated Pull-Ups and Pull-Downs
IO Signal Planes and States
Connectivity Integrated (CNVi)
Connectivity Integrated (CNVi) Functional Description Signal Description Integrated Pull-ups and Pull-downs IO Signal Planes and States
Functional Description
Signal Description
Integrated Pull-ups and Pull-downs
IO Signal Planes and States
Controller Link
Controller Link Signal Description Integrated Pull-Ups and Pull-Downs IO Signal Planes and States External CL_RST Pin Driven Open drained Mode Support
Signal Description
Integrated Pull-Ups and Pull-Downs
IO Signal Planes and States
External CL_RST Pin Driven Open drained Mode Support
Integrated Sensor Hub (ISH)
Integrated Sensor Hub (ISH) Features Functional Description Signal Description Integrated Pull-Ups and Pull-Down IO Signal Planes and States
Features
ISH I2C Controllers ISH I3C Controllers ISH UART Controller ISH GSPI Controller ISH GPIOs
ISH I2C Controllers
ISH I3C Controllers
ISH UART Controller
ISH GSPI Controller
ISH GPIOs
Functional Description
Functional Description ISH Micro-Controller SRAM PCI Host Interface ISH IPC ISH Interrupt Handling via IOAPIC (Interrupt Controller)
ISH Micro-Controller
SRAM
PCI Host Interface
ISH IPC
ISH Interrupt Handling via IOAPIC (Interrupt Controller)
Signal Description
Integrated Pull-Ups and Pull-Down
IO Signal Planes and States
System Management Interface and SMLink
System Management Interface and SMLink Functional Description Signal Description
Functional Description
Functional Description Integrated USB-C Usage
Integrated USB-C Usage
Signal Description
Host System Management Bus (SMBus) Controller
Host System Management Bus (SMBus) Controller Functional Description SMBus Power Gating Signal Description Integrated Pull-Ups and Pull-Downs IO Signal Planes and States
Functional Description
Functional Description Host Controller SMBus Target Interface
Host Controller
SMBus Target Interface
SMBus Power Gating
Signal Description
Integrated Pull-Ups and Pull-Downs
IO Signal Planes and States
Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI) Functional Description Signal Description Integrated Pull-Ups and Pull-Downs IO Signal Planes and States
Functional Description
SPI0 Support for TPM SPI0 for Flash
SPI0 Support for TPM
SPI0 for Flash
Signal Description
Integrated Pull-Ups and Pull-Downs
IO Signal Planes and States
Enhanced Serial Peripheral Interface (eSPI)
Enhanced Serial Peripheral Interface (eSPI) Functional Description Signal Description
Functional Description
Functional Description Channels and Supported Transactions
Channels and Supported Transactions
Signal Description
Intel® Serial IO Generic SPI (GSPI) Controllers
Intel® Serial IO Generic SPI (GSPI) Controllers Functional Description Signal Description Integrated Pull-Ups and Pull-Downs IO Signal Planes and States
Functional Description
Functional Description Controller Overview DMA Controller Reset Power Management Interrupts Error Handling
Controller Overview
DMA Controller
Reset
Power Management
Interrupts
Error Handling
Signal Description
Integrated Pull-Ups and Pull-Downs
IO Signal Planes and States
Touch Host Controller (THC)
Touch Host Controller (THC) Functional Description Signal Description Integrated Pull-Ups and Pull-Downs IO Signal Planes and States
Functional Description
Signal Description
Integrated Pull-Ups and Pull-Downs
IO Signal Planes and States
Intel® Serial IO Universal Asynchronous ReceiverTransmitter (UART) Controlle
Intel® Serial IO Universal Asynchronous ReceiverTransmitter (UART) Controlle Functional Description Signal Description Integrated Pull-Ups and Pull-Downs IO Signal Planes and States LSx
Functional Description
UART Serial (RS-232) Protocols Overview 16550 8-bit Addressing - Debug Driver Compatibility DMA Controller Reset Power Management Interrupts Error Handling
UART Serial (RS-232) Protocols Overview
16550 8-bit Addressing - Debug Driver Compatibility
DMA Controller
Reset
Power Management
Interrupts
Error Handling
Signal Description
Integrated Pull-Ups and Pull-Downs
IO Signal Planes and States
LSx
LSx LSx Signal Description Integrated Pull-Ups and Pull-Downs IO Signal Planes and States
LSx Signal Description
Integrated Pull-Ups and Pull-Downs
IO Signal Planes and States
Private Configuration Space Port ID
Testability and Monitoring
Testability and Monitoring Signal Description
Signal Description

DRAM IO Power Management

Unused signals should be disabled to save power and reduce electromagnetic interference. Clocks and CS signals are controlled per DIMM rank and will be powered down for unused ranks.

The I/O buffer for an unused signal should be tri-stated (output driver disabled), the input receiver (differential sense-amp) should be disabled. The input path should be gated to prevent spurious results due to noise on the unused signals (typically handled automatically when input receiver is disabled).

DDR Electrical Power Gating