Intel® Core™ Processor (Series 3)
Formerly known as Wildcat Lake, Datasheet, Volume 1 of 2
| ID | Date | Version | Classification |
|---|---|---|---|
| 913965 | 05/19/2026 | 001 | Public |
Revision IDs
The Revision ID (RID) register is an 8-bit register located at offset 08h in the PCI header of every PCI/PCIe* function. The RID register is used by software to identify a particular component stepping when a driver change or patch unique to that stepping is needed.
The RID register reports one of the two possible values:
The default power-on value for the RID register is SRID. The assigned value is based on the product’s stepping. CRID is intended for the corporate Intel® Stable Image Platform Program (Intel® SIPP). CRID is normally identical to the SRID value of a previous production stepping of the product with which the new stepping is deemed compatible. Intel® SIPP allows an OS image built on the earlier stepping to be used on any new compatible stepping(s). Three CRID values are possible and can be used to manage software images.
Following reset, the SRID value can be read from the RID registers of all Processor devices and functions.
To select either SRID or CRID to be reflected in the RID registers:
BIOS needs to write appropriate value into the Configured Revision ID (CRID) register located in the PMC MMIO space.- BIOS must write this register with the appropriate value after S4/S5 states and after PLTRST# events.
After CRID is selected and applied by BIOS, software will not be able to obtain the original SRID value of the Processor by reading the RID registers. Customers implementing CRID who also want to determine the SRID in runtime may develop their own tool. For example, BIOS can capture the SRID value before BIOS applies CRID and store that value in a runtime accessible place (that is, SMBIOS, ACPI Type 4 Memory, NVRAM, CMOS) so that it can be read by the customer tool later. Alternatively, theBIOS can store the SRID value and display this information in BIOSsetup while reporting that CRID is enabled.
BIOS needs to check CRID_UIP bit (in PMC MMIO space) as a part of the update flow. PMC HW sets this bit to indicate that SetID broadcast flow has been requested by BIOS. This bit is cleared by PMC FW only when the completion/s of SetIDVal message is received by PMC. BIOS is required to read this bit as cleared before writing to the CRID register (to request a CRID update). BIOS is also required to poll on reads to this bit until it detects the bit as cleared after BIOS has written to the CRID register.