Intel® Core™ Processor (Series 3)
Formerly known as Wildcat Lake, Datasheet, Volume 1 of 2
| ID | Date | Version | Classification |
|---|---|---|---|
| 913965 | 05/19/2026 | 001 | Public |
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Revision History
Introduction
Processor and Device IDs
Package Mechanical Specifications
Memory Mapping
Security Technologies
Intel Virtualization Technology
Instructions Set Enhancements
Intel® Neural Processing Unit (Intel® NPU)
Audio Voice and Speech
Power Management
Power Delivery
Thermal Management
System Clocks
Real Time Clock (RTC)
Memory
USB Type-C Sub System
Universal Serial Bus (USB)
PCI Express (PCIe)
Universal Flash Storage
Graphics
Display
Processor Sideband Signals
General Purpose Input and Output
Interrupt Timer Subsystem (ITSS)
Intel® Serial IO Inter-Integrated Circuit (I2C) Controllers
Intel® Serial IO Improved Inter-Integrated Circuit (I3C) Controllers
Gigabit Ethernet Controller
Connectivity Integrated (CNVi)
Controller Link
Integrated Sensor Hub (ISH)
System Management Interface and SMLink
Host System Management Bus (SMBus) Controller
Serial Peripheral Interface (SPI)
Enhanced Serial Peripheral Interface (eSPI)
Intel® Serial IO Generic SPI (GSPI) Controllers
Touch Host Controller (THC)
Intel® Serial IO Universal Asynchronous ReceiverTransmitter (UART) Controlle
Private Configuration Space Port ID
Testability and Monitoring
Security Technologies
Intel® Converged Boot Guard and TXT
Crypto Acceleration Instructions
Intel® Secure Key
Execute Disable Bit
Intel® Supervisor Mode Execution Protection (Intel® SMEP)
Intel® Supervisor Mode Access Protection (Intel® SMAP)
User Mode Instruction Prevention (UMIP)
Read Processor ID (RDPID)
Intel® System Resources Defense and Intel® System Security Report
Intel® Total Memory Encryption - Multi-Key
Control-flow Enforcement Technology (Intel® CET)
BIOS Guard
Intel® Platform Trust Technology
Linear Address Space Separation (LASS)
Intel® Total Storage Encryption (Intel® TSE)
Security Firmware Engines
Audio Voice and Speech
Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities
Audio DSP Capabilities
Intel® High Definition Audio Interface Capabilities
Direct Attached Digital Microphone (PDM) Interface
USB Audio Offload Support
I2S PCM Interface
Intel® Display Audio Interface
MIPI® SoundWire Interface
Signal Description
Integrated Pull-Ups and Pull-Downs
IO Signal Planes and States
Power and Performance Technologies
Intel® Thread Director
Intel® Smart Cache Technology
P-core LP E-core Level 0, Level 1 and Level 2 Caches
Ring Interconnect
Intel® Hybrid Technology
Intel® Turbo Boost Technology 2.0
Intel® Adaptive Boost Technology
Intel System Agent Enhanced SpeedStep ® Technology
Enhanced Intel SpeedStep® Technology
Intel® Speed Shift Technology
Intel® Advanced Vector Extensions 2 (Intel® AVX2)
Intel® 64 Architecture x2APIC
Intel® Dynamic Tuning Technology (Intel® DTT)
Cache Line Write Back (CLWB)
User Mode Wait Instructions
Thermal Management Features
Skin Temperature Control (STC)
Adaptive Thermal Monitor
Digital Thermal Sensor
FORCEPR# Signal
FORCEPR Demotion
Voltage Regulator Protection using FORCEPR#
Thermal Solution Design and FORCEPR Behavior
Low-Power States and FORCEPR Behavior
THERMTRIP Signal
Critical Temperature Detection
System Memory Interface
Processor SKU Support Matrix
Supported Memory Modules and Devices
System Memory Timing Support
Memory Controller (MC)
System Memory Frequency
Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)
Data Scrambling
Data Swapping
LPDDR5x CMDADD Ascending and Descending
DDR IO Interleaving
DRAM Clock Generation
DRAM Reference Voltage Generation
Data Swizzling
Error Correction With Standard RAM
Post Package Repair (PPR)
RFM
In-Memory Analytics Accelerator
Functional Description
The NPU IP comprises several individual components grouped into two major subsystems:
Details of these blocks are provided in the next sections.
Host Control
The functionality of the NPU is exposed to a SoC via a base set of registers (enumerated as a PCIe device or directly memory mapped into the address space of the Host).
These registers provide access to control and data path interfaces and reside in the Host Subsystem. All host communications are consumed by the NPU scheduler, a 64-bit RISC-V micro-controller. As well as responding to control messages it manages all the job submission/completion FIFOs that make up the data path of the NPU.Deep Learning (Neural Compute Engine)
The NPU IP Deep Learning capability is provided by a configurable number of Neural Compute Engine (NCE) Tiles. The NCE Tiles are managed by the NPU Scheduler.
Each Tile includes a configurable amount of near-compute SRAM, one Data Processing Unit (DPU) with a configurable number of multiply-accumulates, and two DSPs (SHAVE-512) for optimal processing of custom deep learning operations. Global barriers and task FIFOs are also available for job synchronization and dispatch.
The Intel® Core™ Processor (Series 3) NPU comprises of 1 NCE Tiles, totaling 4k DPU INT8 MACs, 2 DSPs and 2.0 MB of associated near-compute memory.Below is the block diagram of NPU IP: