Intel® Core™ Processor (Series 3)
Formerly known as Wildcat Lake, Datasheet, Volume 1 of 2
Signal Description
| Signal Name | Type | Description |
|---|---|---|
| Intel® High Definition Audio Signals | ||
| GPP_D16/HDA_RST#/DMIC_CLK_A1 | O | Intel HD Audio Reset: Host H/W reset to internal and external codecs. |
| GPP_D11/HDA_SYNC/I2S0_SFRM | O | Intel HD Audio Sync: 48 kHz fixed rate frame sync to the codecs. |
| GPP_D10/HDA_BCLK/I2S0_SCLK | O | Intel HD Audio Bit Clock: Up to 24 MHz serial data clock generated by the Intel® HD Audio controller. |
| GPP_D12/HDA_SDO/I2S0_TXD | O | Intel HD Audio Serial Data Out: Serial TDM data output to the codecs. The serial output is double-pumped for a bit rate of up to 48 Mb/s. |
| GPP_D13/HDA_SDI0/I2S0_RXD | I/O | Intel HD Audio Serial Data In 0: Serial TDM data input from the two codec(s). The serial input is single-pumped for a bit rate of up to 24 Mb/s. These signals contain integrated Pull-down resistors, which are enabled while the primary well is powered. |
| GPP_D17/HDA_SDI1/DMIC_DATA1 | I/O | Intel HD Audio Serial Data In 1: Serial TDM data input from the two codec(s). The serial input is single-pumped for a bit rate of up to 24 Mb/s. These signals contain integrated Pull-down resistors, which are enabled while the primary well is powered. |
| I2S / PCM Interface | ||
| GPP_D10/HDA_BCLK/I2S0_SCLK | I/O | I2S / PCM serial bit clock 0: Serial bit clock used to control the timing of a transfer. Can be generated internally (Host mode) or taken from an external source (Device mode). |
| GPP_S02/SNDW3_DATA1/SNDW0_CLK/DMIC_CLK_A0/I2S1_SCLK | I/O | I2S / PCM serial bit clock 1:Serial bit clock is used to control the timing of a transfer. Can be generated internally (Host mode) or taken from an external source (Device mode). |
| GPP_S04/SNDW2_CLK/DMIC_CLK_A0/I2S2_SCLK | I/O | I2S / PCM serial bit clock 2: Serial bit clock is used to control the timing of a transfer. Can be generated internally (Host mode) or taken from an external source (Device mode). |
| GPP_D11/HDA_SYNC/I2S0_SFRM | I/O | I2S / PCM serial frame indicator 0: This signal indicates the beginning and the end of a serialized data word. Can be generated internally (Host mode) or taken from an external source (Device mode). |
| GPP_S03/SNDW3_DATA2/SNDW2A_DATA1/SNDW0_DATA0/DMIC_DATA0/I2S1_SFRM | I/O | I2S / PCM serial frame indicator 1: This signal indicates the beginning and the end of a serialized data word. Can be generated internally (Host mode) or taken from an external source (Device mode). |
| GPP_S05/SNDW2_DATA0/DMIC_DATA0/I2S2_SFRM | I/O | I2S / PCM serial frame indicator 2: This signal indicates the beginning and the end of a serialized data word. Can be generated internally (Host mode) or taken from an external source (Device mode). |
| GPP_D12/HDA_SDO/I2S0_TXD | O | I2S / PCM transmit data (serial data out)0: Serial data out line. Sample length is a function of the selected serial data sample size. |
| GPP_S00/SNDW3_CLK/I2S1_TXD | O | I2S / PCM transmit data (serial data out)1: Serial data out line. Sample length is a function of the selected serial data sample size. |
| GPP_S06/SNDW2_DATA1/SNDW1_CLK/DMIC_CLK_A1/I2S2_TXD | O | I2S / PCM transmit data (serial data out)2: Serial data out line. Sample length is a function of the selected serial data sample size. |
| GPP_D13/HDA_SDI0/I2S0_RXD | I | I2S / PCM receive data (serial data in)0: Serial data in line. Sample length is a function of the selected serial data sample size. |
| GPP_S01/SNDW3_DATA0/I2S1_RXD | I | I2S / PCM receive data (serial data in)1: Serial data in line. Sample length is a function of the selected serial data sample size. |
| GPP_S07/SNDW3_DATA3/SNDW2_DATA2/SNDW1_DATA0/DMIC_DATA1/I2S2_RXD | I | I2S / PCM receive data (serial data in)2: Serial data in line. Sample length is a function of the selected serial data sample size. |
| GPP_D09/I2S_MCLK1_OUT | O | I2S / PCM Host reference clock 0: This signal is the host reference clock that connects to an audio codec. |
| DMIC Interface | ||
| GPP_S02/SNDW3_DATA1/SNDW0_CLK/DMIC_CLK_A0/I2S1_SCLK or GPP_S04/SNDW2_CLK/DMIC_CLK_A0/I2S2_SCLK | O | Digital Mic Clock A0:Serial data clock generated by the HD Audio controller. The clock output frequency is up to 4.8 MHz. Duplication for clock pin (instance A) in case platform wanted to separate clock connection for left channel mic vs right channel mic. For the case of sharing single clock connection to both left and right channel mics, clock pin (instance A) should be used. |
| GPP_D16/HDA_RST#/DMIC_CLK_A1 or GPP_S06/SNDW2_DATA1 /SNDW1_CLK/DMIC_CLK_A1/I2S2_TXD | O | Digital Mic Clock A1:Serial data clock generated by the HD Audio controller. The clock output frequency is up to 4.8 MHz. Duplication for clock pin (instance A) in case platform wanted to separate clock connection for left channel mic vs right channel mic. For the case of sharing single clock connection to both left and right channel mics, clock pin (instance A) should be used. |
| GPP_S03/SNDW3_DATA2/SNDW2A_DATA1/SNDW0_DATA0/DMIC_DATA0/I2S1_SFRM or GPP_S05/SNDW2_DATA0/DMIC_DATA0/I2S2_SFRM | I | Digital Mic Data:Serial data input from the digital mic. |
| GPP_D17/HDA_SDI1/DMIC_DATA1 or GPP_S07/SNDW3_DATA3/SNDW2_DATA2/SNDW1_DATA0/DMIC_DATA1/I2S2_RXD | I | Digital Mic Data:Serial data input from the digital mic. |
| Mic Mute Interface | ||
| GPP_H03/MIC_MUTE | Mic Mute: Indicate the user privacy mode setting on the system | |
| GPP_H17/MIC_MUTE_LED | Mic Mute Led: Led to Indicate the user privacy mode setting in the system. | |
| SoundWire Interface | ||
| GPP_S02/SNDW3_DATA1/SNDW0_CLK/DMIC_CLK_A0/I2S1_SCLK | I/O | SoundWire0 Clock: Serial bit clock used to control the timing of a transfer. SoundWire3 Multilane Data1: To support multilane capability for high fidelity codecs |
| GPP_S03/SNDW3_DATA2/SNDW2A_DATA1/SNDW0_DATA0/DMIC_DATA0/I2S1_SFRM | I/O | SoundWire3 Multilane Data2: To support multilane capability for high fidelity codecs SoundWire2 Multilane Data1: To support multilane capability for high fidelity codecs SoundWire0 Data0: Serialized data line containing framing and data being transmitted/received. |
| GPP_S06/SNDW2_DATA1 /SNDW1_CLK/DMIC_CLK_A1/I2S2_TXD | I/O | SoundWire2 Multilane Data1: To support multilane capability for high fidelity codecs SoundWire1 Clock: Serial bit clock used to control the timing of a transfer. |
| GPP_S07/SNDW3_DATA3/SNDW2_DATA2/SNDW1_DATA0/DMIC_DATA1/I2S2_RXD | I/O | SoundWire3 Multilane Data3: To support multilane capability for high fidelity codecs SoundWire2 Multilane Data1: To support multilane capability for high fidelity codecs SoundWire1 Data0: Serialized data line containing framing and data being transmitted/received. |
| GPP_S04/SNDW2_CLK/DMIC_CLK_A0/I2S2_SCLK | I/O | SoundWire2 Clock: Serial bit clock used to control the timing of a transfer. |
| GPP_S05/SNDW2_DATA0/DMIC_DATA0/I2S2_SFRM | I/O | SoundWire2 Data0: Serialized data line containing framing and data being transmitted / received. |
| GPP_S00/SNDW3_CLK/I2S1_TXD | I/O | SoundWire3 Clock: Serial bit clock used to control the timing of a transfer. |
| GPP_S01/SNDW3_DATA0/I2S1_RXD | I/O | SoundWire3 Data0: Serialized data line containing framing and data being transmitted / received. |
| SNDW_RCOMP | A | SoundWire Resistor compensation. |