Feature Set

• 1 Neural Compute Engine Tile, where each tile consist of:
  • 2.0 MB CMX Memory
  • Two 512-bit ACT-SHAVEs
  • DPU (4K MACs)
• DMA Engine:
  • 2x 64B AXI Interface to DDR
  • Bit Compactor Compression unit for weights decompression and activation compression and decompression
  • Address Translation Prefetching capability in the DMA controller. A dedicated prefetch machine provides single-read accesses to pages at a configurable offset from the current transfer. All prefetch commands are carried on the read channel of the converged 64B AXI DMA data bus.
  • Address Patching capability for DRAM Accesses
• 256 KB of SHAVE L2 Cache for Data and Instruction shared between ACT-SHAVEs.
• Barriers for hardware and assisted task synchronization and pipelining
• Programmable HW FIFO Block for Work Descriptors and IPC
• Virtual Addressing for all resources used during Inference (Memory, Barriers, FIFOs and DMA/M2I Interrupt IDs)