PCIE_​A[4:1]_​TX_​N

PCIE_​A[4:1]_​TX_​P

O

PCI Express* Controller A Differential Transmit Pairs

These are the PCI Express* based outbound high-speed differential signals from PCIe Controller A

PCIE_​C[2:1]_​TX_​N

PCIE_​C[2:1]_​TX_​P

O

PCI Express* Controller B Differential Transmit Pairs

These are the PCI Express* based outbound high-speed differential signals from PCIe Controller C

PCIE_​A[4:1]_​RX_​N

PCIE_​A[4:1]_​RX_​P

I

PCI Express* Controller A Differential Receive Pairs

These are the PCI Express* based inbound high-speed differential signals for PCIe Controller A

PCIE_​C[2:1]_​RX_​N

PCIE_​C[2:1]_​RX_​P

I

PCI Express* Controller B Differential Receive Pairs

These are the PCI Express* based inbound high-speed differential signals for PCIe Controller C

PCIE_​A_​RCOMP

PCIE_​C_​RCOMP

A

PCI Express* Controllers A/C PHY Impedance Compensation Inputs

PCIE_​LINK_​DOWN

O

PCI Express* Link Down Debug Signal

PCIe link failure debug signal. PCIe Root Port(s) will assert this signal when a link down event occurs and is detected. For example when a link fails to train during an L1 sub-state exit event.