Intel® Core™ Processor (Series 3)
Formerly known as Wildcat Lake, Datasheet, Volume 1 of 2
| ID | Date | Version | Classification |
|---|---|---|---|
| 913965 | 05/19/2026 | 001 | Public |
Legal Disclaimer
Revision History
Introduction
Processor and Device IDs
Package Mechanical Specifications
Memory Mapping
Security Technologies
Intel Virtualization Technology
Instructions Set Enhancements
Intel® Neural Processing Unit (Intel® NPU)
Audio Voice and Speech
Power Management
Power Delivery
Thermal Management
System Clocks
Real Time Clock (RTC)
Memory
USB Type-C Sub System
Universal Serial Bus (USB)
PCI Express (PCIe)
Universal Flash Storage
Graphics
Display
Processor Sideband Signals
General Purpose Input and Output
Interrupt Timer Subsystem (ITSS)
Intel® Serial IO Inter-Integrated Circuit (I2C) Controllers
Intel® Serial IO Improved Inter-Integrated Circuit (I3C) Controllers
Gigabit Ethernet Controller
Connectivity Integrated (CNVi)
Controller Link
Integrated Sensor Hub (ISH)
System Management Interface and SMLink
Host System Management Bus (SMBus) Controller
Serial Peripheral Interface (SPI)
Enhanced Serial Peripheral Interface (eSPI)
Intel® Serial IO Generic SPI (GSPI) Controllers
Touch Host Controller (THC)
Intel® Serial IO Universal Asynchronous ReceiverTransmitter (UART) Controlle
Private Configuration Space Port ID
Testability and Monitoring
Security Technologies
Intel® Converged Boot Guard and TXT
Crypto Acceleration Instructions
Intel® Secure Key
Execute Disable Bit
Intel® Supervisor Mode Execution Protection (Intel® SMEP)
Intel® Supervisor Mode Access Protection (Intel® SMAP)
User Mode Instruction Prevention (UMIP)
Read Processor ID (RDPID)
Intel® System Resources Defense and Intel® System Security Report
Intel® Total Memory Encryption - Multi-Key
Control-flow Enforcement Technology (Intel® CET)
BIOS Guard
Intel® Platform Trust Technology
Linear Address Space Separation (LASS)
Intel® Total Storage Encryption (Intel® TSE)
Security Firmware Engines
Audio Voice and Speech
Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities
Audio DSP Capabilities
Intel® High Definition Audio Interface Capabilities
Direct Attached Digital Microphone (PDM) Interface
USB Audio Offload Support
I2S PCM Interface
Intel® Display Audio Interface
MIPI® SoundWire Interface
Signal Description
Integrated Pull-Ups and Pull-Downs
IO Signal Planes and States
Power and Performance Technologies
Intel® Thread Director
Intel® Smart Cache Technology
P-core LP E-core Level 0, Level 1 and Level 2 Caches
Ring Interconnect
Intel® Hybrid Technology
Intel® Turbo Boost Technology 2.0
Intel® Adaptive Boost Technology
Intel System Agent Enhanced SpeedStep ® Technology
Enhanced Intel SpeedStep® Technology
Intel® Speed Shift Technology
Intel® Advanced Vector Extensions 2 (Intel® AVX2)
Intel® 64 Architecture x2APIC
Intel® Dynamic Tuning Technology (Intel® DTT)
Cache Line Write Back (CLWB)
User Mode Wait Instructions
Thermal Management Features
Skin Temperature Control (STC)
Adaptive Thermal Monitor
Digital Thermal Sensor
FORCEPR# Signal
FORCEPR Demotion
Voltage Regulator Protection using FORCEPR#
Thermal Solution Design and FORCEPR Behavior
Low-Power States and FORCEPR Behavior
THERMTRIP Signal
Critical Temperature Detection
System Memory Interface
Processor SKU Support Matrix
Supported Memory Modules and Devices
System Memory Timing Support
Memory Controller (MC)
System Memory Frequency
Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)
Data Scrambling
Data Swapping
LPDDR5x CMDADD Ascending and Descending
DDR IO Interleaving
DRAM Clock Generation
DRAM Reference Voltage Generation
Data Swizzling
Error Correction With Standard RAM
Post Package Repair (PPR)
RFM
In-Memory Analytics Accelerator
Signal Description
| Signal Name | Type | Description |
|---|---|---|
| DBG_PMODE | O | ITP Power Mode Indicator. This signal is used to transmit processor and power/reset information to the Debugger. |
| PRDY# | O | Probe Mode Ready: PRDY# is a processor output used by debug tools to determine processor debug readiness |
| PREQ# | IOD | Probe Mode Request: PREQ# is used by debug tools to request debug operation of the processor. |
| SOC JTAG Signals | ||
| SOC_JTAG_TCK | I/O | Test Clock Input (TCK): The test clock input provides the clock for the JTAG test logic. |
| SOC_JTAG_TMS | IOD | Test Mode Select (TMS): The signal is decoded by the Test Access Port (TAP) controller to control test operations. |
| SOC_JTAG_TDI | IOD | Test Data Input (TDI): Serial test instructions and data are received by the test logic at TDI. |
| SOC_JTAG_TDO | IOD | Test Data Output (TDO): TDO is the serial output for test instructions and data from the test logic defined in this standard. |
| SOC_JTAG_TRST# | I/O | Test Reset(TRST): Resets the Test Access Port (TAP) logic. This signal should be driven low during power on Reset. |
| Breakpoint and Performance Monitor Signals | ||
| BPM[0] | I/O | Breakpoint and Performance Monitor Signals(BPM): Outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. |
| BPM[1] | I/O | Breakpoint and Performance Monitor Signals(BPM): Outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. |
| Boot Halt Signal | ||
| BOOTHALT# | IOD | Boot Halt : This signal is used for platform boot halt. |