Intel® Core™ Processor (Series 3)

Formerly known as Wildcat Lake, Datasheet, Volume 1 of 2

ID Date Version Classification
913965 05/19/2026 001 Public
Document Table of Contents
RFM

IO Signal Planes and States

I/O Signal Planes and States

Signal Name

Power Plane

During Reset1

Immediately After Reset1

S4/S5

High Definition Audio Interface

HDA_​RST#

Primary

Asserted

Asserted

Asserted

HDA_​SYNC

Primary

Internal Pull-down

Driven Low

Internal Pull-down

HDA_​BCLK

Primary

Driven Low

Driven Low

Driven Low

HDA_​SDO

Primary

Internal Pull-down

Driven Low

Internal Pull-down

HDA_​SDI[1:0]

Primary

Internal Pull-down

Internal Pull-down

Internal Pull-down

DMIC Interface

DMIC_​CLK_​A[1:0]

Primary

Driven Low

Driven Low

Driven Low

DMIC_​DATA[1:0]

Primary

Internal Pull-down

Internal Pull-down

Internal Pull-down

SoundWire Interface

SNDW[1:0]_​DATA0

Primary

Internal Pull-down

Internal Pull-down

Internal Pull-down

SNDW2_​DATA[2:0]

Primary

Internal Pull-down

Internal Pull-down

Internal Pull-down

SNDW3_​DATA[3:0]

Primary

Internal Pull-down

Internal Pull-down

Internal Pull-down

SNDW[3:0]_​CLK

Primary

Driven Low

Driven Low

Driven Low

MIC_​MUTE

Primary

Driven Low

Driven Low

Driven Low

MIC_​MUTE_​LED

Primary

Driven Low

Driven Low

Driven Low

Note:Reset reference for primary well pins is RSMRST#.