PCIe Max Rate

4.0

4.0

L1 Sub-States (L1.0, L1.1, L1.2)

Yes

Yes

L0s Link State (RX/TX)

Yes

Yes

S4/S5 Sleep States (Sx)

Yes

Yes

Common Clock Mode

Yes

Yes

Separate Reference Clock with Independent SSC (SRIS)

No

No

Separate Reference Clock with No SSC (SRNS)

No

No

Precision Time Management (PTM)

Yes

Yes

Advanced Error Reporting (AER)

Yes

Yes

End-to-End Lane Reversal

Yes

Yes

Latency Tolerance Reporting (LTR)

Yes

Yes

LTR Programmable by OS

No

No

PCIe TX Half Swing

No

No

PCIe TX Full Swing

Yes

Yes

Run Time D3 (RTD3)

Yes

Yes

RTD3 through PFET_​EN to remove power from PCIe Device

Yes

Yes

Access Control Services (ACS)

Yes

Yes

Alternative Routing-ID Interpretation (ARI)

Yes

Yes

Port 8xh I/O Cycle Decode Forwarding

Yes

Yes

Lane Polarity Inversion

Yes

Yes

PCIe Controller Root Port Hot-Plug via CLKREQ#

Yes

Yes

Downstream Port Containment (DPC)

No

No

Enhanced Downstream Port Containment (eDPC)

No

No

Virtual Channel (VC)

0/1

0/1

NVMe Cycle Router

No

No

Volume Management Device (Intel® VMD)

No

No

RAID[0] and RAID[1] Mode Support

No

No

RAID[5] and RAID[10] Mode Support

No

No

PCIe Controller (PC) Root Port (RP)

Peer-2-Peer (P2P) Mem Write Transactions

RPs between PCA and PCC= No

RPs within PCA and within PCC = Yes

PCIe Controller (PC) Root Port (RP)

Peer-2-Peer (P2P) Mem Read Transactions

No

PCIe Controller (PC) Root Port (RP)

Peer-2-Peer (P2P) MCTP VDM Transactions

RPs within PCA or within PCC= Yes

RPs between PCA/C = Yes

Flattening Portal Bridge (FPB)

No

No

PCIe Root Port Initiated Dynamic Width Change

No

No

PCIe Root Port Initiated Dynamic Speed Change

Yes

Yes

End Point Device Initiated Dynamic Width Change

Yes

Yes

End Point Device Initiated Dynamic Speed Change

Yes

Yes

Max Payload Size (MPS)

256B

256B