SPI0 Support for TPM

The processorSPI0 flash controller supports a discrete TPM on the platform via its dedicated SPI0_​CS2# signal. The platform must have no more than 1 TPM.

The SPI0 controller default reset frequency is 20 MHz, but a valid soft strap setting can override this for required operating frequency. The SPI0 TPM device must support a 20 MHz clock and should be able to operate within the 15-20 MHz range. Support for frequencies above 20 MHz is optional. The SPI0 controller supports a maximum operating frequency of 48 MHz for dTPM.

TPM requires the support for the interrupt routing. However, the TPM’s interrupt pin is routed to the processor interrupt configurable GPIO pin. Thus, TPM interrupt is completely independent from the SPI0 controller.