Intel® Core™ Ultra 200V Series Processors CFG and MEM Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 831649 | 03/30/2026 | 001 | Public |
(DDR_THERM_CONTROL_0_0_0_MCHBAR_PCU) – Offset 5e88
Controls the thermal throttling of DDR/SoC based on DDR temperature.
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31:9 | 0h | RO | Reserved |
| 8 | 0h | RW | (ENABLE) Enable/Disable of thermal throttling of iMC and other SoC components based on MR4 reading. |
| 7:0 | 0h | RW | (TARGET_TEMPERATURE) Target DDR temperature in units of DRAM MR4. SoC will apply throttling action in case this temperature exceeded. |