31:20

0h

RW/L

(TopOfDPR)

Top address + 1 of DPR. This is the base of TSEG. Bits 19:0 of the BASE reported here are 0x0_​0000.

19:12

0h

RO

Reserved

11:4

0h

RW/L

(DPRSIZE)

This is the size of memory, in MB, that will be protected from DMA accesses. A value of 0x00 in this field means no additional memory is protected. The maximum amount of memory that will be protected is 255 MB.
The amount of memory reported in this field will be protected from all DMA accesses, including translated CPU accesses and graphics. The top of the protected range is the BASE of TSEG -1.
Note: If TSEG is not enabled, then the top of this range becomes the base of stolen graphics, or ME stolen space or TOLUD, whichever would have been the location of TSEG, assuming it had been enabled.
The DPR range works independently of any other range, including the NoDMA.TABLE protection or the PMRC checks in VTd, and is done post any VTd translation or Intel TXT NoDMA lookup. Therefore incoming cycles are checked against this range after the VTd translation and faulted if they hit this protected range, even if they passed the VTd translation or were clean in the NoDMA lookup.
All the memory checks are ORed with respect to NOT being allowed to go to memory. So if either PMRC, DPR, NoDMA table lookup, NoDMA.TABLE.PROTECT OR a VTd translation disallows the cycle, then the cycle is not allowed to go to memory. Or in other words, all the above checks must pass before a cycle is allowed to DRAM.

3

0h

RO

Reserved

2

0h

RW/L

(EPM)

This field controls DMA accesses to the DMA Protected Range (DPR) region.
0: DPR is disabled
1: DPR is enabled. All DMA requests accessing DPR region are blocked.
HW reports the status of DPR enable/disable through the PRS field in this register. When this bit change, one must have to wait till the status (PRS) has updated before changing it again.

1

0h

RW/L

(PRS)

This field indicates the status of DPR.
0: DPR protection disabled
1: DPR protection enabled

0

0h

RW/L

(LOCK)

All bits which may be updated by SW in this register are locked down when this bit is set.