63:62

0h

RO

Reserved

61:46

0h

RO/V/P

sa perf status0 (SA_​VOLTAGE)

This register holds the System Agent voltage. In dies in which SA volatge is connected to external VR then this field is not supported.

45:41

2h

RO/V

sa perf status0 (SYSTEM_​CACHE_​DIV_​DENOMINATOR)

System Cache clock value, represented as the Qclk divider denominator.
This field is relevant for both SysC0clk and SysC1clk.

40:28

0h

RO

Reserved

27:20

0h

RO/V

sa perf status0 (IPU_​PS_​RATIO)

IPU processing system (PS) ratio in 25MHz granularity for FLL mode (default).

19:12

0h

RO/V

sa perf status0 (IPU_​IS_​RATIO)

IPU input system (IS) ratio in 16.667MHz. This ratio is translated to clock divider by CCU.

11:10

0h

RO/V

sa perf status0 (GEAR)

Memory Gear:
0: Gear1
1: Gear2
2: Gear4

9:2

0h

RO/V

sa perf status0 (QCLK_​RATIO)

DDR QCLK RATIO. Reference is granularity of 33.33MHz.
Note1: The ratio is valid only post MRC training
Note2: The update of this field is not too tight meaning first the PLL is locked and then the ratio is updated

1:0

0h

RO/V

sa perf status0 (LAST_​DE_​WP_​REQ_​SERVED)

Last DE workpoint request served by Pcode