Intel® Core™ Ultra 200V Series Processors CFG and MEM Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 831649 | 03/30/2026 | 001 | Public |
DLVR RFI/EMI Control Register (RFI_EMI_CONTROL_0_0_0_MCHBAR_PCU) – Offset 5a08
DLVR RFI/EMI Control Register
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31:10 | 0h | RO | Reserved |
| 9:8 | 0h | RW | RFI_FREQ_SELECT field (RFI_FREQ_SELECT) Sets pll clock frequency in MHz - per WiFi driver request. Targeting 2 frequencies: 2227.2 and 2140 |
| 7 | 0h | RW | FREQ_HOPPING_ENABLE field (FREQ_HOPPING_ENABLE) When set, Freq hopping enabled. |
| 6 | 0h | RW | FREQ_SSC_SPREAD_SPEC_CONTROL_LOCK field (FREQ_SSC_SPREAD_SPEC_CONTROL_LOCK) Spread spectrum control lock |
| 5 | 0h | RW | FREQ_SSC_MODE field (FREQ_SSC_MODE) SSC Mode |
| 4:0 | 0h | RW | FREQ_SSC_SPRD field (FREQ_SSC_SPRD) Sets pll spectrum spread percentage |