63:32

0h

RO

Reserved

31:24

0h

RW/V

Threshold on Counter Increment (thresh)

Threshold is used, along with the invert bit, to compare against the incoming increment value that will be added to the counter.
For events that increment by more than 1 per cycle, if the threshold is set to a value greater than 1, the data register will accumulate instances in which the event increment is >= threshold.

23

0h

RW/V

Invert comparison against Threshold (invert)

0 - comparison will be: is event increment >= threshold
1 - comparison is inverted: is event increment < threshold

22:21

0h

RO

Reserved

20

0h

RW/V

Freeze On Overflow (frz_​on_​ov)

When an overflow is detected from this register, a PMON overflow message is sent to the global control.
This bit will tell the global control whether it should assert the global freeze for all counters in the same domain.

19

0h

RO

Reserved

18

0h

RW/V

Edge Detect (edge_​det)

When set to 1, rather than measuring the event in each cycle it is active, the corresponding counter will increment when a 0 to 1 transition (i.e. rising edge) is detected.
When 0, the counter will increment in each cycle that the event is asserted.

17

0h

RW/1S/V

Reset Counter (rst)

When set to 1, the corresponding counter will be cleared to 0.

16

0h

RO

Reserved

15:8

0h

RW/V

Unit Mask (umask)

For additional IP specific encoding space

7:0

0h

RW/V

Event Select (ev_​sel)

field to select which of the available events should be recorded in the paired data register.