63:40

0h

RO

Reserved

39:32

8h

RW

ACT to Write CAS Delay - tRCDw (tRCDW)

Holds DDR timing parameter tRCDW, which is tRCD for writes in LPDDR5x. ACT to CAS (WR) same bank minimum delay in tCK (WCK for LPDDR5) cycles. Must be programmed equal to tRCD field when using a non-LPDDR5 config. Supported range is 8-59.

31:30

0h

RO

Reserved

29:22

8h

RW

ACT to CAS Delay - tRCD (tRCD)

Holds DDR timing parameter tRCD. ACT to CAS (RD) same bank minimum delay in tCK (WCK for LPDDR5) cycles. Supported range is 8-59.

21:15

4h

RW

ACT to ACT Different Bank Group Delay - tRRD_​dg (tRRD_​dg)

Holds DDR timing parameter tRRD. ACT to ACT (different bank group in DDR5) minimum delay in tCK (WCK for LPDDR5) cycles. Supported range is 4-32.

14:9

4h

RW

ACT to ACT Same Bank Group Delay - tRRD_​sg (tRRD_​sg)

Holds DDR timing parameter tRRD/tRRD_​L. For LPDDR program tRRD, for DDR5 program tRRD_​L. ACT to ACT (same bank group in DDR5) minimum delay in tCK (WCK for LPDDR5) cycles. Supported range is 4-32.

8:0

10h

RW

Four ACT Window - tFAW (tFAW)

Holds DDR timing parameter tFAW (four activates window). In tCK (WCK for LPDDR5) cycles. Supported range is 16-88.