Intel® Core™ Ultra 200V Series Processors CFG and MEM Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 831649 | 03/30/2026 | 001 | Public |
PCIe Device Control Status (DEVCTRLSTAT) – Offset 48
PCIE Device Status Register
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31:22 | 0h | RO | Reserved |
| 21 | 0h | RO/V | Txn Pending Field (TXN_PENDING) Transaction Pending bit |
| 20 | 0h | RO | Aux Power Det Field (AUX_PWR_DETECTED) Aux Power Detected. Always tied to 0 |
| 19 | 0h | RW/1C | Ur Field (UR_DETECTED) Unsupported Request Detected |
| 18 | 0h | RW/1C | Fatal Error Det Field (FER_DETECTED) Fatal Error Detected |
| 17 | 0h | RW/1C | Non Fatal Err Det Field (NFER_DETECTED) Non Fatal Error Detected |
| 16 | 0h | RW/1C | Correctable Error Det Field (CER_DETECTED) Correctable Error Detected |
| 15 | 0h | WO | Initiate Flr Field (INITIATE_FLR) Initiate Function Level Reset |
| 14:12 | 2h | RW | Max Read Request Size Field (MAX_RD_REQ_SIZE) Max Read Request Size |
| 11 | 0h | RW | Enable No Snoop Field (EN_NS) Enable No Snoop |
| 10 | 0h | RO | Aux Power Det Field (AUX_PWR_PM_EN) Aux Power Enable |
| 9 | 0h | RO | Phantom Function En Field (PHANTOM_FUNC_EN) Phantom Function Enable. Not support by Bridge |
| 8 | 0h | RW | Etf En Field (ETF_EN) Extended Tag Field Enable |
| 7:5 | 0h | RW | Max Payload Size Field (MAX_PL_SIZE) Maximum Payload Size |
| 4 | 1h | RW | Enable Relaxed Ordering Field (EN_RO) Enable Relaxed Ordering |
| 3 | 0h | RW | Ur Reporting En Field (URR_EN) Unsupported Request Reporting Enable |
| 2 | 0h | RW | Fatal Err Reporting En Field (FER_EN) Fatal Error Reporting Enable |
| 1 | 0h | RW | Non Fatal Err Reporting En Field (NFER_EN) Non Fatal Error Reporting Enable |
| 0 | 0h | RW | Correctable Error Reporting En Field (CER_EN) Correctable Error Reporting Enable |