Intel® Core™ Ultra 200V Series Processors CFG and MEM Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 831649 | 03/30/2026 | 001 | Public |
(PLATFORM_TEMPERATURE_CONTROL_3_0_0_0_MCHBAR) – Offset 5b30
Provides control over limitation of CPU due to platform temperature
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 63:32 | 0h | RO | Reserved |
| 31:24 | 0b | RW | (TEMPERATURE_OVERRIDE) Allows SW to override the input temperature. Pcode will use this value instead of the sensor temperature. EC control is not impacted. Units: 0.5C. |
| 23:16 | 0b | RW | (MIN_PERFORMANCE_LEVEL) Minimum Performance level below which the STC limit will not throttle. 0 - all levels of throttling allowed incl. survivability actions. 256 - no throttling allowed. |
| 15:13 | 0h | RO | Reserved |
| 12 | 0b | RW | (TEMPERATURE_OVERRIDE_EN) When set, Pcode will use TEMPERATURE_OVERRIDE values instead of reading from corresponding sensor. |
| 11:9 | 0b | RW | (GAIN) Sets the aggressiveness of control loop |
| 8 | 0b | RW | (ENABLE) Enables the control. |
| 7:0 | 0b | RW | (TARGET_TEMP) Target temperature limit to which the control mechanism is regulating. Units: 0.5C. |