63:58

10h

RW

clock start to first command post FSP on LPDDR5 (tckfspx)

Time from DRAM clock start to power down exit (LP5) on post FSP, on SAGV SRX. Value programmed is in WCK/tCK clocks.
This replaces tCKCSH (tCKCKEH) For LPDDR5 after FSP command (SAGV SRX).

57

0h

RO

Reserved

56:52

0h

RW

Valid Clock Requirement after Power Down Entry - tCSLCK (tCSLCK)

Holds the JEDEC Timing Parameter tCSLCK in WCK, only applicable when wck_​config_​0_​0_​0_​mchbar.lp5_​wck_​mode is configured to either AS_​MANUAL or AS_​SAFE modes.
Valid WCK Clock Requirement after PDE or SRE. When sending WCK SYNC OFF CAS due to PDE or SRE, the MC needs to ensure the tCSLCK timing is satisfied before asserting the ISpid_​WCkStop SPID wire.

51:47

0h

RW

Valid Clock Requirement after WCK Stop - tWCKSTOP (tWCKSTOP)

Holds the JEDEC Timing Parameter tWCKSTOP in WCK, only applicable when wck_​config_​0_​0_​0_​mchbar.lp5_​wck_​mode is configured to AS_​MANUAL mode.
Valid WCK Clock Requirement after CAS. When sending WCK SYNC OFF CAS due to IDLE, the MC needs to ensure the tWCKSTOP timing is satisfied before asserting the ISpid_​WCkStop SPID wire.

46:20

0h

RO

Reserved

19:10

0h

RW

WR WCK ASYNC GAP (wr_​wck_​async_​gap)

Specifies the minimum gap between write to read/write command not requiring async command (specified in WCK).
When the gap is bigger than the value in this register, MC issues auto sync command before sending the second rd/wr command.
The value to be programmed is (CWL + BL/n_​max + RD(tWCKPST/tCK)).

9:0

0h

RW

RD WCK ASYNC GAP (rd_​wck_​async_​gap)

Specifies the minimum gap between read to read/write command not requiring async command (specified in WCK).
When the gap is bigger than the value in this register, MC issues auto sync command before sending the second rd/wr command.
The value to be programmed is (RL + BL/n_​max + RD(tWCKPST/tCK)).