VTDs Range Base Address Register (VTDBAR_0_0_0_MCHBAR_NCU) – Offset 5410 - 001 - ID:831649 | Intel® Core™ Ultra 200V Series Processors CFG and MEM Registers

Introduction
Processor Configuration Register Definitions and Address Ranges
D0:F0 Host Bridge and DRAM Controller - GTTMMADR
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 1)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 1)
- VTDs Range Base Address Register (VTDBAR_0_0_0_MCHBAR_NCU)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 2)
- CAPID0_F PCI (CAPID0_F_0_0_0_PCI)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 3)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 4)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management
D0:F0 Host Bridge and DRAM Controller - SAFBAR PMON Registers Part1
D0:F0 Host Bridge and DRAM Controller - SAFBAR PMON Registers Part2
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR
D10:F0 Platform Monitoring Technology (PMT) Registers
D11:F0 Vision Processing Unit
D2:F0 Processor Graphics
D4:F0 Dynamic Tuning Technology
D5:F0 Image Processing Unit

VTDs Range Base Address Register (VTDBAR_0_0_0_MCHBAR_NCU) – Offset 5410

This is the base address for the VTDs configuration space. There is no physical memory within this 512KB window that can be addressed. The 512KB reserved by this register does not alias to any PCI 2.3 compliant memory mapped space. On reset, the VTDs configuration space is disabled and must be enabled by writing a 1 to the relevant VTDBAREN[7:0] bit.
All the bits in this register are locked in LT mode.
BIOS programs this register after which the register cannot be altered.

Bit Range	Default	Access	Field Name and Description
63:38	0h	RO	Reserved
37:19	0h	RW	VTD Base Address (VTDBAR) This field corresponds to bits x to 19 of the base address VTD configuration space. BIOS will program this register resulting in a base address for a 512KB block of contiguous memory address space. This register ensures that a naturally aligned 512KB space is allocated within the first 4TB of addressable memory space. System Software uses this base address to program the VTD register set. All the Bits in this register are locked in LT mode.
18:8	0h	RO	Reserved
7:0	0h	RW	VTD BAR Enable (VTDBAREN) Enable bit per 64KB 0: The corresponding 64KB range is disabled and does not claim any memory 1: The corresponding 64KB range memory mapped accesses are claimed and decoded appropriately This bit will remain 0 if VTd capability is disabled.

D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 2)

D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 1) D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 2)