31:26

0h

RO

Reserved

25

0h

RW/L

DRAM ECC Disable (ECCDIS)

0: ECC is supported
1: ECC is not supported

24

0h

RW/L

Force DRAM ECC Enable (FDEE)

0: DRAM ECC optional via software.
1: DRAM ECC enabled. MCHBAR C0MISCCTL bit [0] and C1MISCCTL bit [0] are forced to 1 and Read-Only.
Note that FDEE and ECCDIS must not both be set to 1.

23

0h

RW/L

VT-d Disable (VTDD)

0: VT-d is supported
1: VT-d is not supported

22:21

0h

RO

Reserved

20:19

0h

RW/L

DRAM Maximum Size per Channel (DDRSZ)

This field defines the maximum allowed memory size per channel.
0: Unlimited (64GB per channel)
1: Maximum 8GB per channel
2: Maximum 4GB per channel
3: Maximum 2GB per channel

18

0h

RO

Reserved

17

0x0

RW/L

DRAM 1N Timing Disable (D1NM)

0: Part is capable of supporting 1n mode timings on the DDR interface.
1: Part is not capable of supporting 1n mode. Only supported timings are 2n or greater.

16:15

0h

RO

Reserved

14

0h

RW/L

2 DIMMs Per Channel Enable (DDPCD)

Allows Dual Channel operation but only supports 1 DIMM per channel.
0: 2 DIMMs per channel enabled
1: 2 DIMMs per channel disabled. This setting hardwires bits 2 and 3 of the rank population field for each channel to zero. (MCHBAR offset 260h, bits 22-23 for channel 0 and MCHBAR offset 660h, bits 22-23 for channel 1)

13

0h

RW/L

X2APIC Enable (X2APIC_​EN)

Extended Interrupt Mode.
0b: Hardware does not support Extended APIC mode.
1b: Hardware supports Extended APIC mode.

12

0h

RW/L

Dual Memory Channel Support (PDCD)

0: Capable of Dual Channel
1: Not Capable of Dual Channel - only single channel capable.

11

0h

RO

Reserved

10

0h

RW/L

DID0 Override Enable (DID0OE)

0: Disable ability to override DID0 - For production
1: Enable ability to override DID - For debug and samples only

9:8

0h

RO

Reserved

7:4

0h

RW/L

Compatibility Revision ID (CRID)

Compatibility Revision ID

3

0h

RW/L

Memory Overclocking (DDR_​OVERCLOCK)

Memory Overclocking is enabled.
When supported, memory can be trained at higher than default maximum frequencies.
0: Memory Overclocking is not supported
1: Memory Overclocking is supported

2:0

0h

RO

Reserved