63:51

200h

RW

Self Refresh Exit to Command Requiring DLL Lock - tXSDLL (tXSDLL)

Delay between DDR SR exit and the first command that requires DRAM DLL lock (i.e RD/WR from DDR).

50:47

0h

RO

Reserved

46:40

20h

RW

Minimum Self Refresh Residency - tSR (tSR)

Minimum residency time in self refresh state.
In LP5 and LP4 it is tSR
In DDR5 it is tCSL

39:32

50h

RW

PHY SRX Delay for LPMode4 (lpmode4_​srx_​delay)

This timing paramether describe a max value in DCLKs of dfi_​lp_​ctl->0 to ddrphy sending SRX to DRAM at lpmode4 exit. delay should be few SBCLKs latency in ddrphy + TXP +TCSH.

31:13

0h

RO

Reserved

12:0

0h

RW

Self Refresh Exit Time - tXSR (tXSR)

Exit self refresh to valid commands delay.
In LP4 configure this parameter for tXSR or tXSR abort in terms of tCK (WCK for LPDDR5) cycles if used.